OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [opcodes/] [or32-opc.c] - Blame information for rev 827

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Table of opcodes for the OpenRISC 1000 ISA.
2 225 jeremybenn
   Copyright 2002, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
3 24 jeremybenn
   Contributed by Damjan Lampret (lampret@opencores.org).
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
 
22
/* We treat all letters the same in encode/decode routines so
23
   we need to assign some characteristics to them like signess etc.  */
24
#include <string.h>
25
#include <stdio.h>
26
#include <stdlib.h>
27
#include "safe-ctype.h"
28
#include "ansidecl.h"
29
#ifdef HAVE_CONFIG_H
30
# include "config.h"
31
#endif
32 225 jeremybenn
#ifdef HAS_EXECUTION
33
# ifdef HAVE_INTTYPES_H
34
#  include <inttypes.h> /* ...but to get arch.h we need uint{8,16,32}_t... */
35
# endif
36
# include "port.h"
37
# include "arch.h" /* ...but to get abstract.h, we need oraddr_t... */
38
# include "abstract.h" /* To get struct iqueue_entry... */
39
# include "debug.h" /* To get debug() */
40
#endif
41 24 jeremybenn
#include "opcode/or32.h"
42
 
43
const struct or32_letter or32_letters[] =
44
{
45
  { 'A', NUM_UNSIGNED },
46
  { 'B', NUM_UNSIGNED },
47
  { 'D', NUM_UNSIGNED },
48
  { 'I', NUM_SIGNED },
49
  { 'K', NUM_UNSIGNED },
50
  { 'L', NUM_UNSIGNED },
51
  { 'N', NUM_SIGNED },
52
  { '0', NUM_UNSIGNED },
53
  { '\0', 0 }     /* Dummy entry.  */
54
};
55
 
56
/* Opcode encoding:
57
   machine[31:30]: first two bits of opcode
58
                   00 - neither of source operands is GPR
59
                   01 - second source operand is GPR (rB)
60
                   10 - first source operand is GPR (rA)
61
                   11 - both source operands are GPRs (rA and rB)
62
   machine[29:26]: next four bits of opcode
63
   machine[25:00]: instruction operands (specific to individual instruction)
64
 
65
  Recommendation: irrelevant instruction bits should be set with a value of
66
  bits in same positions of instruction preceding current instruction in the
67
  code (when assembling).  */
68
 
69
#ifdef HAS_EXECUTION
70 225 jeremybenn
# if SIMPLE_EXECUTION
71
#  define EFN &l_none
72
#  define EF(func) &(func)
73
#  define EFI &l_invalid
74
# elif COMPLEX_EXECUTION
75
#  define EFN "l_none"
76
#  define EFI "l_invalid"
77
#  ifdef __GNUC__
78
#   define EF(func) #func
79
#  else
80
#   define EF(func) "func"
81
#  endif
82
# else /* DYNAMIC_EXECUTION */
83
#  define EFN &l_none
84
#  define EF(func) &(gen_ ##func)
85
#  define EFI &gen_l_invalid
86
# endif
87
#else /* HAS_EXECUTION */
88
# define EFN &l_none
89
# define EF(func) EFN
90
# define EFI EFN
91 24 jeremybenn
#endif /* HAS_EXECUTION */
92
 
93 225 jeremybenn
const struct or32_opcode or32_opcodes[] = {
94
  { "l.j",        "N",           "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY, it_jump },
95
  { "l.jal",      "N",           "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY, it_jump },
96
  { "l.bnf",      "N",           "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
97
  { "l.bf",       "N",           "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
98
  { "l.nop",      "K",           "00 0x5  01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0, it_nop },
99
  { "l.movhi",    "rD,K",        "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0, it_movimm },
100
  { "l.macrc",    "rD",          "00 0x6  DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0, it_mac },
101
  { "l.sys",      "K",           "00 0x8  00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0, it_exception },
102
  { "l.trap",     "K",           "00 0x8  01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0, it_exception },
103
  { "l.msync",    "",            "00 0x8  10000 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
104
  { "l.psync",    "",            "00 0x8  10100 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
105
  { "l.csync",    "",            "00 0x8  11000 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
106
  { "l.rfe",      "",            "00 0x9  ----- ----- ---- ---- ---- ----", EF(l_rfe), 0, it_exception },
107
  { "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0",   EFI, 0, it_unknown },
108
  { "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1",   EFI, 0, it_unknown },
109
  { "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2",   EFI, 0, it_unknown },
110
  { "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3",   EFI, 0, it_unknown },
111
  { "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4",   EFI, 0, it_unknown },
112
  { "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5",   EFI, 0, it_unknown },
113
  { "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6",   EFI, 0, it_unknown },
114
  { "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7",   EFI, 0, it_unknown },
115
  { "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8",   EFI, 0, it_unknown },
116
  { "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9",   EFI, 0, it_unknown },
117
  { "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA",   EFI, 0, it_unknown },
118
  { "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB",   EFI, 0, it_unknown },
119
  { "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0",   EFI, 0, it_unknown },
120
  { "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1",   EFI, 0, it_unknown },
121
  { "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2",   EFI, 0, it_unknown },
122
  { "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3",   EFI, 0, it_unknown },
123
  { "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4",   EFI, 0, it_unknown },
124
  { "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5",   EFI, 0, it_unknown },
125
  { "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6",   EFI, 0, it_unknown },
126
  { "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7",   EFI, 0, it_unknown },
127
  { "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8",   EFI, 0, it_unknown },
128
  { "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9",   EFI, 0, it_unknown },
129
  { "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA",   EFI, 0, it_unknown },
130
  { "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB",   EFI, 0, it_unknown },
131
  { "lv.add.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0",   EFI, 0, it_unknown },
132
  { "lv.add.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1",   EFI, 0, it_unknown },
133
  { "lv.adds.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2",   EFI, 0, it_unknown },
134
  { "lv.adds.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3",   EFI, 0, it_unknown },
135
  { "lv.addu.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4",   EFI, 0, it_unknown },
136
  { "lv.addu.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5",   EFI, 0, it_unknown },
137
  { "lv.addus.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6",   EFI, 0, it_unknown },
138
  { "lv.addus.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7",   EFI, 0, it_unknown },
139
  { "lv.and",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8",   EFI, 0, it_unknown },
140
  { "lv.avg.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9",   EFI, 0, it_unknown },
141
  { "lv.avg.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA",   EFI, 0, it_unknown },
142
  { "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0",   EFI, 0, it_unknown },
143
  { "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1",   EFI, 0, it_unknown },
144
  { "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2",   EFI, 0, it_unknown },
145
  { "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3",   EFI, 0, it_unknown },
146
  { "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4",   EFI, 0, it_unknown },
147
  { "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5",   EFI, 0, it_unknown },
148
  { "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6",   EFI, 0, it_unknown },
149
  { "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7",   EFI, 0, it_unknown },
150
  { "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8",   EFI, 0, it_unknown },
151
  { "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9",   EFI, 0, it_unknown },
152
  { "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA",   EFI, 0, it_unknown },
153
  { "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB",   EFI, 0, it_unknown },
154
  { "lv.madds.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4",   EFI, 0, it_unknown },
155
  { "lv.max.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5",   EFI, 0, it_unknown },
156
  { "lv.max.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6",   EFI, 0, it_unknown },
157
  { "lv.merge.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7",   EFI, 0, it_unknown },
158
  { "lv.merge.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8",   EFI, 0, it_unknown },
159
  { "lv.min.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9",   EFI, 0, it_unknown },
160
  { "lv.min.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA",   EFI, 0, it_unknown },
161
  { "lv.msubs.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB",   EFI, 0, it_unknown },
162
  { "lv.muls.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC",   EFI, 0, it_unknown },
163
  { "lv.nand",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD",   EFI, 0, it_unknown },
164
  { "lv.nor",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE",   EFI, 0, it_unknown },
165
  { "lv.or",      "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF",   EFI, 0, it_unknown },
166
  { "lv.pack.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0",   EFI, 0, it_unknown },
167
  { "lv.pack.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1",   EFI, 0, it_unknown },
168
  { "lv.packs.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2",   EFI, 0, it_unknown },
169
  { "lv.packs.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3",   EFI, 0, it_unknown },
170
  { "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4",   EFI, 0, it_unknown },
171
  { "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5",   EFI, 0, it_unknown },
172
  { "lv.perm.n",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6",   EFI, 0, it_unknown },
173
  { "lv.rl.b",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7",   EFI, 0, it_unknown },
174
  { "lv.rl.h",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8",   EFI, 0, it_unknown },
175
  { "lv.sll.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9",   EFI, 0, it_unknown },
176
  { "lv.sll.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA",   EFI, 0, it_unknown },
177
  { "lv.sll",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB",   EFI, 0, it_unknown },
178
  { "lv.srl.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC",   EFI, 0, it_unknown },
179
  { "lv.srl.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD",   EFI, 0, it_unknown },
180
  { "lv.sra.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE",   EFI, 0, it_unknown },
181
  { "lv.sra.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF",   EFI, 0, it_unknown },
182
  { "lv.srl",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0",   EFI, 0, it_unknown },
183
  { "lv.sub.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1",   EFI, 0, it_unknown },
184
  { "lv.sub.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2",   EFI, 0, it_unknown },
185
  { "lv.subs.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3",   EFI, 0, it_unknown },
186
  { "lv.subs.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4",   EFI, 0, it_unknown },
187
  { "lv.subu.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5",   EFI, 0, it_unknown },
188
  { "lv.subu.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6",   EFI, 0, it_unknown },
189
  { "lv.subus.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7",   EFI, 0, it_unknown },
190
  { "lv.subus.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8",   EFI, 0, it_unknown },
191
  { "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9",   EFI, 0, it_unknown },
192
  { "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA",   EFI, 0, it_unknown },
193
  { "lv.xor",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB",   EFI, 0, it_unknown },
194
  { "lv.cust1",   "",            "00 0xA  ----- ----- ---- ---- 0xC ----",  EFI, 0, it_unknown },
195
  { "lv.cust2",   "",            "00 0xA  ----- ----- ---- ---- 0xD ----",  EFI, 0, it_unknown },
196
  { "lv.cust3",   "",            "00 0xA  ----- ----- ---- ---- 0xE ----",  EFI, 0, it_unknown },
197
  { "lv.cust4",   "",            "00 0xA  ----- ----- ---- ---- 0xF ----",  EFI, 0, it_unknown },
198 24 jeremybenn
 
199 225 jeremybenn
  { "l.jr",       "rB",          "01 0x1  ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY, it_jump },
200
  { "l.jalr",     "rB",          "01 0x2  ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY, it_jump },
201
  { "l.maci",     "rA,I",        "01 0x3  ----- AAAAA IIII IIII IIII IIII", EF(l_mac), 0, it_mac },
202
  { "l.cust1",    "",            "01 0xC  ----- ----- ---- ---- ---- ----", EF(l_cust1), 0, it_unknown },
203
  { "l.cust2",    "",            "01 0xD  ----- ----- ---- ---- ---- ----", EF(l_cust2), 0, it_unknown },
204
  { "l.cust3",    "",            "01 0xE  ----- ----- ---- ---- ---- ----", EF(l_cust3), 0, it_unknown },
205
  { "l.cust4",    "",            "01 0xF  ----- ----- ---- ---- ---- ----", EF(l_cust4), 0, it_unknown },
206 24 jeremybenn
 
207 225 jeremybenn
  { "l.ld",       "rD,I(rA)",    "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_load },
208
  { "l.lwz",      "rD,I(rA)",    "10 0x1  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0, it_load },
209
  { "l.lws",      "rD,I(rA)",    "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_load },
210
  { "l.lbz",      "rD,I(rA)",    "10 0x3  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0, it_load },
211
  { "l.lbs",      "rD,I(rA)",    "10 0x4  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0, it_load },
212
  { "l.lhz",      "rD,I(rA)",    "10 0x5  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0, it_load },
213
  { "l.lhs",      "rD,I(rA)",    "10 0x6  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0, it_load },
214 24 jeremybenn
 
215 225 jeremybenn
  { "l.addi",     "rD,rA,I",     "10 0x7  DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), OR32_W_FLAG, it_arith },
216
  { "l.addic",    "rD,rA,I",     "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_arith },
217
  { "l.andi",     "rD,rA,K",     "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), OR32_W_FLAG, it_arith },
218
  { "l.ori",      "rD,rA,K",     "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0, it_arith },
219
  { "l.xori",     "rD,rA,I",     "10 0xB  DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0, it_arith },
220
  { "l.muli",     "rD,rA,I",     "10 0xC  DDDDD AAAAA IIII IIII IIII IIII", EF(l_mul), 0, it_arith },
221
  { "l.mfspr",    "rD,rA,K",     "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0, it_move },
222
  { "l.slli",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0, it_shift },
223
  { "l.srli",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0, it_shift },
224
  { "l.srai",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0, it_shift },
225
  { "l.rori",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0, it_shift },
226 24 jeremybenn
 
227 225 jeremybenn
  { "l.sfeqi",    "rA,I",        "10 0xF  00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG, it_compare },
228
  { "l.sfnei",    "rA,I",        "10 0xF  00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG, it_compare },
229
  { "l.sfgtui",   "rA,I",        "10 0xF  00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG, it_compare },
230
  { "l.sfgeui",   "rA,I",        "10 0xF  00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG, it_compare },
231
  { "l.sfltui",   "rA,I",        "10 0xF  00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG, it_compare },
232
  { "l.sfleui",   "rA,I",        "10 0xF  00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG, it_compare },
233
  { "l.sfgtsi",   "rA,I",        "10 0xF  01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG, it_compare },
234
  { "l.sfgesi",   "rA,I",        "10 0xF  01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG, it_compare },
235
  { "l.sfltsi",   "rA,I",        "10 0xF  01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG, it_compare },
236
  { "l.sflesi",   "rA,I",        "10 0xF  01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG, it_compare },
237 24 jeremybenn
 
238 225 jeremybenn
  { "l.mtspr",    "rA,rB,K",     "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0, it_move },
239
  { "l.mac",      "rA,rB",       "11 0x1  ----- AAAAA BBBB B--- ---- 0x1",  EF(l_mac), 0, it_mac },
240
  { "l.msb",      "rA,rB",       "11 0x1  ----- AAAAA BBBB B--- ---- 0x2",  EF(l_msb), 0, it_mac },
241 24 jeremybenn
 
242 225 jeremybenn
  { "lf.add.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x0",   EF(lf_add_s), 0, it_float },
243
  { "lf.sub.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x1",   EF(lf_sub_s), 0, it_float },
244
  { "lf.mul.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x2",   EF(lf_mul_s), 0, it_float },
245
  { "lf.div.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x3",   EF(lf_div_s), 0, it_float },
246
  { "lf.itof.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x4",   EF(lf_itof_s), 0, it_float },
247
  { "lf.ftoi.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x5",   EF(lf_ftoi_s), 0, it_float },
248
  { "lf.rem.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x6",   EF(lf_rem_s), 0, it_float },
249
  { "lf.madd.s",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x7",   EF(lf_madd_s), 0, it_float },
250
  { "lf.sfeq.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x8",   EF(lf_sfeq_s), 0, it_float },
251
  { "lf.sfne.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x9",   EF(lf_sfne_s), 0, it_float },
252
  { "lf.sfgt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xA",   EF(lf_sfgt_s), 0, it_float },
253
  { "lf.sfge.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xB",   EF(lf_sfge_s), 0, it_float },
254
  { "lf.sflt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xC",   EF(lf_sflt_s), 0, it_float },
255
  { "lf.sfle.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xD",   EF(lf_sfle_s), 0, it_float },
256
  { "lf.cust1.s", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xD ----",  EFI, 0, it_float },
257 24 jeremybenn
 
258 225 jeremybenn
  { "lf.add.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x0",   EFI, 0, it_float },
259
  { "lf.sub.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x1",   EFI, 0, it_float },
260
  { "lf.mul.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x2",   EFI, 0, it_float },
261
  { "lf.div.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x3",   EFI, 0, it_float },
262
  { "lf.itof.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x4",   EFI, 0, it_float },
263
  { "lf.ftoi.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x5",   EFI, 0, it_float },
264
  { "lf.rem.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x6",   EFI, 0, it_float },
265
  { "lf.madd.d",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x7",   EFI, 0, it_float },
266
  { "lf.sfeq.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x8",   EFI, 0, it_float },
267
  { "lf.sfne.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x9",   EFI, 0, it_float },
268
  { "lf.sfgt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xA",   EFI, 0, it_float },
269
  { "lf.sfge.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xB",   EFI, 0, it_float },
270
  { "lf.sflt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xC",   EFI, 0, it_float },
271
  { "lf.sfle.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD",   EFI, 0, it_float },
272
  { "lf.cust1.d", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xE ----",  EFI, 0, it_float },
273 24 jeremybenn
 
274 225 jeremybenn
  { "l.sd",       "I(rD),rB",    "11 0x4  IIIII DDDDD BBBB BIII IIII IIII", EFI, 0, it_store },
275
  { "l.sw",       "I(rD),rB",    "11 0x5  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sw), 0, it_store },
276
  { "l.sb",       "I(rD),rB",    "11 0x6  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sb), 0, it_store },
277
  { "l.sh",       "I(rD),rB",    "11 0x7  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sh), 0, it_store },
278 24 jeremybenn
 
279 225 jeremybenn
  { "l.add",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",  EF(l_add), OR32_W_FLAG, it_arith },
280
  { "l.addc",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",  EF(l_addc), OR32_W_FLAG, it_arith },
281
  { "l.sub",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2",  EF(l_sub), 0, it_arith },
282
  { "l.and",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3",  EF(l_and), OR32_W_FLAG, it_arith },
283
  { "l.or",       "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4",  EF(l_or), 0, it_arith },
284
  { "l.xor",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5",  EF(l_xor), 0, it_arith },
285
  { "l.mul",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6",  EF(l_mul), 0, it_arith },
286 24 jeremybenn
 
287 225 jeremybenn
  { "l.sll",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8",  EF(l_sll), 0, it_shift },
288
  { "l.srl",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8",  EF(l_srl), 0, it_shift },
289
  { "l.sra",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8",  EF(l_sra), 0, it_shift },
290
  { "l.ror",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8",  EFI, 0, it_shift },
291
  { "l.div",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x9",  EF(l_div), 0, it_arith },
292
  { "l.divu",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xA",  EF(l_divu), 0, it_arith },
293
  { "l.mulu",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB",  EFI, 0, it_arith },
294
  { "l.extbs",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 01-- 0xC",  EF(l_extbs), 0, it_move },
295
  { "l.exths",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 00-- 0xC",  EF(l_exths), 0, it_move },
296
  { "l.extws",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 00-- 0xD",  EF(l_extws), 0, it_move },
297
  { "l.extbz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 11-- 0xC",  EF(l_extbz), 0, it_move },
298
  { "l.exthz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 10-- 0xC",  EF(l_exthz), 0, it_move },
299
  { "l.extwz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 01-- 0xD",  EF(l_extwz), 0, it_move },
300
  { "l.cmov",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE",  EF(l_cmov), OR32_R_FLAG, it_move },
301
  { "l.ff1",      "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 ---- 0xF",  EF(l_ff1), 0, it_arith },
302
  { "l.fl1",      "rD,rA",       "11 0x8  DDDDD AAAAA ---- --01 ---- 0xF",  EFI, 0, it_arith },
303 24 jeremybenn
 
304 225 jeremybenn
  { "l.sfeq",     "rA,rB",       "11 0x9  00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG, it_compare },
305
  { "l.sfne",     "rA,rB",       "11 0x9  00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG, it_compare },
306
  { "l.sfgtu",    "rA,rB",       "11 0x9  00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG, it_compare },
307
  { "l.sfgeu",    "rA,rB",       "11 0x9  00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG, it_compare },
308
  { "l.sfltu",    "rA,rB",       "11 0x9  00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG, it_compare },
309
  { "l.sfleu",    "rA,rB",       "11 0x9  00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG, it_compare },
310
  { "l.sfgts",    "rA,rB",       "11 0x9  01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG, it_compare },
311
  { "l.sfges",    "rA,rB",       "11 0x9  01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG, it_compare },
312
  { "l.sflts",    "rA,rB",       "11 0x9  01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG, it_compare },
313
  { "l.sfles",    "rA,rB",       "11 0x9  01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG, it_compare },
314 24 jeremybenn
 
315 225 jeremybenn
  { "l.cust5",    "rD,rA,rB,L,K","11 0xC  DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI, 0, it_unknown },
316
  { "l.cust6",    "",            "11 0xD  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
317
  { "l.cust7",    "",            "11 0xE  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
318
  { "l.cust8",    "",            "11 0xF  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
319 24 jeremybenn
 
320
  /* This section should not be defined in or1ksim, since it contains duplicates,
321
     which would cause machine builder to complain.  */
322
#ifdef HAS_CUST
323 225 jeremybenn
  { "l.cust5_1",  "rD",          "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
324
  { "l.cust5_2",  "rD,rA"   ,    "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
325
  { "l.cust5_3",  "rD,rA,rB",    "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
326
 
327
  { "l.cust6_1",  "rD",          "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
328
  { "l.cust6_2",  "rD,rA"   ,    "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
329
  { "l.cust6_3",  "rD,rA,rB",    "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
330
 
331
  { "l.cust7_1",  "rD",          "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
332
  { "l.cust7_2",  "rD,rA"   ,    "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
333
  { "l.cust7_3",  "rD,rA,rB",    "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
334
 
335
  { "l.cust8_1",  "rD",          "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
336
  { "l.cust8_2",  "rD,rA"   ,    "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
337
  { "l.cust8_3",  "rD,rA,rB",    "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
338 24 jeremybenn
#endif
339
 
340
  /* Dummy entry, not included in num_opcodes.  This
341
     lets code examine entry i+1 without checking
342
     if we've run off the end of the table.  */
343 225 jeremybenn
  { "", "", "", EFI, 0, 0 }
344 24 jeremybenn
};
345
 
346
#undef EFI
347
#undef EFN
348
#undef EF 
349
 
350
/* Define dummy, if debug is not defined.  */
351 225 jeremybenn
#ifndef HAS_DEBUG
352
#define debug(l, fmt...) ;
353 24 jeremybenn
#endif
354
 
355
const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
356
 
357
/* Calculates instruction length in bytes. Always 4 for OR32.  */
358
 
359
int
360
insn_len (int insn_index ATTRIBUTE_UNUSED)
361
{
362 225 jeremybenn
  insn_index = 0; /* Just to get rid that warning.  */
363 24 jeremybenn
  return 4;
364
}
365
 
366
/* Is individual insn's operand signed or unsigned?  */
367
 
368
int
369
letter_signed (char l)
370
{
371
  const struct or32_letter *pletter;
372
 
373
  for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
374
    if (pletter->letter == l)
375
      return pletter->sign;
376
 
377
  printf ("letter_signed(%c): Unknown letter.\n", l);
378
  return 0;
379
}
380
 
381 225 jeremybenn
/* Simple cache for letter ranges */
382
static int range_cache[256] = {0};
383
 
384 24 jeremybenn
/* Number of letters in the individual lettered operand.  */
385
int
386
letter_range (char l)
387
{
388
  const struct or32_opcode *pinsn;
389
  char *enc;
390
  int range = 0;
391 225 jeremybenn
 
392
  /* Is value cached? */
393
  if ((range = range_cache[(unsigned char)l])) return range;
394 24 jeremybenn
 
395
  for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++)
396
    {
397
      if (strchr (pinsn->encoding,l))
398
        {
399
          for (enc = pinsn->encoding; *enc != '\0'; enc ++)
400
            if ((*enc == '0') && (*(enc + 1) == 'x'))
401
              enc += 2;
402
            else if (*enc == l)
403
              range++;
404 225 jeremybenn
          return range_cache[(unsigned char)l] = range;
405 24 jeremybenn
        }
406
    }
407
 
408
  printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
409
  exit (1);
410
}
411
 
412
/* MM: Returns index of given instruction name.  */
413
 
414
int
415
insn_index (char *insn)
416
{
417
  unsigned int i;
418
  int found = -1;
419
 
420
  for (i = 0; i < or32_num_opcodes; i++)
421
    if (!strcmp (or32_opcodes[i].name, insn))
422
      {
423
        found = i;
424
        break;
425
      }
426
  return found;
427
}
428
 
429
const char *
430
insn_name (int index)
431
{
432
  if (index >= 0 && index < (int) or32_num_opcodes)
433
    return or32_opcodes[index].name;
434
  else
435
    return "???";
436
}
437
 
438 225 jeremybenn
#if defined(HAS_EXECUTION) && SIMPLE_EXECUTION
439 24 jeremybenn
void
440 225 jeremybenn
l_none(struct iqueue_entry *current)
441
{
442
}
443
#elif defined(HAS_EXECUTION) && DYNAMIC_EXECUTION
444
void
445
l_none(struct op_queue *opq, int *param_t, orreg_t *param, int delay_slot)
446
{
447
}
448
#else
449
void
450 24 jeremybenn
l_none (void)
451
{
452
}
453 225 jeremybenn
#endif
454 24 jeremybenn
 
455
/* Finite automata for instruction decoding building code.  */
456
 
457
/* Find simbols in encoding.  */
458
 
459 225 jeremybenn
unsigned long
460 24 jeremybenn
insn_extract (char param_ch, char *enc_initial)
461
{
462
  char *enc;
463
  unsigned long ret = 0;
464
  unsigned opc_pos = 32;
465
 
466
  for (enc = enc_initial; *enc != '\0'; )
467
    if ((*enc == '0') && (*(enc + 1) == 'x'))
468
      {
469
        unsigned long tmp = strtol (enc+2, NULL, 16);
470
 
471
        opc_pos -= 4;
472
        if (param_ch == '0' || param_ch == '1')
473
          {
474
            if (param_ch == '0')
475
              tmp = 15 - tmp;
476
            ret |= tmp << opc_pos;
477
          }
478
        enc += 3;
479
      }
480
    else
481
      {
482
        if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
483
          {
484
            opc_pos--;
485
            if (param_ch == *enc)
486 673 yannv
              ret |= 1UL << opc_pos;
487 24 jeremybenn
          }
488
        enc++;
489
      }
490
  return ret;
491
}
492
 
493
#define MAX_AUTOMATA_SIZE  1200
494
#define MAX_OP_TABLE_SIZE  1200
495
#define MAX_LEN            8
496
 
497
#ifndef MIN
498
#define MIN(x, y)          ((x) < (y) ? (x) : (y))
499
#endif
500
 
501
unsigned long *automata;
502
int nuncovered;
503
int curpass = 0;
504
 
505
/* MM: Struct that hold runtime build information about instructions.  */
506 225 jeremybenn
struct temp_insn_struct *ti;
507 24 jeremybenn
 
508
struct insn_op_struct *op_data, **op_start;
509
 
510
/* Recursive utility function used to find best match and to build automata.  */
511
 
512
static unsigned long *
513
cover_insn (unsigned long * cur, int pass, unsigned int mask)
514
{
515
  int best_first = 0, last_match = -1, ninstr = 0;
516
  unsigned int best_len = 0;
517
  unsigned int i;
518
  unsigned long cur_mask = mask;
519
  unsigned long *next;
520
 
521
  for (i = 0; i < or32_num_opcodes; i++)
522
    if (ti[i].in_pass == pass)
523
      {
524
        cur_mask &= ti[i].insn_mask;
525
        ninstr++;
526
        last_match = i;
527
      }
528
 
529
  debug (8, "%08X %08lX\n", mask, cur_mask);
530
 
531
  if (ninstr == 0)
532
    return 0;
533
 
534
  if (ninstr == 1)
535
    {
536
      /* Leaf holds instruction index.  */
537
      debug (8, "%li>I%i %s\n",
538
             (long)(cur - automata), last_match, or32_opcodes[last_match].name);
539
 
540
      *cur = LEAF_FLAG | last_match;
541
      cur++;
542
      nuncovered--;
543
    }
544
  else
545
    {
546
      /* Find longest match.  */
547
      for (i = 0; i < 32; i++)
548
        {
549
          unsigned int len;
550
 
551
          for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
552
            {
553
              unsigned long m = (1UL << ((unsigned long) len)) - 1;
554
 
555
              debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)",
556
                     len,m, cur_mask, i, (cur_mask >> (unsigned)i),
557
                     (cur_mask >> (unsigned) i) & m);
558
 
559
              if ((m & (cur_mask >> (unsigned) i)) == m)
560
                {
561
                  best_len = len;
562
                  best_first = i;
563
                  debug (9, "!");
564
                }
565
              else
566
                break;
567
            }
568
        }
569
 
570
      debug (9, "\n");
571
 
572
      if (!best_len)
573
        {
574
          fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
575
 
576
          for (i = 0; i < or32_num_opcodes; i++)
577
            if (ti[i].in_pass == pass)
578
              fprintf (stderr, "%s ", or32_opcodes[i].name);
579
 
580
          fprintf (stderr, "\n");
581
          exit (1);
582
        }
583
 
584
      debug (8, "%li> #### %i << %i (%i) ####\n",
585
             (long)(cur - automata), best_len, best_first, ninstr);
586
 
587
      *cur = best_first;
588
      cur++;
589 673 yannv
      *cur = (1UL << best_len) - 1;
590 24 jeremybenn
      cur++;
591
      next = cur;
592
 
593
      /* Allocate space for pointers.  */
594 673 yannv
      cur += 1UL << best_len;
595
      cur_mask = (1UL << (unsigned long) best_len) - 1;
596 24 jeremybenn
 
597 673 yannv
      for (i = 0; i < (1U << best_len); i++)
598 24 jeremybenn
        {
599
          unsigned int j;
600
          unsigned long *c;
601
 
602
          curpass++;
603
          for (j = 0; j < or32_num_opcodes; j++)
604
            if (ti[j].in_pass == pass
605
                && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
606
                && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
607
              ti[j].in_pass = curpass;
608
 
609
          debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
610
          c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
611
          if (c)
612
            {
613 225 jeremybenn
              debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i,
614
                     (unsigned long)(cur - automata));
615 24 jeremybenn
              *next = cur - automata;
616
              cur = c;
617
            }
618
          else
619
            {
620
              debug (8, "%li> N/A\n", (long)(next - automata));
621
              *next = 0;
622
            }
623
          next++;
624
        }
625
    }
626
  return cur;
627
}
628
 
629
/* Returns number of nonzero bits.  */
630
 
631
static int
632
num_ones (unsigned long value)
633
{
634
  int c = 0;
635
 
636
  while (value)
637
    {
638
      if (value & 1)
639
        c++;
640
      value >>= 1;
641
    }
642
  return c;
643
}
644
 
645
/* Utility function, which converts parameters from or32_opcode
646
   format to more binary form.  Parameters are stored in ti struct.  */
647
 
648
static struct insn_op_struct *
649
parse_params (const struct or32_opcode * opcode,
650
              struct insn_op_struct * cur)
651
{
652
  char *args = opcode->args;
653
  int i, type;
654 225 jeremybenn
  int num_cur_op = 0;
655 24 jeremybenn
 
656
  i = 0;
657
  type = 0;
658
  /* In case we don't have any parameters, we add dummy read from r0.  */
659
 
660
  if (!(*args))
661
    {
662
      cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
663
      cur->data = 0;
664
      debug (9, "#%08lX %08lX\n", cur->type, cur->data);
665
      cur++;
666
      return cur;
667
  }
668
 
669
  while (*args != '\0')
670
    {
671
      if (*args == 'r')
672
        {
673
          args++;
674
          type |= OPTYPE_REG;
675 225 jeremybenn
    if (*args == 'D')
676
      type |= OPTYPE_DST;
677 24 jeremybenn
        }
678
      else if (ISALPHA (*args))
679
        {
680
          unsigned long arg;
681
 
682
          arg = insn_extract (*args, opcode->encoding);
683
          debug (9, "%s : %08lX ------\n", opcode->name, arg);
684
          if (letter_signed (*args))
685
            {
686
              type |= OPTYPE_SIG;
687
              type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
688
            }
689
 
690 225 jeremybenn
    num_cur_op = 0;
691 24 jeremybenn
          /* Split argument to sequences of consecutive ones.  */
692
          while (arg)
693
            {
694
              int shr = 0;
695
              unsigned long tmp = arg, mask = 0;
696
 
697
              while ((tmp & 1) == 0)
698
                {
699
                  shr++;
700
                  tmp >>= 1;
701
                }
702
              while (tmp & 1)
703
                {
704
                  mask++;
705
                  tmp >>= 1;
706
                }
707
              cur->type = type | shr;
708
              cur->data = mask;
709 673 yannv
              arg &= ~(((1UL << mask) - 1) << shr);
710 24 jeremybenn
              debug (6, "|%08lX %08lX\n", cur->type, cur->data);
711
              cur++;
712 225 jeremybenn
        num_cur_op++;
713 24 jeremybenn
            }
714
          args++;
715
        }
716
      else if (*args == '(')
717
        {
718
          /* Next param is displacement.
719
             Later we will treat them as one operand.  */
720 225 jeremybenn
    /* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
721
     * operand */
722
    while(num_cur_op > 0) {
723
            cur[-num_cur_op].type |= type | OPTYPE_DIS;
724
      num_cur_op--;
725
    }
726
    cur[-1].type |= OPTYPE_OP;
727
          debug(9, ">%08X %08X\n", cur->type, cur->data);
728 24 jeremybenn
          type = 0;
729
          i++;
730
          args++;
731
        }
732
      else if (*args == OPERAND_DELIM)
733
        {
734
          cur--;
735
          cur->type = type | cur->type | OPTYPE_OP;
736
          debug (9, ">%08lX %08lX\n", cur->type, cur->data);
737
          cur++;
738
          type = 0;
739
          i++;
740
          args++;
741
        }
742
      else if (*args == '0')
743
        {
744
          cur->type = type;
745
          cur->data = 0;
746
          debug (9, ">%08lX %08lX\n", cur->type, cur->data);
747
          cur++;
748
          type = 0;
749
          i++;
750
          args++;
751
        }
752
      else if (*args == ')')
753
        args++;
754
      else
755
        {
756
          fprintf (stderr, "%s : parse error in args.\n", opcode->name);
757
          exit (1);
758
        }
759
    }
760
 
761
  cur--;
762
  cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
763
  debug (9, "#%08lX %08lX\n", cur->type, cur->data);
764
  cur++;
765
 
766
  return cur;
767
}
768
 
769
/* Constructs new automata based on or32_opcodes array.  */
770
 
771
void
772
build_automata (void)
773
{
774
  unsigned int i;
775
  unsigned long *end;
776
  struct insn_op_struct *cur;
777
 
778
  automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
779
  ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
780
 
781
  nuncovered = or32_num_opcodes;
782
  printf ("Building automata... ");
783
  /* Build temporary information about instructions.  */
784
  for (i = 0; i < or32_num_opcodes; i++)
785
    {
786
      unsigned long ones, zeros;
787
      char *encoding = or32_opcodes[i].encoding;
788
 
789
      ones  = insn_extract('1', encoding);
790
      zeros = insn_extract('0', encoding);
791
 
792
      ti[i].insn_mask = ones | zeros;
793
      ti[i].insn = ones;
794
      ti[i].in_pass = curpass = 0;
795
 
796
      /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
797
        or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
798
    }
799
 
800
  /* Until all are covered search for best criteria to separate them.  */
801
  end = cover_insn (automata, curpass, 0xFFFFFFFF);
802
 
803
  if (end - automata > MAX_AUTOMATA_SIZE)
804
    {
805
      fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
806
      exit (1);
807
    }
808
 
809
  printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
810
  printf ("Parsing operands data... ");
811
 
812
  op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
813
  op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
814
  cur = op_data;
815
 
816
  for (i = 0; i < or32_num_opcodes; i++)
817
    {
818
      op_start[i] = cur;
819
      cur = parse_params (&or32_opcodes[i], cur);
820
 
821
      if (cur - op_data > MAX_OP_TABLE_SIZE)
822
        {
823
          fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
824
          exit (1);
825
        }
826
    }
827
  printf ("done.\n");
828
}
829
 
830
void
831
destruct_automata (void)
832
{
833
  free (ti);
834
  free (automata);
835
  free (op_data);
836
  free (op_start);
837
}
838
 
839
/* Decodes instruction and returns instruction index.  */
840
 
841
int
842
insn_decode (unsigned int insn)
843
{
844
  unsigned long *a = automata;
845
  int i;
846
 
847
  while (!(*a & LEAF_FLAG))
848
    {
849
      unsigned int first = *a;
850
 
851
      debug (9, "%li ", (long)(a - automata));
852
 
853
      a++;
854
      i = (insn >> first) & *a;
855
      a++;
856
      if (!*(a + i))
857
        {
858
          /* Invalid instruction found?  */
859
          debug (9, "XXX\n");
860
          return -1;
861
        }
862
      a = automata + *(a + i);
863
    }
864
 
865
  i = *a & ~LEAF_FLAG;
866
 
867
  debug (9, "%i\n", i);
868
 
869
  /* Final check - do we have direct match?
870
     (based on or32_opcodes this should be the only possibility,
871
     but in case of invalid/missing instruction we must perform a check)  */
872
  if ((ti[i].insn_mask & insn) == ti[i].insn)
873
    return i;
874
  else
875
    return -1;
876
}
877
 
878
static char disassembled_str[50];
879
char *disassembled = &disassembled_str[0];
880
 
881
/* Automagically does zero- or sign- extension and also finds correct
882
   sign bit position if sign extension is correct extension. Which extension
883
   is proper is figured out from letter description.  */
884
 
885 225 jeremybenn
unsigned long
886 24 jeremybenn
extend_imm (unsigned long imm, char l)
887
{
888
  unsigned long mask;
889
  int letter_bits;
890
 
891
  /* First truncate all bits above valid range for this letter
892
     in case it is zero extend.  */
893
  letter_bits = letter_range (l);
894 673 yannv
  mask = (1UL << letter_bits) - 1;
895 24 jeremybenn
  imm &= mask;
896
 
897
  /* Do sign extend if this is the right one.  */
898
  if (letter_signed(l) && (imm >> (letter_bits - 1)))
899
    imm |= (~mask);
900
 
901
  return imm;
902
}
903
 
904
static unsigned long
905
or32_extract (char param_ch, char *enc_initial, unsigned long insn)
906
{
907
  char *enc;
908
  unsigned long ret = 0;
909
  int opc_pos = 0;
910
  int param_pos = 0;
911
 
912
  for (enc = enc_initial; *enc != '\0'; enc++)
913
    if (*enc == param_ch)
914
      {
915
        if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
916
          continue;
917
        else
918
          param_pos++;
919
      }
920
 
921
#if DEBUG
922
  printf ("or32_extract: %x ", param_pos);
923
#endif
924
  opc_pos = 32;
925
 
926
  for (enc = enc_initial; *enc != '\0'; )
927
    if ((*enc == '0') && (*(enc + 1) == 'x'))
928
      {
929
        opc_pos -= 4;
930
        if ((param_ch == '0') || (param_ch == '1'))
931
          {
932
            unsigned long tmp = strtol (enc, NULL, 16);
933
#if DEBUG
934
            printf (" enc=%s, tmp=%x ", enc, tmp);
935
#endif
936
            if (param_ch == '0')
937
              tmp = 15 - tmp;
938
            ret |= tmp << opc_pos;
939
          }
940
        enc += 3;
941
      }
942
    else if ((*enc == '0') || (*enc == '1'))
943
      {
944
        opc_pos--;
945
        if (param_ch == *enc)
946 673 yannv
          ret |= 1UL << opc_pos;
947 24 jeremybenn
        enc++;
948
      }
949
    else if (*enc == param_ch)
950
      {
951
        opc_pos--;
952
        param_pos--;
953
#if DEBUG
954
        printf ("\n  ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
955
#endif  
956
        if (ISLOWER (param_ch))
957
          ret -= ((insn >> opc_pos) & 0x1) << param_pos;
958
        else
959
          ret += ((insn >> opc_pos) & 0x1) << param_pos;
960
        enc++;
961
      }
962
    else if (ISALPHA (*enc))
963
      {
964
        opc_pos--;
965
        enc++;
966
      }
967
    else if (*enc == '-')
968
      {
969
        opc_pos--;
970
        enc++;
971
      }
972
    else
973
      enc++;
974
 
975
#if DEBUG
976
  printf ("ret=%x\n", ret);
977
#endif
978
  return ret;
979
}
980
 
981
/* Print register. Used only by print_insn.  */
982
 
983 225 jeremybenn
static char *
984
or32_print_register (char *dest, char param_ch, char *encoding, unsigned long insn)
985 24 jeremybenn
{
986
  int regnum = or32_extract(param_ch, encoding, insn);
987
 
988 225 jeremybenn
  sprintf (dest, "r%d", regnum);
989
  while (*dest) dest++;
990
  return dest;
991 24 jeremybenn
}
992
 
993
/* Print immediate. Used only by print_insn.  */
994
 
995 225 jeremybenn
static char *
996
or32_print_immediate (char *dest, char param_ch, char *encoding, unsigned long insn)
997 24 jeremybenn
{
998
  int imm = or32_extract (param_ch, encoding, insn);
999
 
1000
  imm = extend_imm (imm, param_ch);
1001 225 jeremybenn
 
1002 24 jeremybenn
  if (letter_signed (param_ch))
1003
    {
1004
      if (imm < 0)
1005 225 jeremybenn
        sprintf (dest, "%d", imm);
1006 24 jeremybenn
      else
1007 225 jeremybenn
        sprintf (dest, "0x%x", imm);
1008 24 jeremybenn
    }
1009
  else
1010 225 jeremybenn
    sprintf (dest, "%#x", imm);
1011
  while (*dest) dest++;
1012
  return dest;
1013 24 jeremybenn
}
1014
 
1015 225 jeremybenn
/* Disassemble one instruction from insn index.
1016 24 jeremybenn
   Return the size of the instruction.  */
1017 225 jeremybenn
 
1018 24 jeremybenn
int
1019 225 jeremybenn
disassemble_index (insn, index)
1020
     unsigned long insn;
1021
     int index;
1022 24 jeremybenn
{
1023 225 jeremybenn
  char *dest = disassembled;
1024 24 jeremybenn
 
1025
  if (index >= 0)
1026
    {
1027
      struct or32_opcode const *opcode = &or32_opcodes[index];
1028
      char *s;
1029
 
1030 225 jeremybenn
      strcpy (dest, opcode->name);
1031
      while (*dest) dest++;
1032
      *dest++ = ' ';
1033
      *dest = 0;
1034
 
1035 24 jeremybenn
      for (s = opcode->args; *s != '\0'; ++s)
1036
        {
1037
          switch (*s)
1038
            {
1039
            case '\0':
1040 225 jeremybenn
              return insn_len (insn);
1041 24 jeremybenn
 
1042
            case 'r':
1043 225 jeremybenn
              dest = or32_print_register(dest, *++s, opcode->encoding, insn);
1044 24 jeremybenn
              break;
1045
 
1046
            default:
1047
              if (strchr (opcode->encoding, *s))
1048 225 jeremybenn
                dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
1049
              else {
1050
                *dest++ = *s;
1051
                *dest = 0;
1052
              }
1053 24 jeremybenn
            }
1054
        }
1055
    }
1056
  else
1057
    {
1058
      /* This used to be %8x for binutils.  */
1059 225 jeremybenn
      sprintf(dest, ".word 0x%08lx", insn);
1060
      while (*dest) dest++;
1061 24 jeremybenn
    }
1062
 
1063
  return insn_len (insn);
1064
}
1065 225 jeremybenn
 
1066
/* Disassemble one instruction from insn to disassemble.
1067
   Return the size of the instruction.  */
1068
 
1069
int
1070
disassemble_insn (unsigned long insn)
1071
{
1072
  return disassemble_index (insn, insn_decode (insn));
1073
}
1074
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.