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jeremybenn |
/* s390-opc.c -- S390 opcode list
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Copyright 2000, 2001, 2003, 2007 Free Software Foundation, Inc.
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Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/s390.h"
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/* This file holds the S390 opcode table. The opcode table
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includes almost all of the extended instruction mnemonics. This
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permits the disassembler to use them, and simplifies the assembler
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logic, at the cost of increasing the table size. The table is
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strictly constant data, so the compiler should be able to put it in
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the .text section.
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This file also holds the operand table. All knowledge about
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inserting operands into instructions and vice-versa is kept in this
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file. */
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/* The operands table.
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The fields are bits, shift, insert, extract, flags. */
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const struct s390_operand s390_operands[] =
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{
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#define UNUSED 0
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{ 0, 0, 0 }, /* Indicates the end of the operand list */
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#define R_8 1 /* GPR starting at position 8 */
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{ 4, 8, S390_OPERAND_GPR },
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#define R_12 2 /* GPR starting at position 12 */
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{ 4, 12, S390_OPERAND_GPR },
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#define R_16 3 /* GPR starting at position 16 */
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{ 4, 16, S390_OPERAND_GPR },
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#define R_20 4 /* GPR starting at position 20 */
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{ 4, 20, S390_OPERAND_GPR },
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#define R_24 5 /* GPR starting at position 24 */
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{ 4, 24, S390_OPERAND_GPR },
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#define R_28 6 /* GPR starting at position 28 */
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{ 4, 28, S390_OPERAND_GPR },
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#define R_32 7 /* GPR starting at position 32 */
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{ 4, 32, S390_OPERAND_GPR },
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#define F_8 8 /* FPR starting at position 8 */
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{ 4, 8, S390_OPERAND_FPR },
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#define F_12 9 /* FPR starting at position 12 */
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{ 4, 12, S390_OPERAND_FPR },
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#define F_16 10 /* FPR starting at position 16 */
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{ 4, 16, S390_OPERAND_FPR },
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#define F_20 11 /* FPR starting at position 16 */
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{ 4, 16, S390_OPERAND_FPR },
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#define F_24 12 /* FPR starting at position 24 */
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{ 4, 24, S390_OPERAND_FPR },
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#define F_28 13 /* FPR starting at position 28 */
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{ 4, 28, S390_OPERAND_FPR },
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#define F_32 14 /* FPR starting at position 32 */
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{ 4, 32, S390_OPERAND_FPR },
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#define A_8 15 /* Access reg. starting at position 8 */
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{ 4, 8, S390_OPERAND_AR },
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#define A_12 16 /* Access reg. starting at position 12 */
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{ 4, 12, S390_OPERAND_AR },
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#define A_24 17 /* Access reg. starting at position 24 */
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{ 4, 24, S390_OPERAND_AR },
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#define A_28 18 /* Access reg. starting at position 28 */
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{ 4, 28, S390_OPERAND_AR },
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#define C_8 19 /* Control reg. starting at position 8 */
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{ 4, 8, S390_OPERAND_CR },
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#define C_12 20 /* Control reg. starting at position 12 */
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{ 4, 12, S390_OPERAND_CR },
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#define B_16 21 /* Base register starting at position 16 */
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{ 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
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#define B_32 22 /* Base register starting at position 32 */
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{ 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
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#define X_12 23 /* Index register starting at position 12 */
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{ 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
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#define D_20 24 /* Displacement starting at position 20 */
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{ 12, 20, S390_OPERAND_DISP },
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#define D_36 25 /* Displacement starting at position 36 */
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{ 12, 36, S390_OPERAND_DISP },
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#define D20_20 26 /* 20 bit displacement starting at 20 */
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{ 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
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#define L4_8 27 /* 4 bit length starting at position 8 */
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{ 4, 8, S390_OPERAND_LENGTH },
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#define L4_12 28 /* 4 bit length starting at position 12 */
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{ 4, 12, S390_OPERAND_LENGTH },
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#define L8_8 29 /* 8 bit length starting at position 8 */
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{ 8, 8, S390_OPERAND_LENGTH },
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#define U4_8 30 /* 4 bit unsigned value starting at 8 */
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{ 4, 8, 0 },
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#define U4_12 31 /* 4 bit unsigned value starting at 12 */
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{ 4, 12, 0 },
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#define U4_16 32 /* 4 bit unsigned value starting at 16 */
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{ 4, 16, 0 },
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#define U4_20 33 /* 4 bit unsigned value starting at 20 */
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{ 4, 20, 0 },
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#define U8_8 34 /* 8 bit unsigned value starting at 8 */
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{ 8, 8, 0 },
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#define U8_16 35 /* 8 bit unsigned value starting at 16 */
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{ 8, 16, 0 },
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#define I16_16 36 /* 16 bit signed value starting at 16 */
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{ 16, 16, S390_OPERAND_SIGNED },
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#define U16_16 37 /* 16 bit unsigned value starting at 16 */
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{ 16, 16, 0 },
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#define J16_16 38 /* PC relative jump offset at 16 */
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{ 16, 16, S390_OPERAND_PCREL },
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#define J32_16 39 /* PC relative long offset at 16 */
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{ 32, 16, S390_OPERAND_PCREL },
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#define I32_16 40 /* 32 bit signed value starting at 16 */
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{ 32, 16, S390_OPERAND_SIGNED },
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#define U32_16 41 /* 32 bit unsigned value starting at 16 */
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{ 32, 16, 0 },
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#define M_16 42 /* 4 bit optional mask starting at 16 */
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{ 4, 16, S390_OPERAND_OPTIONAL },
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#define RO_28 43 /* optional GPR starting at position 28 */
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{ 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }
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};
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/* Macros used to form opcodes. */
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/* 8/16/48 bit opcodes. */
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#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
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#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
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(x >> 16) & 255, (x >> 8) & 255, x & 255}
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/* The new format of the INSTR_x_y and MASK_x_y defines is based
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on the following rules:
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1) the middle part of the definition (x in INSTR_x_y) is the official
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names of the instruction format that you can find in the principals
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of operation.
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2) the last part of the definition (y in INSTR_x_y) gives you an idea
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which operands the binary represenation of the instruction has.
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The meanings of the letters in y are:
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a - access register
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c - control register
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d - displacement, 12 bit
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f - floating pointer register
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i - signed integer, 4, 8, 16 or 32 bit
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l - length, 4 or 8 bit
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p - pc relative
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r - general purpose register
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u - unsigned integer, 4, 8, 16 or 32 bit
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m - mode field, 4 bit
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The order of the letters reflects the layout of the format in
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storage and not the order of the paramaters of the instructions.
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The use of the letters is not a 100% match with the PoP but it is
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quite close.
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For example the instruction "mvo" is defined in the PoP as follows:
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MVO D1(L1,B1),D2(L2,B2) [SS]
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--------------------------------------
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| 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
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--------------------------------------
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The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
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#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
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#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
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#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
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#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
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#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
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#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
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#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
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#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
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#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
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#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
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#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
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#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
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#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
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#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
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#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
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#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
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#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
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#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
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#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
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#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
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#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
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#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
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#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
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/* Actually efpc and sfpc do not take an optional operand.
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This is just a workaround for existing code e.g. glibc. */
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#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
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#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
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#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
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#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
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#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
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#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
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#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */
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#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
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#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
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#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
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#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
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#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */
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#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
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#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
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#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
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#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
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#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
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#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
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#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */
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#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
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#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
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#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
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#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */
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#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
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#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
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#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */
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#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */
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#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */
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#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
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#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
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#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
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#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
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#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
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#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
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| 246 |
|
|
#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
|
| 247 |
|
|
#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
|
| 248 |
|
|
#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
|
| 249 |
|
|
#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */
|
| 250 |
|
|
#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
|
| 251 |
|
|
#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
|
| 252 |
|
|
#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
|
| 253 |
|
|
#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
|
| 254 |
|
|
#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
|
| 255 |
|
|
#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
|
| 256 |
|
|
#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
|
| 257 |
|
|
#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
|
| 258 |
|
|
#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
|
| 259 |
|
|
#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
|
| 260 |
|
|
#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
|
| 261 |
|
|
#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
|
| 262 |
|
|
#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
|
| 263 |
|
|
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
|
| 264 |
|
|
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
|
| 265 |
|
|
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
|
| 266 |
|
|
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
|
| 267 |
|
|
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
|
| 268 |
|
|
|
| 269 |
|
|
#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 270 |
|
|
#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 271 |
|
|
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 272 |
|
|
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 273 |
|
|
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 274 |
|
|
#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 275 |
|
|
#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 276 |
|
|
#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 277 |
|
|
#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 278 |
|
|
#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 279 |
|
|
#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 280 |
|
|
#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 281 |
|
|
#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
|
| 282 |
|
|
#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
|
| 283 |
|
|
#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 284 |
|
|
#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 285 |
|
|
#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
|
| 286 |
|
|
#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 287 |
|
|
#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
|
| 288 |
|
|
#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 289 |
|
|
#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 290 |
|
|
#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 291 |
|
|
#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 292 |
|
|
#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
| 293 |
|
|
#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 294 |
|
|
#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 295 |
|
|
#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 296 |
|
|
#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 297 |
|
|
#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 298 |
|
|
#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 299 |
|
|
#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 300 |
|
|
#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 301 |
|
|
#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 302 |
|
|
#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
|
| 303 |
|
|
#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 304 |
|
|
#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 305 |
|
|
#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
|
| 306 |
|
|
#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 307 |
|
|
#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 308 |
|
|
#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 309 |
|
|
#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 310 |
|
|
#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 311 |
|
|
#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
|
| 312 |
|
|
#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 313 |
|
|
#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 314 |
|
|
#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 315 |
|
|
#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 316 |
|
|
#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 317 |
|
|
#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 318 |
|
|
#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 319 |
|
|
#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 320 |
|
|
#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 321 |
|
|
#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 322 |
|
|
#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 323 |
|
|
#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 324 |
|
|
#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 325 |
|
|
#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 326 |
|
|
#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 327 |
|
|
#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 328 |
|
|
#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 329 |
|
|
#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 330 |
|
|
#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 331 |
|
|
#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 332 |
|
|
#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
|
| 333 |
|
|
#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 334 |
|
|
#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 335 |
|
|
#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 336 |
|
|
#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 337 |
|
|
#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
| 338 |
|
|
#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 339 |
|
|
#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 340 |
|
|
#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 341 |
|
|
#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 342 |
|
|
#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 343 |
|
|
#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 344 |
|
|
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 345 |
|
|
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
| 346 |
|
|
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
|
| 347 |
|
|
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
| 348 |
|
|
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
|
| 349 |
|
|
|
| 350 |
|
|
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
|
| 351 |
|
|
|
| 352 |
|
|
const struct s390_opcode s390_opformats[] =
|
| 353 |
|
|
{
|
| 354 |
|
|
{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 },
|
| 355 |
|
|
{ "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 },
|
| 356 |
|
|
{ "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 },
|
| 357 |
|
|
{ "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 },
|
| 358 |
|
|
{ "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 },
|
| 359 |
|
|
{ "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 },
|
| 360 |
|
|
{ "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 },
|
| 361 |
|
|
{ "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 },
|
| 362 |
|
|
{ "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 },
|
| 363 |
|
|
{ "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 },
|
| 364 |
|
|
{ "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 },
|
| 365 |
|
|
{ "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 },
|
| 366 |
|
|
{ "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 },
|
| 367 |
|
|
{ "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 },
|
| 368 |
|
|
{ "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
|
| 369 |
|
|
{ "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 },
|
| 370 |
|
|
{ "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 },
|
| 371 |
|
|
{ "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 },
|
| 372 |
|
|
{ "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 },
|
| 373 |
|
|
{ "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
|
| 374 |
|
|
{ "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 },
|
| 375 |
|
|
{ "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
|
| 376 |
|
|
};
|
| 377 |
|
|
|
| 378 |
|
|
const int s390_num_opformats =
|
| 379 |
|
|
sizeof (s390_opformats) / sizeof (s390_opformats[0]);
|
| 380 |
|
|
|
| 381 |
|
|
#include "s390-opc.tab"
|
