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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [erc32/] [erc32.c] - Blame information for rev 856

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Line No. Rev Author Line
1 24 jeremybenn
/*
2
 * This file is part of SIS.
3
 *
4
 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5
 * European Space Agency
6
 *
7
 * This program is free software; you can redistribute it and/or modify it under
8
 * the terms of the GNU General Public License as published by the Free
9
 * Software Foundation; either version 2 of the License, or (at your option)
10
 * any later version.
11
 *
12
 * This program is distributed in the hope that it will be useful, but WITHOUT
13
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15
 * more details.
16
 *
17
 * You should have received a copy of the GNU General Public License along with
18
 * this program; if not, write to the Free Software Foundation, Inc., 675
19
 * Mass Ave, Cambridge, MA 02139, USA.
20
 *
21
 */
22
 
23
/* The control space devices */
24
 
25
#include <sys/types.h>
26
#include <stdio.h>
27
#include <termios.h>
28
#include <sys/fcntl.h>
29
#include <sys/file.h>
30
#include <unistd.h>
31
#include "sis.h"
32
#include "end.h"
33
#include "sim-config.h"
34
 
35
extern int      ctrl_c;
36
extern int32    sis_verbose;
37
extern int32    sparclite, sparclite_board;
38
extern int      rom8,wrp,uben;
39
extern char     uart_dev1[], uart_dev2[];
40
 
41
int dumbio = 0; /* normal, smart, terminal oriented IO by default */
42
 
43
/* MEC registers */
44
#define MEC_START       0x01f80000
45
#define MEC_END         0x01f80100
46
 
47
/* Memory exception waitstates */
48
#define MEM_EX_WS       1
49
 
50
/* ERC32 always adds one waitstate during RAM std */
51
#define STD_WS 1
52
 
53
#ifdef ERRINJ
54
extern int errmec;
55
#endif
56
 
57
/* The target's byte order is big-endian by default until we load a
58
   little-endian program.  */
59
 
60
int     current_target_byte_order = BIG_ENDIAN;
61
 
62
#define MEC_WS  0                /* Waitstates per MEC access (0 ws) */
63
#define MOK     0
64
 
65
/* MEC register addresses */
66
 
67
#define MEC_MCR         0x000
68
#define MEC_SFR         0x004
69
#define MEC_PWDR        0x008
70
#define MEC_MEMCFG      0x010
71
#define MEC_IOCR        0x014
72
#define MEC_WCR         0x018
73
 
74
#define MEC_MAR0        0x020
75
#define MEC_MAR1        0x024
76
 
77
#define MEC_SSA1        0x020
78
#define MEC_SEA1        0x024
79
#define MEC_SSA2        0x028
80
#define MEC_SEA2        0x02C
81
#define MEC_ISR         0x044
82
#define MEC_IPR         0x048
83
#define MEC_IMR         0x04C
84
#define MEC_ICR         0x050
85
#define MEC_IFR         0x054
86
#define MEC_WDOG        0x060
87
#define MEC_TRAPD       0x064
88
#define MEC_RTC_COUNTER 0x080
89
#define MEC_RTC_RELOAD  0x080
90
#define MEC_RTC_SCALER  0x084
91
#define MEC_GPT_COUNTER 0x088
92
#define MEC_GPT_RELOAD  0x088
93
#define MEC_GPT_SCALER  0x08C
94
#define MEC_TIMER_CTRL  0x098
95
#define MEC_SFSR        0x0A0
96
#define MEC_FFAR        0x0A4
97
#define MEC_ERSR        0x0B0
98
#define MEC_DBG         0x0C0
99
#define MEC_TCR         0x0D0
100
 
101
#define MEC_BRK         0x0C4
102
#define MEC_WPR         0x0C8
103
 
104
#define MEC_UARTA       0x0E0
105
#define MEC_UARTB       0x0E4
106
#define MEC_UART_CTRL   0x0E8
107
#define SIM_LOAD        0x0F0
108
 
109
/* Memory exception causes */
110
#define PROT_EXC        0x3
111
#define UIMP_ACC        0x4
112
#define MEC_ACC         0x6
113
#define WATCH_EXC       0xa
114
#define BREAK_EXC       0xb
115
 
116
/* Size of UART buffers (bytes) */
117
#define UARTBUF 1024
118
 
119
/* Number of simulator ticks between flushing the UARTS.         */
120
/* For good performance, keep above 1000                         */
121
#define UART_FLUSH_TIME   3000
122
 
123
/* MEC timer control register bits */
124
#define TCR_GACR 1
125
#define TCR_GACL 2
126
#define TCR_GASE 4
127
#define TCR_GASL 8
128
#define TCR_TCRCR 0x100
129
#define TCR_TCRCL 0x200
130
#define TCR_TCRSE 0x400
131
#define TCR_TCRSL 0x800
132
 
133
/* New uart defines */
134
#define UART_TX_TIME    1000
135
#define UART_RX_TIME    1000
136
#define UARTA_DR        0x1
137
#define UARTA_SRE       0x2
138
#define UARTA_HRE       0x4
139
#define UARTA_OR        0x40
140
#define UARTA_CLR       0x80
141
#define UARTB_DR        0x10000
142
#define UARTB_SRE       0x20000
143
#define UARTB_HRE       0x40000
144
#define UARTB_OR        0x400000
145
#define UARTB_CLR       0x800000
146
 
147
#define UART_DR         0x100
148
#define UART_TSE        0x200
149
#define UART_THE        0x400
150
 
151
/* MEC registers */
152
 
153
static char     fname[256];
154
static int32    find = 0;
155
static uint32   mec_ssa[2];     /* Write protection start address */
156
static uint32   mec_sea[2];     /* Write protection end address */
157
static uint32   mec_wpr[2];     /* Write protection control fields */
158
static uint32   mec_sfsr;
159
static uint32   mec_ffar;
160
static uint32   mec_ipr;
161
static uint32   mec_imr;
162
static uint32   mec_isr;
163
static uint32   mec_icr;
164
static uint32   mec_ifr;
165
static uint32   mec_mcr;        /* MEC control register */
166
static uint32   mec_memcfg;     /* Memory control register */
167
static uint32   mec_wcr;        /* MEC waitstate register */
168
static uint32   mec_iocr;       /* MEC IO control register */
169
static uint32   posted_irq;
170
static uint32   mec_ersr;       /* MEC error and status register */
171
static uint32   mec_tcr;        /* MEC test comtrol register */
172
 
173
static uint32   rtc_counter;
174
static uint32   rtc_reload;
175
static uint32   rtc_scaler;
176
static uint32   rtc_scaler_start;
177
static uint32   rtc_enabled;
178
static uint32   rtc_cr;
179
static uint32   rtc_se;
180
 
181
static uint32   gpt_counter;
182
static uint32   gpt_reload;
183
static uint32   gpt_scaler;
184
static uint32   gpt_scaler_start;
185
static uint32   gpt_enabled;
186
static uint32   gpt_cr;
187
static uint32   gpt_se;
188
 
189
static uint32   wdog_scaler;
190
static uint32   wdog_counter;
191
static uint32   wdog_rst_delay;
192
static uint32   wdog_rston;
193
 
194
enum wdog_type {
195
    init, disabled, enabled, stopped
196
};
197
 
198
static enum wdog_type wdog_status;
199
 
200
 
201
/* ROM size 1024 Kbyte */
202
#define ROM_SZ          0x100000
203
#define ROM_MASK        0x0fffff
204
 
205
/* RAM size 4 Mbyte */
206
#define RAM_START       0x02000000
207
#define RAM_END         0x02400000
208
#define RAM_MASK        0x003fffff
209
 
210
/* SPARClite boards all seem to have RAM at the same place. */
211
#define RAM_START_SLITE 0x40000000
212
#define RAM_END_SLITE   0x40400000
213
#define RAM_MASK_SLITE  0x003fffff
214
 
215
/* Memory support variables */
216
 
217
static uint32   mem_ramr_ws;    /* RAM read waitstates */
218
static uint32   mem_ramw_ws;    /* RAM write waitstates */
219
static uint32   mem_romr_ws;    /* ROM read waitstates */
220
static uint32   mem_romw_ws;    /* ROM write waitstates */
221
static uint32   mem_ramstart;   /* RAM start */
222
static uint32   mem_ramend;     /* RAM end */
223
static uint32   mem_rammask;    /* RAM address mask */
224
static uint32   mem_ramsz;      /* RAM size */
225
static uint32   mem_romsz;      /* ROM size */
226
static uint32   mem_accprot;    /* RAM write protection enabled */
227
static uint32   mem_blockprot;  /* RAM block write protection enabled */
228
 
229
static unsigned char    romb[ROM_SZ];
230
static unsigned char    ramb[RAM_END - RAM_START];
231
 
232
 
233
/* UART support variables */
234
 
235
static int32    fd1, fd2;       /* file descriptor for input file */
236
static int32    Ucontrol;       /* UART status register */
237
static unsigned char aq[UARTBUF], bq[UARTBUF];
238
static int32    anum, aind = 0;
239
static int32    bnum, bind = 0;
240
static char     wbufa[UARTBUF], wbufb[UARTBUF];
241
static unsigned wnuma;
242
static unsigned wnumb;
243
static FILE    *f1in, *f1out, *f2in, *f2out;
244
static struct termios ioc1, ioc2, iocold1, iocold2;
245
static int      f1open = 0, f2open = 0;
246
 
247
static char     uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
248
static uint32   uart_stat_reg;
249
static uint32   uarta_data, uartb_data;
250
 
251
#ifdef ERA
252
int era = 0;
253
int erareg;
254
#endif
255
 
256
/* Forward declarations */
257
 
258
static void     decode_ersr PARAMS ((void));
259
#ifdef ERRINJ
260
static void     iucomperr PARAMS ((void));
261
#endif
262
static void     mecparerror PARAMS ((void));
263
static void     decode_memcfg PARAMS ((void));
264
static void     decode_wcr PARAMS ((void));
265
static void     decode_mcr PARAMS ((void));
266
static void     close_port PARAMS ((void));
267
static void     mec_reset PARAMS ((void));
268
static void     mec_intack PARAMS ((int32 level));
269
static void     chk_irq PARAMS ((void));
270
static void     mec_irq PARAMS ((int32 level));
271
static void     set_sfsr PARAMS ((uint32 fault, uint32 addr,
272
                                  uint32 asi, uint32 read));
273
static int32    mec_read PARAMS ((uint32 addr, uint32 asi, uint32 *data));
274
static int      mec_write PARAMS ((uint32 addr, uint32 data));
275
static void     port_init PARAMS ((void));
276
static uint32   read_uart PARAMS ((uint32 addr));
277
static void     write_uart PARAMS ((uint32 addr, uint32 data));
278
static void     flush_uart PARAMS ((void));
279
static void     uarta_tx PARAMS ((void));
280
static void     uartb_tx PARAMS ((void));
281
static void     uart_rx PARAMS ((caddr_t arg));
282
static void     uart_intr PARAMS ((caddr_t arg));
283
static void     uart_irq_start PARAMS ((void));
284
static void     wdog_intr PARAMS ((caddr_t arg));
285
static void     wdog_start PARAMS ((void));
286
static void     rtc_intr PARAMS ((caddr_t arg));
287
static void     rtc_start PARAMS ((void));
288
static uint32   rtc_counter_read PARAMS ((void));
289
static void     rtc_scaler_set PARAMS ((uint32 val));
290
static void     rtc_reload_set PARAMS ((uint32 val));
291
static void     gpt_intr PARAMS ((caddr_t arg));
292
static void     gpt_start PARAMS ((void));
293
static uint32   gpt_counter_read PARAMS ((void));
294
static void     gpt_scaler_set PARAMS ((uint32 val));
295
static void     gpt_reload_set PARAMS ((uint32 val));
296
static void     timer_ctrl PARAMS ((uint32 val));
297
static unsigned char *
298
                get_mem_ptr PARAMS ((uint32 addr, uint32 size));
299
 
300
static void     fetch_bytes PARAMS ((int asi, unsigned char *mem,
301
                                     uint32 *data, int sz));
302
 
303
static void     store_bytes PARAMS ((unsigned char *mem, uint32 *data, int sz));
304
 
305
extern int      ext_irl;
306
 
307
 
308
/* One-time init */
309
 
310
void
311
init_sim()
312
{
313
    port_init();
314
}
315
 
316
/* Power-on reset init */
317
 
318
void
319
reset()
320
{
321
    mec_reset();
322
    uart_irq_start();
323
    wdog_start();
324
}
325
 
326
static void
327
decode_ersr()
328
{
329
    if (mec_ersr & 0x01) {
330
        if (!(mec_mcr & 0x20)) {
331
            if (mec_mcr & 0x40) {
332
                sys_reset();
333
                mec_ersr = 0x8000;
334
                if (sis_verbose)
335
                    printf("Error manager reset - IU in error mode\n");
336
            } else {
337
                sys_halt();
338
                mec_ersr |= 0x2000;
339
                if (sis_verbose)
340
                    printf("Error manager halt - IU in error mode\n");
341
            }
342
        } else
343
            mec_irq(1);
344
    }
345
    if (mec_ersr & 0x04) {
346
        if (!(mec_mcr & 0x200)) {
347
            if (mec_mcr & 0x400) {
348
                sys_reset();
349
                mec_ersr = 0x8000;
350
                if (sis_verbose)
351
                    printf("Error manager reset - IU comparison error\n");
352
            } else {
353
                sys_halt();
354
                mec_ersr |= 0x2000;
355
                if (sis_verbose)
356
                    printf("Error manager halt - IU comparison error\n");
357
            }
358
        } else
359
            mec_irq(1);
360
    }
361
    if (mec_ersr & 0x20) {
362
        if (!(mec_mcr & 0x2000)) {
363
            if (mec_mcr & 0x4000) {
364
                sys_reset();
365
                mec_ersr = 0x8000;
366
                if (sis_verbose)
367
                    printf("Error manager reset - MEC hardware error\n");
368
            } else {
369
                sys_halt();
370
                mec_ersr |= 0x2000;
371
                if (sis_verbose)
372
                    printf("Error manager halt - MEC hardware error\n");
373
            }
374
        } else
375
            mec_irq(1);
376
    }
377
}
378
 
379
#ifdef ERRINJ
380
static void
381
iucomperr()
382
{
383
    mec_ersr |= 0x04;
384
    decode_ersr();
385
}
386
#endif
387
 
388
static void
389
mecparerror()
390
{
391
    mec_ersr |= 0x20;
392
    decode_ersr();
393
}
394
 
395
 
396
/* IU error mode manager */
397
 
398
void
399
error_mode(pc)
400
    uint32          pc;
401
{
402
 
403
    mec_ersr |= 0x1;
404
    decode_ersr();
405
}
406
 
407
 
408
/* Check memory settings */
409
 
410
static void
411
decode_memcfg()
412
{
413
    if (rom8) mec_memcfg &= ~0x20000;
414
    else mec_memcfg |= 0x20000;
415
 
416
    mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
417
    mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
418
 
419
    if (sparclite_board) {
420
        mem_ramstart = RAM_START_SLITE;
421
        mem_ramend = RAM_END_SLITE;
422
        mem_rammask = RAM_MASK_SLITE;
423
    }
424
    else {
425
        mem_ramstart = RAM_START;
426
        mem_ramend = RAM_END;
427
        mem_rammask = RAM_MASK;
428
    }
429
    if (sis_verbose)
430
        printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
431
               mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
432
}
433
 
434
static void
435
decode_wcr()
436
{
437
    mem_ramr_ws = mec_wcr & 3;
438
    mem_ramw_ws = (mec_wcr >> 2) & 3;
439
    mem_romr_ws = (mec_wcr >> 4) & 0x0f;
440
    if (rom8) {
441
        if (mem_romr_ws > 0 )  mem_romr_ws--;
442
        mem_romr_ws = 5 + (4*mem_romr_ws);
443
    }
444
    mem_romw_ws = (mec_wcr >> 8) & 0x0f;
445
    if (sis_verbose)
446
        printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
447
               mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
448
}
449
 
450
static void
451
decode_mcr()
452
{
453
    mem_accprot = (mec_wpr[0] | mec_wpr[1]);
454
    mem_blockprot = (mec_mcr >> 3) & 1;
455
    if (sis_verbose && mem_accprot)
456
        printf("Memory block write protection enabled\n");
457
    if (mec_mcr & 0x08000) {
458
        mec_ersr |= 0x20;
459
        decode_ersr();
460
    }
461
    if (sis_verbose && (mec_mcr & 2))
462
        printf("Software reset enabled\n");
463
    if (sis_verbose && (mec_mcr & 1))
464
        printf("Power-down mode enabled\n");
465
}
466
 
467
/* Flush ports when simulator stops */
468
 
469
void
470
sim_halt()
471
{
472
#ifdef FAST_UART
473
    flush_uart();
474
#endif
475
}
476
 
477
int
478
sim_stop(SIM_DESC sd)
479
{
480
  ctrl_c = 1;
481
  return 1;
482
}
483
 
484
static void
485
close_port()
486
{
487
    if (f1open && f1in != stdin)
488
        fclose(f1in);
489
    if (f2open && f2in != stdin)
490
        fclose(f2in);
491
}
492
 
493
void
494
exit_sim()
495
{
496
    close_port();
497
}
498
 
499
static void
500
mec_reset()
501
{
502
    int             i;
503
 
504
    find = 0;
505
    for (i = 0; i < 2; i++)
506
        mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
507
    mec_mcr = 0x01350014;
508
    mec_iocr = 0;
509
    mec_sfsr = 0x078;
510
    mec_ffar = 0;
511
    mec_ipr = 0;
512
    mec_imr = 0x7ffe;
513
    mec_isr = 0;
514
    mec_icr = 0;
515
    mec_ifr = 0;
516
    mec_memcfg = 0x10000;
517
    mec_wcr = -1;
518
    mec_ersr = 0;                /* MEC error and status register */
519
    mec_tcr = 0;         /* MEC test comtrol register */
520
 
521
    decode_memcfg();
522
    decode_wcr();
523
    decode_mcr();
524
 
525
    posted_irq = 0;
526
    wnuma = wnumb = 0;
527
    anum = aind = bnum = bind = 0;
528
 
529
    uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
530
    uarta_data = uartb_data = UART_THE | UART_TSE;
531
 
532
    rtc_counter = 0xffffffff;
533
    rtc_reload = 0xffffffff;
534
    rtc_scaler = 0xff;
535
    rtc_enabled = 0;
536
    rtc_cr = 0;
537
    rtc_se = 0;
538
 
539
    gpt_counter = 0xffffffff;
540
    gpt_reload = 0xffffffff;
541
    gpt_scaler = 0xffff;
542
    gpt_enabled = 0;
543
    gpt_cr = 0;
544
    gpt_se = 0;
545
 
546
    wdog_scaler = 255;
547
    wdog_rst_delay = 255;
548
    wdog_counter = 0xffff;
549
    wdog_rston = 0;
550
    wdog_status = init;
551
 
552
#ifdef ERA
553
    erareg = 0;
554
#endif
555
 
556
}
557
 
558
 
559
 
560
static void
561
mec_intack(level)
562
    int32           level;
563
{
564
    int             irq_test;
565
 
566
    if (sis_verbose)
567
        printf("interrupt %d acknowledged\n", level);
568
    irq_test = mec_tcr & 0x80000;
569
    if ((irq_test) && (mec_ifr & (1 << level)))
570
        mec_ifr &= ~(1 << level);
571
    else
572
        mec_ipr &= ~(1 << level);
573
   chk_irq();
574
}
575
 
576
static void
577
chk_irq()
578
{
579
    int32           i;
580
    uint32          itmp;
581
    int             old_irl;
582
 
583
    old_irl = ext_irl;
584
    if (mec_tcr & 0x80000) itmp = mec_ifr;
585
    else itmp  = 0;
586
    itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
587
    ext_irl = 0;
588
    if (itmp != 0) {
589
        for (i = 15; i > 0; i--) {
590
            if (((itmp >> i) & 1) != 0) {
591
                if ((sis_verbose) && (i > old_irl))
592
                    printf("IU irl: %d\n", i);
593
                ext_irl = i;
594
                set_int(i, mec_intack, i);
595
                break;
596
            }
597
        }
598
    }
599
}
600
 
601
static void
602
mec_irq(level)
603
    int32           level;
604
{
605
    mec_ipr |= (1 << level);
606
    chk_irq();
607
}
608
 
609
static void
610
set_sfsr(fault, addr, asi, read)
611
    uint32          fault;
612
    uint32          addr;
613
    uint32          asi;
614
    uint32          read;
615
{
616
    if ((asi == 0xa) || (asi == 0xb)) {
617
        mec_ffar = addr;
618
        mec_sfsr = (fault << 3) | (!read << 15);
619
        mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
620
        switch (asi) {
621
        case 0xa:
622
            mec_sfsr |= 0x0004;
623
            break;
624
        case 0xb:
625
            mec_sfsr |= 0x1004;
626
            break;
627
        }
628
    }
629
}
630
 
631
static int32
632
mec_read(addr, asi, data)
633
    uint32          addr;
634
    uint32          asi;
635
    uint32         *data;
636
{
637
 
638
    switch (addr & 0x0ff) {
639
 
640
    case MEC_MCR:               /* 0x00 */
641
        *data = mec_mcr;
642
        break;
643
 
644
    case MEC_MEMCFG:            /* 0x10 */
645
        *data = mec_memcfg;
646
        break;
647
 
648
    case MEC_IOCR:
649
        *data = mec_iocr;       /* 0x14 */
650
        break;
651
 
652
    case MEC_SSA1:              /* 0x20 */
653
        *data = mec_ssa[0] | (mec_wpr[0] << 23);
654
        break;
655
    case MEC_SEA1:              /* 0x24 */
656
        *data = mec_sea[0];
657
        break;
658
    case MEC_SSA2:              /* 0x28 */
659
        *data = mec_ssa[1] | (mec_wpr[1] << 23);
660
        break;
661
    case MEC_SEA2:              /* 0x2c */
662
        *data = mec_sea[1];
663
        break;
664
 
665
    case MEC_ISR:               /* 0x44 */
666
        *data = mec_isr;
667
        break;
668
 
669
    case MEC_IPR:               /* 0x48 */
670
        *data = mec_ipr;
671
        break;
672
 
673
    case MEC_IMR:               /* 0x4c */
674
        *data = mec_imr;
675
        break;
676
 
677
    case MEC_IFR:               /* 0x54 */
678
        *data = mec_ifr;
679
        break;
680
 
681
    case MEC_RTC_COUNTER:       /* 0x80 */
682
        *data = rtc_counter_read();
683
        break;
684
    case MEC_RTC_SCALER:        /* 0x84 */
685
        if (rtc_enabled)
686
            *data = rtc_scaler - (now() - rtc_scaler_start);
687
        else
688
            *data = rtc_scaler;
689
        break;
690
 
691
    case MEC_GPT_COUNTER:       /* 0x88 */
692
        *data = gpt_counter_read();
693
        break;
694
 
695
    case MEC_GPT_SCALER:        /* 0x8c */
696
        if (rtc_enabled)
697
            *data = gpt_scaler - (now() - gpt_scaler_start);
698
        else
699
            *data = gpt_scaler;
700
        break;
701
 
702
 
703
    case MEC_SFSR:              /* 0xA0 */
704
        *data = mec_sfsr;
705
        break;
706
 
707
    case MEC_FFAR:              /* 0xA4 */
708
        *data = mec_ffar;
709
        break;
710
 
711
    case SIM_LOAD:
712
        fname[find] = 0;
713
        if (find == 0)
714
            strcpy(fname, "simload");
715
        find = bfd_load(fname);
716
        if (find == -1)
717
            *data = 0;
718
        else
719
            *data = 1;
720
        find = 0;
721
        break;
722
 
723
    case MEC_ERSR:              /* 0xB0 */
724
        *data = mec_ersr;
725
        break;
726
 
727
    case MEC_TCR:               /* 0xD0 */
728
        *data = mec_tcr;
729
        break;
730
 
731
    case MEC_UARTA:             /* 0xE0 */
732
    case MEC_UARTB:             /* 0xE4 */
733
        if (asi != 0xb) {
734
            set_sfsr(MEC_ACC, addr, asi, 1);
735
            return (1);
736
        }
737
        *data = read_uart(addr);
738
        break;
739
 
740
    case MEC_UART_CTRL:         /* 0xE8 */
741
 
742
        *data = read_uart(addr);
743
        break;
744
 
745
    default:
746
        set_sfsr(MEC_ACC, addr, asi, 1);
747
        return (1);
748
        break;
749
    }
750
    return (MOK);
751
}
752
 
753
static int
754
mec_write(addr, data)
755
    uint32          addr;
756
    uint32          data;
757
{
758
    if (sis_verbose > 1)
759
        printf("MEC write a: %08x, d: %08x\n",addr,data);
760
    switch (addr & 0x0ff) {
761
 
762
    case MEC_MCR:
763
        mec_mcr = data;
764
        decode_mcr();
765
        if (mec_mcr & 0x08000) mecparerror();
766
        break;
767
 
768
    case MEC_SFR:
769
        if (mec_mcr & 0x2) {
770
            sys_reset();
771
            mec_ersr = 0x4000;
772
            if (sis_verbose)
773
                printf(" Software reset issued\n");
774
        }
775
        break;
776
 
777
    case MEC_IOCR:
778
        mec_iocr = data;
779
        if (mec_iocr & 0xC0C0C0C0) mecparerror();
780
        break;
781
 
782
    case MEC_SSA1:              /* 0x20 */
783
        if (data & 0xFE000000) mecparerror();
784
        mec_ssa[0] = data & 0x7fffff;
785
        mec_wpr[0] = (data >> 23) & 0x03;
786
        mem_accprot = mec_wpr[0] || mec_wpr[1];
787
        if (sis_verbose && mec_wpr[0])
788
            printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
789
                   mec_ssa[0] << 2, mec_sea[0] << 2);
790
        break;
791
    case MEC_SEA1:              /* 0x24 */
792
        if (data & 0xFF800000) mecparerror();
793
        mec_sea[0] = data & 0x7fffff;
794
        break;
795
    case MEC_SSA2:              /* 0x28 */
796
        if (data & 0xFE000000) mecparerror();
797
        mec_ssa[1] = data & 0x7fffff;
798
        mec_wpr[1] = (data >> 23) & 0x03;
799
        mem_accprot = mec_wpr[0] || mec_wpr[1];
800
        if (sis_verbose && mec_wpr[1])
801
            printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
802
                   mec_ssa[1] << 2, mec_sea[1] << 2);
803
        break;
804
    case MEC_SEA2:              /* 0x2c */
805
        if (data & 0xFF800000) mecparerror();
806
        mec_sea[1] = data & 0x7fffff;
807
        break;
808
 
809
    case MEC_UARTA:
810
    case MEC_UARTB:
811
        if (data & 0xFFFFFF00) mecparerror();
812
    case MEC_UART_CTRL:
813
        if (data & 0xFF00FF00) mecparerror();
814
        write_uart(addr, data);
815
        break;
816
 
817
    case MEC_GPT_RELOAD:
818
        gpt_reload_set(data);
819
        break;
820
 
821
    case MEC_GPT_SCALER:
822
        if (data & 0xFFFF0000) mecparerror();
823
        gpt_scaler_set(data);
824
        break;
825
 
826
    case MEC_TIMER_CTRL:
827
        if (data & 0xFFFFF0F0) mecparerror();
828
        timer_ctrl(data);
829
        break;
830
 
831
    case MEC_RTC_RELOAD:
832
        rtc_reload_set(data);
833
        break;
834
 
835
    case MEC_RTC_SCALER:
836
        if (data & 0xFFFFFF00) mecparerror();
837
        rtc_scaler_set(data);
838
        break;
839
 
840
    case MEC_SFSR:              /* 0xA0 */
841
        if (data & 0xFFFF0880) mecparerror();
842
        mec_sfsr = 0x78;
843
        break;
844
 
845
    case MEC_ISR:
846
        if (data & 0xFFFFE000) mecparerror();
847
        mec_isr = data;
848
        break;
849
 
850
    case MEC_IMR:               /* 0x4c */
851
 
852
        if (data & 0xFFFF8001) mecparerror();
853
        mec_imr = data & 0x7ffe;
854
        chk_irq();
855
        break;
856
 
857
    case MEC_ICR:               /* 0x50 */
858
 
859
        if (data & 0xFFFF0001) mecparerror();
860
        mec_ipr &= ~data & 0x0fffe;
861
        chk_irq();
862
        break;
863
 
864
    case MEC_IFR:               /* 0x54 */
865
 
866
        if (mec_tcr & 0x080000) {
867
            if (data & 0xFFFF0001) mecparerror();
868
            mec_ifr = data & 0xfffe;
869
            chk_irq();
870
        }
871
        break;
872
    case SIM_LOAD:
873
        fname[find++] = (char) data;
874
        break;
875
 
876
 
877
    case MEC_MEMCFG:            /* 0x10 */
878
        if (data & 0xC0E08000) mecparerror();
879
        mec_memcfg = data;
880
        decode_memcfg();
881
        if (mec_memcfg & 0xc0e08000)
882
            mecparerror();
883
        break;
884
 
885
    case MEC_WCR:               /* 0x18 */
886
        mec_wcr = data;
887
        decode_wcr();
888
        break;
889
 
890
    case MEC_ERSR:              /* 0xB0 */
891
        if (mec_tcr & 0x100000)
892
            if (data & 0xFFFFEFC0) mecparerror();
893
            mec_ersr = data & 0x103f;
894
        break;
895
 
896
    case MEC_TCR:               /* 0xD0 */
897
        if (data & 0xFFE1FFC0) mecparerror();
898
        mec_tcr = data & 0x1e003f;
899
        break;
900
 
901
    case MEC_WDOG:              /* 0x60 */
902
        wdog_scaler = (data >> 16) & 0x0ff;
903
        wdog_counter = data & 0x0ffff;
904
        wdog_rst_delay = data >> 24;
905
        wdog_rston = 0;
906
        if (wdog_status == stopped)
907
            wdog_start();
908
        wdog_status = enabled;
909
        break;
910
 
911
    case MEC_TRAPD:             /* 0x64 */
912
        if (wdog_status == init) {
913
            wdog_status = disabled;
914
            if (sis_verbose)
915
                printf("Watchdog disabled\n");
916
        }
917
        break;
918
 
919
    case MEC_PWDR:
920
        if (mec_mcr & 1)
921
            wait_for_irq();
922
        break;
923
 
924
    default:
925
        set_sfsr(MEC_ACC, addr, 0xb, 0);
926
        return (1);
927
        break;
928
    }
929
    return (MOK);
930
}
931
 
932
 
933
/* MEC UARTS */
934
 
935
static int      ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
936
 
937
void
938
init_stdio()
939
{
940
    if (dumbio)
941
        return; /* do nothing */
942
    if (!ifd1)
943
        tcsetattr(0, TCSANOW, &ioc1);
944
    if (!ifd2)
945
        tcsetattr(0, TCSANOW, &ioc2);
946
}
947
 
948
void
949
restore_stdio()
950
{
951
    if (dumbio)
952
        return; /* do nothing */
953
    if (!ifd1)
954
        tcsetattr(0, TCSANOW, &iocold1);
955
    if (!ifd2)
956
        tcsetattr(0, TCSANOW, &iocold2);
957
}
958
 
959
#define DO_STDIO_READ( _fd_, _buf_, _len_ )          \
960
             ( dumbio                                \
961
               ? (0) /* no bytes read, no delay */   \
962
               : read( _fd_, _buf_, _len_ ) )
963
 
964
 
965
static void
966
port_init()
967
{
968
 
969
    if (uben) {
970
    f2in = stdin;
971
    f1in = NULL;
972
    f2out = stdout;
973
    f1out = NULL;
974
    } else {
975
    f1in = stdin;
976
    f2in = NULL;
977
    f1out = stdout;
978
    f2out = NULL;
979
    }
980
    if (uart_dev1[0] != 0)
981
        if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
982
            printf("Warning, couldn't open output device %s\n", uart_dev1);
983
        } else {
984
            if (sis_verbose)
985
                printf("serial port A on %s\n", uart_dev1);
986
            f1in = f1out = fdopen(fd1, "r+");
987
            setbuf(f1out, NULL);
988
            f1open = 1;
989
        }
990
    if (f1in) ifd1 = fileno(f1in);
991
    if (ifd1 == 0) {
992
        if (sis_verbose)
993
            printf("serial port A on stdin/stdout\n");
994
        if (!dumbio) {
995
            tcgetattr(ifd1, &ioc1);
996
            iocold1 = ioc1;
997
            ioc1.c_lflag &= ~(ICANON | ECHO);
998
            ioc1.c_cc[VMIN] = 0;
999
            ioc1.c_cc[VTIME] = 0;
1000
        }
1001
        f1open = 1;
1002
    }
1003
 
1004
    if (f1out) {
1005
        ofd1 = fileno(f1out);
1006
        if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1007
    }
1008
 
1009
    if (uart_dev2[0] != 0)
1010
        if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1011
            printf("Warning, couldn't open output device %s\n", uart_dev2);
1012
        } else {
1013
            if (sis_verbose)
1014
                printf("serial port B on %s\n", uart_dev2);
1015
            f2in = f2out = fdopen(fd2, "r+");
1016
            setbuf(f2out, NULL);
1017
            f2open = 1;
1018
        }
1019
    if (f2in)  ifd2 = fileno(f2in);
1020
    if (ifd2 == 0) {
1021
        if (sis_verbose)
1022
            printf("serial port B on stdin/stdout\n");
1023
        if (!dumbio) {
1024
            tcgetattr(ifd2, &ioc2);
1025
            iocold2 = ioc2;
1026
            ioc2.c_lflag &= ~(ICANON | ECHO);
1027
            ioc2.c_cc[VMIN] = 0;
1028
            ioc2.c_cc[VTIME] = 0;
1029
        }
1030
        f2open = 1;
1031
    }
1032
 
1033
    if (f2out) {
1034
        ofd2 = fileno(f2out);
1035
        if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1036
    }
1037
 
1038
    wnuma = wnumb = 0;
1039
 
1040
}
1041
 
1042
static uint32
1043
read_uart(addr)
1044
    uint32          addr;
1045
{
1046
 
1047
    unsigned        tmp;
1048
 
1049
    tmp = 0;
1050
    switch (addr & 0xff) {
1051
 
1052
    case 0xE0:                  /* UART 1 */
1053
#ifndef _WIN32
1054
#ifdef FAST_UART
1055
 
1056
        if (aind < anum) {
1057
            if ((aind + 1) < anum)
1058
                mec_irq(4);
1059
            return (0x700 | (uint32) aq[aind++]);
1060
        } else {
1061
            if (f1open) {
1062
                anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1063
            }
1064
            if (anum > 0) {
1065
                aind = 0;
1066
                if ((aind + 1) < anum)
1067
                    mec_irq(4);
1068
                return (0x700 | (uint32) aq[aind++]);
1069
            } else {
1070
                return (0x600 | (uint32) aq[aind]);
1071
            }
1072
 
1073
        }
1074
#else
1075
        tmp = uarta_data;
1076
        uarta_data &= ~UART_DR;
1077
        uart_stat_reg &= ~UARTA_DR;
1078
        return tmp;
1079
#endif
1080
#else
1081
        return(0);
1082
#endif
1083
        break;
1084
 
1085
    case 0xE4:                  /* UART 2 */
1086
#ifndef _WIN32
1087
#ifdef FAST_UART
1088
        if (bind < bnum) {
1089
            if ((bind + 1) < bnum)
1090
                mec_irq(5);
1091
            return (0x700 | (uint32) bq[bind++]);
1092
        } else {
1093
            if (f2open) {
1094
                bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1095
            }
1096
            if (bnum > 0) {
1097
                bind = 0;
1098
                if ((bind + 1) < bnum)
1099
                    mec_irq(5);
1100
                return (0x700 | (uint32) bq[bind++]);
1101
            } else {
1102
                return (0x600 | (uint32) bq[bind]);
1103
            }
1104
 
1105
        }
1106
#else
1107
        tmp = uartb_data;
1108
        uartb_data &= ~UART_DR;
1109
        uart_stat_reg &= ~UARTB_DR;
1110
        return tmp;
1111
#endif
1112
#else
1113
        return(0);
1114
#endif
1115
        break;
1116
 
1117
    case 0xE8:                  /* UART status register  */
1118
#ifndef _WIN32
1119
#ifdef FAST_UART
1120
 
1121
        Ucontrol = 0;
1122
        if (aind < anum) {
1123
            Ucontrol |= 0x00000001;
1124
        } else {
1125
            if (f1open) {
1126
                anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1127
            }
1128
            if (anum > 0) {
1129
                Ucontrol |= 0x00000001;
1130
                aind = 0;
1131
                mec_irq(4);
1132
            }
1133
        }
1134
        if (bind < bnum) {
1135
            Ucontrol |= 0x00010000;
1136
        } else {
1137
            if (f2open) {
1138
                bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1139
            }
1140
            if (bnum > 0) {
1141
                Ucontrol |= 0x00010000;
1142
                bind = 0;
1143
                mec_irq(5);
1144
            }
1145
        }
1146
 
1147
        Ucontrol |= 0x00060006;
1148
        return (Ucontrol);
1149
#else
1150
        return (uart_stat_reg);
1151
#endif
1152
#else
1153
        return(0x00060006);
1154
#endif
1155
        break;
1156
    default:
1157
        if (sis_verbose)
1158
            printf("Read from unimplemented MEC register (%x)\n", addr);
1159
 
1160
    }
1161
    return (0);
1162
}
1163
 
1164
static void
1165
write_uart(addr, data)
1166
    uint32          addr;
1167
    uint32          data;
1168
{
1169
    unsigned char   c;
1170
 
1171
    c = (unsigned char) data;
1172
    switch (addr & 0xff) {
1173
 
1174
    case 0xE0:                  /* UART A */
1175
#ifdef FAST_UART
1176
        if (f1open) {
1177
            if (wnuma < UARTBUF)
1178
                wbufa[wnuma++] = c;
1179
            else {
1180
                while (wnuma)
1181
                    wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1182
                wbufa[wnuma++] = c;
1183
            }
1184
        }
1185
        mec_irq(4);
1186
#else
1187
        if (uart_stat_reg & UARTA_SRE) {
1188
            uarta_sreg = c;
1189
            uart_stat_reg &= ~UARTA_SRE;
1190
            event(uarta_tx, 0, UART_TX_TIME);
1191
        } else {
1192
            uarta_hreg = c;
1193
            uart_stat_reg &= ~UARTA_HRE;
1194
        }
1195
#endif
1196
        break;
1197
 
1198
    case 0xE4:                  /* UART B */
1199
#ifdef FAST_UART
1200
        if (f2open) {
1201
            if (wnumb < UARTBUF)
1202
                wbufb[wnumb++] = c;
1203
            else {
1204
                while (wnumb)
1205
                    wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1206
                wbufb[wnumb++] = c;
1207
            }
1208
        }
1209
        mec_irq(5);
1210
#else
1211
        if (uart_stat_reg & UARTB_SRE) {
1212
            uartb_sreg = c;
1213
            uart_stat_reg &= ~UARTB_SRE;
1214
            event(uartb_tx, 0, UART_TX_TIME);
1215
        } else {
1216
            uartb_hreg = c;
1217
            uart_stat_reg &= ~UARTB_HRE;
1218
        }
1219
#endif
1220
        break;
1221
    case 0xE8:                  /* UART status register */
1222
#ifndef FAST_UART
1223
        if (data & UARTA_CLR) {
1224
            uart_stat_reg &= 0xFFFF0000;
1225
            uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1226
        }
1227
        if (data & UARTB_CLR) {
1228
            uart_stat_reg &= 0x0000FFFF;
1229
            uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1230
        }
1231
#endif
1232
        break;
1233
    default:
1234
        if (sis_verbose)
1235
            printf("Write to unimplemented MEC register (%x)\n", addr);
1236
 
1237
    }
1238
}
1239
 
1240
static void
1241
flush_uart()
1242
{
1243
    while (wnuma && f1open)
1244
        wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1245
    while (wnumb && f2open)
1246
        wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1247
}
1248
 
1249
 
1250
 
1251
static void
1252
uarta_tx()
1253
{
1254
 
1255
    while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1256
    if (uart_stat_reg & UARTA_HRE) {
1257
        uart_stat_reg |= UARTA_SRE;
1258
    } else {
1259
        uarta_sreg = uarta_hreg;
1260
        uart_stat_reg |= UARTA_HRE;
1261
        event(uarta_tx, 0, UART_TX_TIME);
1262
    }
1263
    mec_irq(4);
1264
}
1265
 
1266
static void
1267
uartb_tx()
1268
{
1269
    while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1270
    if (uart_stat_reg & UARTB_HRE) {
1271
        uart_stat_reg |= UARTB_SRE;
1272
    } else {
1273
        uartb_sreg = uartb_hreg;
1274
        uart_stat_reg |= UARTB_HRE;
1275
        event(uartb_tx, 0, UART_TX_TIME);
1276
    }
1277
    mec_irq(5);
1278
}
1279
 
1280
static void
1281
uart_rx(arg)
1282
    caddr_t         arg;
1283
{
1284
    int32           rsize;
1285
    char            rxd;
1286
 
1287
 
1288
    rsize = 0;
1289
    if (f1open)
1290
        rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1291
    if (rsize > 0) {
1292
        uarta_data = UART_DR | rxd;
1293
        if (uart_stat_reg & UARTA_HRE)
1294
            uarta_data |= UART_THE;
1295
        if (uart_stat_reg & UARTA_SRE)
1296
            uarta_data |= UART_TSE;
1297
        if (uart_stat_reg & UARTA_DR) {
1298
            uart_stat_reg |= UARTA_OR;
1299
            mec_irq(7);         /* UART error interrupt */
1300
        }
1301
        uart_stat_reg |= UARTA_DR;
1302
        mec_irq(4);
1303
    }
1304
    rsize = 0;
1305
    if (f2open)
1306
        rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1307
    if (rsize) {
1308
        uartb_data = UART_DR | rxd;
1309
        if (uart_stat_reg & UARTB_HRE)
1310
            uartb_data |= UART_THE;
1311
        if (uart_stat_reg & UARTB_SRE)
1312
            uartb_data |= UART_TSE;
1313
        if (uart_stat_reg & UARTB_DR) {
1314
            uart_stat_reg |= UARTB_OR;
1315
            mec_irq(7);         /* UART error interrupt */
1316
        }
1317
        uart_stat_reg |= UARTB_DR;
1318
        mec_irq(5);
1319
    }
1320
    event(uart_rx, 0, UART_RX_TIME);
1321
}
1322
 
1323
static void
1324
uart_intr(arg)
1325
    caddr_t         arg;
1326
{
1327
    read_uart(0xE8);            /* Check for UART interrupts every 1000 clk */
1328
    flush_uart();               /* Flush UART ports      */
1329
    event(uart_intr, 0, UART_FLUSH_TIME);
1330
}
1331
 
1332
 
1333
static void
1334
uart_irq_start()
1335
{
1336
#ifdef FAST_UART
1337
    event(uart_intr, 0, UART_FLUSH_TIME);
1338
#else
1339
#ifndef _WIN32
1340
    event(uart_rx, 0, UART_RX_TIME);
1341
#endif
1342
#endif
1343
}
1344
 
1345
/* Watch-dog */
1346
 
1347
static void
1348
wdog_intr(arg)
1349
    caddr_t         arg;
1350
{
1351
    if (wdog_status == disabled) {
1352
        wdog_status = stopped;
1353
    } else {
1354
 
1355
        if (wdog_counter) {
1356
            wdog_counter--;
1357
            event(wdog_intr, 0, wdog_scaler + 1);
1358
        } else {
1359
            if (wdog_rston) {
1360
                printf("Watchdog reset!\n");
1361
                sys_reset();
1362
                mec_ersr = 0xC000;
1363
            } else {
1364
                mec_irq(15);
1365
                wdog_rston = 1;
1366
                wdog_counter = wdog_rst_delay;
1367
                event(wdog_intr, 0, wdog_scaler + 1);
1368
            }
1369
        }
1370
    }
1371
}
1372
 
1373
static void
1374
wdog_start()
1375
{
1376
    event(wdog_intr, 0, wdog_scaler + 1);
1377
    if (sis_verbose)
1378
        printf("Watchdog started, scaler = %d, counter = %d\n",
1379
               wdog_scaler, wdog_counter);
1380
}
1381
 
1382
 
1383
/* MEC timers */
1384
 
1385
 
1386
static void
1387
rtc_intr(arg)
1388
    caddr_t         arg;
1389
{
1390
    if (rtc_counter == 0) {
1391
 
1392
        mec_irq(13);
1393
        if (rtc_cr)
1394
            rtc_counter = rtc_reload;
1395
        else
1396
            rtc_se = 0;
1397
    } else
1398
        rtc_counter -= 1;
1399
    if (rtc_se) {
1400
        event(rtc_intr, 0, rtc_scaler + 1);
1401
        rtc_scaler_start = now();
1402
        rtc_enabled = 1;
1403
    } else {
1404
        if (sis_verbose)
1405
            printf("RTC stopped\n\r");
1406
        rtc_enabled = 0;
1407
    }
1408
}
1409
 
1410
static void
1411
rtc_start()
1412
{
1413
    if (sis_verbose)
1414
        printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1415
    event(rtc_intr, 0, rtc_scaler + 1);
1416
    rtc_scaler_start = now();
1417
    rtc_enabled = 1;
1418
}
1419
 
1420
static uint32
1421
rtc_counter_read()
1422
{
1423
    return (rtc_counter);
1424
}
1425
 
1426
static void
1427
rtc_scaler_set(val)
1428
    uint32          val;
1429
{
1430
    rtc_scaler = val & 0x0ff;   /* eight-bit scaler only */
1431
}
1432
 
1433
static void
1434
rtc_reload_set(val)
1435
    uint32          val;
1436
{
1437
    rtc_reload = val;
1438
}
1439
 
1440
static void
1441
gpt_intr(arg)
1442
    caddr_t         arg;
1443
{
1444
    if (gpt_counter == 0) {
1445
        mec_irq(12);
1446
        if (gpt_cr)
1447
            gpt_counter = gpt_reload;
1448
        else
1449
            gpt_se = 0;
1450
    } else
1451
        gpt_counter -= 1;
1452
    if (gpt_se) {
1453
        event(gpt_intr, 0, gpt_scaler + 1);
1454
        gpt_scaler_start = now();
1455
        gpt_enabled = 1;
1456
    } else {
1457
        if (sis_verbose)
1458
            printf("GPT stopped\n\r");
1459
        gpt_enabled = 0;
1460
    }
1461
}
1462
 
1463
static void
1464
gpt_start()
1465
{
1466
    if (sis_verbose)
1467
        printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1468
    event(gpt_intr, 0, gpt_scaler + 1);
1469
    gpt_scaler_start = now();
1470
    gpt_enabled = 1;
1471
}
1472
 
1473
static uint32
1474
gpt_counter_read()
1475
{
1476
    return (gpt_counter);
1477
}
1478
 
1479
static void
1480
gpt_scaler_set(val)
1481
    uint32          val;
1482
{
1483
    gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1484
}
1485
 
1486
static void
1487
gpt_reload_set(val)
1488
    uint32          val;
1489
{
1490
    gpt_reload = val;
1491
}
1492
 
1493
static void
1494
timer_ctrl(val)
1495
    uint32          val;
1496
{
1497
 
1498
    rtc_cr = ((val & TCR_TCRCR) != 0);
1499
    if (val & TCR_TCRCL) {
1500
        rtc_counter = rtc_reload;
1501
    }
1502
    if (val & TCR_TCRSL) {
1503
    }
1504
    rtc_se = ((val & TCR_TCRSE) != 0);
1505
    if (rtc_se && (rtc_enabled == 0))
1506
        rtc_start();
1507
 
1508
    gpt_cr = (val & TCR_GACR);
1509
    if (val & TCR_GACL) {
1510
        gpt_counter = gpt_reload;
1511
    }
1512
    if (val & TCR_GACL) {
1513
    }
1514
    gpt_se = (val & TCR_GASE) >> 2;
1515
    if (gpt_se && (gpt_enabled == 0))
1516
        gpt_start();
1517
}
1518
 
1519
 
1520
/* Retrieve data from target memory.  MEM points to location from which
1521
   to read the data; DATA points to words where retrieved data will be
1522
   stored in host byte order.  SZ contains log(2) of the number of bytes
1523
   to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1524
   or 3 (two words). */
1525
 
1526
static void
1527
fetch_bytes (asi, mem, data, sz)
1528
    int             asi;
1529
    unsigned char  *mem;
1530
    uint32         *data;
1531
    int             sz;
1532
{
1533
    if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
1534
        || asi == 8 || asi == 9) {
1535
        switch (sz) {
1536
        case 3:
1537
            data[1] =  (((uint32) mem[7]) & 0xff) |
1538
                      ((((uint32) mem[6]) & 0xff) <<  8) |
1539
                      ((((uint32) mem[5]) & 0xff) << 16) |
1540
                      ((((uint32) mem[4]) & 0xff) << 24);
1541
            /* Fall through to 2 */
1542
        case 2:
1543
            data[0] =  (((uint32) mem[3]) & 0xff) |
1544
                      ((((uint32) mem[2]) & 0xff) <<  8) |
1545
                      ((((uint32) mem[1]) & 0xff) << 16) |
1546
                      ((((uint32) mem[0]) & 0xff) << 24);
1547
            break;
1548
        case 1:
1549
            data[0] =  (((uint32) mem[1]) & 0xff) |
1550
                      ((((uint32) mem[0]) & 0xff) << 8);
1551
            break;
1552
        case 0:
1553
            data[0] = mem[0] & 0xff;
1554
            break;
1555
 
1556
        }
1557
    } else {
1558
        switch (sz) {
1559
        case 3:
1560
            data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
1561
                      ((((uint32) mem[6]) & 0xff) << 16) |
1562
                      ((((uint32) mem[5]) & 0xff) <<  8) |
1563
                       (((uint32) mem[4]) & 0xff);
1564
            /* Fall through to 4 */
1565
        case 2:
1566
            data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
1567
                      ((((uint32) mem[2]) & 0xff) << 16) |
1568
                      ((((uint32) mem[1]) & 0xff) <<  8) |
1569
                       (((uint32) mem[0]) & 0xff);
1570
            break;
1571
        case 1:
1572
            data[0] = ((((uint32) mem[1]) & 0xff) <<  8) |
1573
                       (((uint32) mem[0]) & 0xff);
1574
            break;
1575
        case 0:
1576
            data[0] = mem[0] & 0xff;
1577
            break;
1578
        }
1579
    }
1580
}
1581
 
1582
 
1583
/* Store data in target byte order.  MEM points to location to store data;
1584
   DATA points to words in host byte order to be stored.  SZ contains log(2)
1585
   of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1586
   2 (one word), or 3 (two words). */
1587
 
1588
static void
1589
store_bytes (mem, data, sz)
1590
    unsigned char  *mem;
1591
    uint32         *data;
1592
    int             sz;
1593
{
1594
    if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
1595
        switch (sz) {
1596
        case 3:
1597
            mem[7] = (data[1] >> 24) & 0xff;
1598
            mem[6] = (data[1] >> 16) & 0xff;
1599
            mem[5] = (data[1] >>  8) & 0xff;
1600
            mem[4] = data[1] & 0xff;
1601
            /* Fall through to 2 */
1602
        case 2:
1603
            mem[3] = (data[0] >> 24) & 0xff;
1604
            mem[2] = (data[0] >> 16) & 0xff;
1605
            /* Fall through to 1 */
1606
        case 1:
1607
            mem[1] = (data[0] >>  8) & 0xff;
1608
            /* Fall through to 0 */
1609
        case 0:
1610
            mem[0] = data[0] & 0xff;
1611
            break;
1612
        }
1613
    } else {
1614
        switch (sz) {
1615
        case 3:
1616
            mem[7] = data[1] & 0xff;
1617
            mem[6] = (data[1] >>  8) & 0xff;
1618
            mem[5] = (data[1] >> 16) & 0xff;
1619
            mem[4] = (data[1] >> 24) & 0xff;
1620
            /* Fall through to 2 */
1621
        case 2:
1622
            mem[3] = data[0] & 0xff;
1623
            mem[2] = (data[0] >>  8) & 0xff;
1624
            mem[1] = (data[0] >> 16) & 0xff;
1625
            mem[0] = (data[0] >> 24) & 0xff;
1626
            break;
1627
        case 1:
1628
            mem[1] = data[0] & 0xff;
1629
            mem[0] = (data[0] >> 8) & 0xff;
1630
            break;
1631
        case 0:
1632
            mem[0] = data[0] & 0xff;
1633
            break;
1634
 
1635
        }
1636
    }
1637
}
1638
 
1639
 
1640
/* Memory emulation */
1641
 
1642
int
1643
memory_read(asi, addr, data, sz, ws)
1644
    int32           asi;
1645
    uint32          addr;
1646
    uint32         *data;
1647
    int32           sz;
1648
    int32          *ws;
1649
{
1650
    int32           mexc;
1651
 
1652
#ifdef ERRINJ
1653
    if (errmec) {
1654
        if (sis_verbose)
1655
            printf("Inserted MEC error %d\n",errmec);
1656
        set_sfsr(errmec, addr, asi, 1);
1657
        if (errmec == 5) mecparerror();
1658
        if (errmec == 6) iucomperr();
1659
        errmec = 0;
1660
        return(1);
1661
    }
1662
#endif;
1663
 
1664
    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1665
        fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
1666
        *ws = mem_ramr_ws;
1667
        return (0);
1668
    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1669
        mexc = mec_read(addr, asi, data);
1670
        if (mexc) {
1671
            set_sfsr(MEC_ACC, addr, asi, 1);
1672
            *ws = MEM_EX_WS;
1673
        } else {
1674
            *ws = 0;
1675
        }
1676
        return (mexc);
1677
 
1678
#ifdef ERA
1679
 
1680
    } else if (era) {
1681
        if ((addr < 0x100000) ||
1682
            ((addr>= 0x80000000) && (addr < 0x80100000))) {
1683
            fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
1684
            *ws = 4;
1685
            return (0);
1686
        } else if ((addr >= 0x10000000) &&
1687
                   (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1688
                   (mec_iocr & 0x10))  {
1689
            *data = erareg;
1690
            return (0);
1691
        }
1692
 
1693
    } else  if (addr < mem_romsz) {
1694
            fetch_bytes (asi, &romb[addr], data, sz);
1695
            *ws = mem_romr_ws;
1696
            return (0);
1697
 
1698
#else
1699
    } else if (addr < mem_romsz) {
1700
        fetch_bytes (asi, &romb[addr], data, sz);
1701
        *ws = mem_romr_ws;
1702
        return (0);
1703
#endif
1704
 
1705
    }
1706
 
1707
    printf("Memory exception at %x (illegal address)\n", addr);
1708
    set_sfsr(UIMP_ACC, addr, asi, 1);
1709
    *ws = MEM_EX_WS;
1710
    return (1);
1711
}
1712
 
1713
int
1714
memory_write(asi, addr, data, sz, ws)
1715
    int32           asi;
1716
    uint32          addr;
1717
    uint32         *data;
1718
    int32           sz;
1719
    int32          *ws;
1720
{
1721
    uint32          byte_addr;
1722
    uint32          byte_mask;
1723
    uint32          waddr;
1724
    uint32         *ram;
1725
    int32           mexc;
1726
    int             i;
1727
    int             wphit[2];
1728
 
1729
#ifdef ERRINJ
1730
    if (errmec) {
1731
        if (sis_verbose)
1732
            printf("Inserted MEC error %d\n",errmec);
1733
        set_sfsr(errmec, addr, asi, 0);
1734
        if (errmec == 5) mecparerror();
1735
        if (errmec == 6) iucomperr();
1736
        errmec = 0;
1737
        return(1);
1738
    }
1739
#endif;
1740
 
1741
    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1742
        if (mem_accprot) {
1743
 
1744
            waddr = (addr & 0x7fffff) >> 2;
1745
            for (i = 0; i < 2; i++)
1746
                wphit[i] =
1747
                    (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1748
                     ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1749
                    ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1750
 
1751
            if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1752
                ((!mem_blockprot) &&
1753
                 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1754
                 )) {
1755
                if (sis_verbose)
1756
                    printf("Memory access protection error at 0x%08x\n", addr);
1757
                set_sfsr(PROT_EXC, addr, asi, 0);
1758
                *ws = MEM_EX_WS;
1759
                return (1);
1760
            }
1761
        }
1762
 
1763
        store_bytes (&ramb[addr & mem_rammask], data, sz);
1764
 
1765
        switch (sz) {
1766
        case 0:
1767
        case 1:
1768
            *ws = mem_ramw_ws + 3;
1769
            break;
1770
        case 2:
1771
            *ws = mem_ramw_ws;
1772
            break;
1773
        case 3:
1774
            *ws = 2 * mem_ramw_ws + STD_WS;
1775
            break;
1776
        }
1777
        return (0);
1778
    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1779
        if ((sz != 2) || (asi != 0xb)) {
1780
            set_sfsr(MEC_ACC, addr, asi, 0);
1781
            *ws = MEM_EX_WS;
1782
            return (1);
1783
        }
1784
        mexc = mec_write(addr, *data);
1785
        if (mexc) {
1786
            set_sfsr(MEC_ACC, addr, asi, 0);
1787
            *ws = MEM_EX_WS;
1788
        } else {
1789
            *ws = 0;
1790
        }
1791
        return (mexc);
1792
 
1793
#ifdef ERA
1794
 
1795
    } else if (era) {
1796
        if ((erareg & 2) &&
1797
        ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1798
            addr &= ROM_MASK;
1799
            *ws = sz == 3 ? 8 : 4;
1800
            store_bytes (&romb[addr], data, sz);
1801
            return (0);
1802
        } else if ((addr >= 0x10000000) &&
1803
                   (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1804
                   (mec_iocr & 0x10))  {
1805
            erareg = *data & 0x0e;
1806
            return (0);
1807
        }
1808
 
1809
    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1810
               (((mec_memcfg & 0x20000) && (sz > 1)) ||
1811
                (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1812
 
1813
        *ws = mem_romw_ws + 1;
1814
        if (sz == 3)
1815
            *ws += mem_romw_ws + STD_WS;
1816
        store_bytes (&romb[addr], data, sz);
1817
        return (0);
1818
 
1819
#else
1820
    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1821
               (((mec_memcfg & 0x20000) && (sz > 1)) ||
1822
                (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1823
 
1824
        *ws = mem_romw_ws + 1;
1825
        if (sz == 3)
1826
            *ws += mem_romw_ws + STD_WS;
1827
        store_bytes (&romb[addr], data, sz);
1828
        return (0);
1829
 
1830
#endif
1831
 
1832
    }
1833
 
1834
    *ws = MEM_EX_WS;
1835
    set_sfsr(UIMP_ACC, addr, asi, 0);
1836
    return (1);
1837
}
1838
 
1839
static unsigned char  *
1840
get_mem_ptr(addr, size)
1841
    uint32          addr;
1842
    uint32          size;
1843
{
1844
    if ((addr + size) < ROM_SZ) {
1845
        return (&romb[addr]);
1846
    } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1847
        return (&ramb[addr & mem_rammask]);
1848
    }
1849
 
1850
#ifdef ERA
1851
      else if ((era) && ((addr <0x100000) ||
1852
        ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1853
        return (&romb[addr & ROM_MASK]);
1854
    }
1855
#endif
1856
 
1857
    return ((char *) -1);
1858
}
1859
 
1860
int
1861
sis_memory_write(addr, data, length)
1862
    uint32          addr;
1863
    char           *data;
1864
    uint32          length;
1865
{
1866
    char           *mem;
1867
 
1868
    if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1869
        return (0);
1870
 
1871
    memcpy(mem, data, length);
1872
    return (length);
1873
}
1874
 
1875
int
1876
sis_memory_read(addr, data, length)
1877
    uint32          addr;
1878
    char           *data;
1879
    uint32          length;
1880
{
1881
    char           *mem;
1882
 
1883
    if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1884
        return (0);
1885
 
1886
    memcpy(data, mem, length);
1887
    return (length);
1888
}

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