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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [erc32/] [float.c] - Blame information for rev 840

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1 24 jeremybenn
/*
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 * This file is part of SIS.
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 *
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 * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
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 * Space Agency
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 *
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 * This program is free software; you can redistribute it and/or modify it under
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 * the terms of the GNU General Public License as published by the Free
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 * Software Foundation; either version 2 of the License, or (at your option)
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 * any later version.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License along with
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 * this program; if not, write to the Free Software Foundation, Inc., 675
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 * Mass Ave, Cambridge, MA 02139, USA.
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 *
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 *
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 * This file implements the interface between the host and the simulated
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 * FPU. IEEE trap handling is done as follows:
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 * 1. In the host, all IEEE traps are masked
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 * 2. After each simulated FPU instruction, check if any exception occured
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 *    by reading the exception bits from the host FPU status register
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 *    (get_accex()).
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 * 3. Propagate any exceptions to the simulated FSR.
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 * 4. Clear host exception bits
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 *
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 *
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 * This can also be done using ieee_flags() library routine on sun.
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 */
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#include "sis.h"
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/* Forward declarations */
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extern uint32   _get_sw PARAMS ((void));
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extern uint32   _get_cw PARAMS ((void));
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static void     __setfpucw PARAMS ((unsigned short fpu_control));
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/* This host dependent routine should return the accrued exceptions */
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int
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get_accex()
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{
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#ifdef sparc
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    return ((_get_fsr_raw() >> 5) & 0x1F);
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#elif i386
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    uint32 accx;
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    accx = _get_sw() & 0x3f;
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    accx = ((accx & 1) << 4) | ((accx & 2) >> 1) | ((accx & 4) >> 1) |
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           (accx & 8) | ((accx & 16) >> 2) | ((accx & 32) >> 5);
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    return(accx);
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#else
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    return(0);
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#warning no fpu trap support for this target
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#endif
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}
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/* How to clear the accrued exceptions */
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void
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clear_accex()
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{
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#ifdef sparc
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    set_fsr((_get_fsr_raw() & ~0x3e0));
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#elif i386
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    asm("\n"
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".text\n"
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"       fnclex\n"
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"\n"
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"    ");
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#else
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#warning no fpu trap support for this target
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#endif
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}
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/* How to map SPARC FSR onto the host */
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void
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set_fsr(fsr)
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uint32 fsr;
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{
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#ifdef sparc
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        _set_fsr_raw(fsr & ~0x0f800000);
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#elif i386
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     void __setfpucw(unsigned short fpu_control);
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     uint32 rawfsr;
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     fsr >>= 30;
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     switch (fsr) {
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        case 0:
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        case 2: break;
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        case 1: fsr = 3;
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        case 3: fsr = 1;
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     }
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     rawfsr = _get_cw();
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     rawfsr |= (fsr << 10) | 0x3ff;
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     __setfpucw(rawfsr);
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#else
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#warning no fpu trap support for this target
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#endif
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}
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/* Host dependent support functions */
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#ifdef sparc
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    asm("\n"
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"\n"
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".text\n"
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"        .align 4\n"
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"        .global __set_fsr_raw,_set_fsr_raw\n"
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"__set_fsr_raw:\n"
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"_set_fsr_raw:\n"
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"        save %sp,-104,%sp\n"
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"        st %i0,[%fp+68]\n"
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"        ld [%fp+68], %fsr\n"
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"        mov 0,%i0\n"
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"        ret\n"
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"        restore\n"
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"\n"
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"        .align 4\n"
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"        .global __get_fsr_raw\n"
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"        .global _get_fsr_raw\n"
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"__get_fsr_raw:\n"
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"_get_fsr_raw:\n"
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"        save %sp,-104,%sp\n"
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"        st %fsr,[%fp+68]\n"
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"        ld [%fp+68], %i0\n"
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"        ret\n"
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"        restore\n"
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"\n"
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"    ");
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#elif i386
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    asm("\n"
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"\n"
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".text\n"
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"        .align 8\n"
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".globl _get_sw,__get_sw\n"
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"__get_sw:\n"
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"_get_sw:\n"
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"        pushl %ebp\n"
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"        movl %esp,%ebp\n"
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"        movl $0,%eax\n"
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"        fnstsw %ax\n"
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"        movl %ebp,%esp\n"
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"        popl %ebp\n"
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"        ret\n"
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"\n"
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"        .align 8\n"
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".globl _get_cw,__get_cw\n"
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"__get_cw:\n"
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"_get_cw:\n"
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"        pushl %ebp\n"
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"        movl %esp,%ebp\n"
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"        subw $2,%esp\n"
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"        fnstcw -2(%ebp)\n"
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"        movw -2(%ebp),%eax\n"
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"        movl %ebp,%esp\n"
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"        popl %ebp\n"
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"        ret\n"
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"\n"
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"\n"
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"    ");
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#else
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#warning no fpu trap support for this target
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#endif
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#if i386
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/* #if defined _WIN32 || defined __GO32__ */
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/* This is so floating exception handling works on NT
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   These definitions are from the linux fpu_control.h, which
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   doesn't exist on NT.
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   default to:
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     - extended precision
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     - rounding to nearest
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     - exceptions on overflow, zero divide and NaN
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*/
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#define _FPU_DEFAULT  0x1372 
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#define _FPU_RESERVED 0xF0C0  /* Reserved bits in cw */
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static void
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__setfpucw(unsigned short fpu_control)
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{
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  volatile unsigned short cw;
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  /* If user supplied _fpu_control, use it ! */
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  if (!fpu_control)
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  {
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    /* use defaults */
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    fpu_control = _FPU_DEFAULT;
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  }
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  /* Get Control Word */
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  __asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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  /* mask in */
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  cw &= _FPU_RESERVED;
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  cw = cw | (fpu_control & ~_FPU_RESERVED);
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  /* set cw */
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  __asm__ volatile ("fldcw %0" :: "m" (cw));
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}
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/* #endif */
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#endif

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