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jeremybenn |
/* frv simulator fr450 dependent profiling code.
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Copyright (C) 2001, 2004, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Red Hat
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define WANT_CPU
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "bfd.h"
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#if WITH_PROFILE_MODEL_P
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#include "profile.h"
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#include "profile-fr400.h"
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int
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frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced)
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{
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return idesc->timing->units[unit_num].done;
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}
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int
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frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk,
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INT out_ICCi_1)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk, out_ICCi_1);
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}
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int
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frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr500. */
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return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk, out_ICCi_1);
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}
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/* icc0-icc4 are the upper 4 fields of the CCR. */
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if (out_ICCi_1 >= 0)
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out_ICCi_1 += 4;
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/* GRk and IACCi_1 have a latency of 1 cycle. */
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cycles = idesc->timing->units[unit_num].done;
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update_GRdouble_latency (cpu, out_GRk, cycles + 1);
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update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
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return cycles;
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}
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int
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frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr500. */
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return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk, out_ICCi_1);
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}
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/* icc0-icc4 are the upper 4 fields of the CCR. */
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if (out_ICCi_1 >= 0)
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out_ICCi_1 += 4;
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/* GRk, ICCi_1 and the divider have a latency of 18 cycles */
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cycles = idesc->timing->units[unit_num].done;
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update_GR_latency (cpu, out_GRk, cycles + 18);
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update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
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update_idiv_resource_latency (cpu, 0, cycles + 18);
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return cycles;
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}
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int
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frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_ICCi_2, INT in_ICCi_3)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
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}
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int
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frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_ICCi_2, INT in_FCCi_2)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
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}
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int
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frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_ICCi_3, INT in_FCCi_3)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
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in_ICCi_3, in_FCCi_3);
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}
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int
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frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT out_GRkhi, INT out_GRklo)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
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out_GRkhi, out_GRklo);
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}
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int
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frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT out_GRk, INT out_GRdoublek)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr500. */
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return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk,
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out_GRdoublek);
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}
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cycles = idesc->timing->units[unit_num].done;
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/* The latency of GRk for a load will depend on how long it takes to retrieve
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the the data from the cache or memory. */
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update_GR_latency_for_load (cpu, out_GRk, cycles);
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update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
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if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
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{
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/* GNER has a latency of 2 cycles. */
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update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
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update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
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}
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return cycles;
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}
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int
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frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_GRk, INT in_GRdoublek)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_GRk, in_GRdoublek);
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}
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int
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frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT out_FRk, INT out_FRdoublek)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_FRk, out_FRdoublek);
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}
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int
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frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj,
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INT in_FRk, INT in_FRdoublek)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, in_FRk, in_FRdoublek);
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}
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int
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frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRi, INT in_GRj, INT out_GRk)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
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in_GRi, in_GRj, out_GRk);
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}
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int
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frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_FRk, INT out_GRj)
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{
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int cycles;
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if (model_insn == FRV_INSN_MODEL_PASS_1)
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{
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/* Pass 1 is the same as for fr400. */
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return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced,
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in_FRk, out_GRj);
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}
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/* The latency of GRj is 1 cycle. */
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cycles = idesc->timing->units[unit_num].done;
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update_GR_latency (cpu, out_GRj, cycles + 1);
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return cycles;
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}
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int
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frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_spr, INT out_GRj)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
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in_spr, out_GRj);
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}
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int
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frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRj, INT out_FRk)
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{
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced,
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in_GRj, out_FRk);
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}
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| 262 |
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int
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frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_GRj, INT out_spr)
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{
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/* Modelling for this unit is the same as for fr500. */
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return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
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in_GRj, out_spr);
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}
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| 272 |
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| 273 |
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int
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| 274 |
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frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
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| 275 |
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int unit_num, int referenced,
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| 276 |
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INT in_FRi, INT in_FRj,
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| 277 |
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INT out_FRk)
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{
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| 279 |
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/* Modelling for this unit is the same as for fr400. */
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return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_FRk);
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| 282 |
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}
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| 283 |
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| 284 |
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int
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| 285 |
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frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
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| 286 |
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int unit_num, int referenced,
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| 287 |
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INT in_FRi, INT in_FRj,
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| 288 |
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INT out_FRk)
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| 289 |
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{
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| 290 |
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/* Modelling for this unit is the same as for fr400. */
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| 291 |
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return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
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in_FRi, in_FRj, out_FRk);
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}
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| 294 |
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| 295 |
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int
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| 296 |
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frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
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| 297 |
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int unit_num, int referenced,
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| 298 |
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INT out_FRkhi, INT out_FRklo)
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| 299 |
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{
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| 300 |
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/* Modelling for this unit is the same as for fr400. */
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| 301 |
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return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced,
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out_FRkhi, out_FRklo);
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| 303 |
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}
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| 304 |
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int
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| 306 |
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frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
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| 307 |
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int unit_num, int referenced,
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| 308 |
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INT in_FRi, INT in_FRj,
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| 309 |
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INT out_ACC40Sk, INT out_ACC40Uk)
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| 310 |
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{
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| 311 |
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/* Modelling for this unit is the same as for fr400. */
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| 312 |
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return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced,
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| 313 |
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in_FRi, in_FRj, out_ACC40Sk,
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| 314 |
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out_ACC40Uk);
|
| 315 |
|
|
}
|
| 316 |
|
|
|
| 317 |
|
|
int
|
| 318 |
|
|
frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
|
| 319 |
|
|
int unit_num, int referenced,
|
| 320 |
|
|
INT in_FRi, INT in_FRj,
|
| 321 |
|
|
INT out_ACC40Sk, INT out_ACC40Uk)
|
| 322 |
|
|
{
|
| 323 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 324 |
|
|
return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced,
|
| 325 |
|
|
in_FRi, in_FRj, out_ACC40Sk,
|
| 326 |
|
|
out_ACC40Uk);
|
| 327 |
|
|
}
|
| 328 |
|
|
|
| 329 |
|
|
int
|
| 330 |
|
|
frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
|
| 331 |
|
|
int unit_num, int referenced,
|
| 332 |
|
|
INT in_ACC40Si, INT out_ACC40Sk)
|
| 333 |
|
|
{
|
| 334 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 335 |
|
|
return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced,
|
| 336 |
|
|
in_ACC40Si, out_ACC40Sk);
|
| 337 |
|
|
}
|
| 338 |
|
|
|
| 339 |
|
|
int
|
| 340 |
|
|
frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
|
| 341 |
|
|
int unit_num, int referenced,
|
| 342 |
|
|
INT in_ACC40Si, INT out_ACC40Sk)
|
| 343 |
|
|
{
|
| 344 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 345 |
|
|
return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num,
|
| 346 |
|
|
referenced, in_ACC40Si,
|
| 347 |
|
|
out_ACC40Sk);
|
| 348 |
|
|
}
|
| 349 |
|
|
|
| 350 |
|
|
int
|
| 351 |
|
|
frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
|
| 352 |
|
|
int unit_num, int referenced,
|
| 353 |
|
|
INT in_ACC40Si, INT out_ACC40Sk)
|
| 354 |
|
|
{
|
| 355 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 356 |
|
|
return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num,
|
| 357 |
|
|
referenced, in_ACC40Si,
|
| 358 |
|
|
out_ACC40Sk);
|
| 359 |
|
|
}
|
| 360 |
|
|
|
| 361 |
|
|
int
|
| 362 |
|
|
frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
|
| 363 |
|
|
int unit_num, int referenced,
|
| 364 |
|
|
INT in_ACC40Si, INT out_ACC40Sk)
|
| 365 |
|
|
{
|
| 366 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 367 |
|
|
return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num,
|
| 368 |
|
|
referenced, in_ACC40Si,
|
| 369 |
|
|
out_ACC40Sk);
|
| 370 |
|
|
}
|
| 371 |
|
|
|
| 372 |
|
|
int
|
| 373 |
|
|
frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
|
| 374 |
|
|
int unit_num, int referenced,
|
| 375 |
|
|
INT in_FRi, INT in_FRj,
|
| 376 |
|
|
INT out_FRk)
|
| 377 |
|
|
{
|
| 378 |
|
|
/* Modelling is the same as media unit 1. */
|
| 379 |
|
|
return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced,
|
| 380 |
|
|
in_FRi, in_FRj, out_FRk);
|
| 381 |
|
|
}
|
| 382 |
|
|
|
| 383 |
|
|
int
|
| 384 |
|
|
frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
|
| 385 |
|
|
int unit_num, int referenced,
|
| 386 |
|
|
INT in_FRi, INT out_FRk)
|
| 387 |
|
|
{
|
| 388 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 389 |
|
|
return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced,
|
| 390 |
|
|
in_FRi, out_FRk);
|
| 391 |
|
|
}
|
| 392 |
|
|
|
| 393 |
|
|
int
|
| 394 |
|
|
frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
|
| 395 |
|
|
int unit_num, int referenced,
|
| 396 |
|
|
INT in_FRi, INT in_FRj,
|
| 397 |
|
|
INT out_FRk)
|
| 398 |
|
|
{
|
| 399 |
|
|
/* Modelling is the same as media unit 1. */
|
| 400 |
|
|
return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced,
|
| 401 |
|
|
in_FRi, in_FRj, out_FRk);
|
| 402 |
|
|
}
|
| 403 |
|
|
|
| 404 |
|
|
int
|
| 405 |
|
|
frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
|
| 406 |
|
|
int unit_num, int referenced,
|
| 407 |
|
|
INT in_ACC40Si, INT in_FRj,
|
| 408 |
|
|
INT out_ACC40Sk, INT out_FRk)
|
| 409 |
|
|
{
|
| 410 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 411 |
|
|
return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
|
| 412 |
|
|
in_ACC40Si, in_FRj,
|
| 413 |
|
|
out_ACC40Sk, out_FRk);
|
| 414 |
|
|
}
|
| 415 |
|
|
|
| 416 |
|
|
int
|
| 417 |
|
|
frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
|
| 418 |
|
|
int unit_num, int referenced,
|
| 419 |
|
|
INT in_ACCGi, INT in_FRinti,
|
| 420 |
|
|
INT out_ACCGk, INT out_FRintk)
|
| 421 |
|
|
{
|
| 422 |
|
|
/* Modelling is the same as media-4 unit except use accumulator guards
|
| 423 |
|
|
as input instead of accumulators. */
|
| 424 |
|
|
return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced,
|
| 425 |
|
|
in_ACCGi, in_FRinti,
|
| 426 |
|
|
out_ACCGk, out_FRintk);
|
| 427 |
|
|
}
|
| 428 |
|
|
|
| 429 |
|
|
int
|
| 430 |
|
|
frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
|
| 431 |
|
|
int unit_num, int referenced,
|
| 432 |
|
|
INT in_ACC40Si, INT out_FRk)
|
| 433 |
|
|
{
|
| 434 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 435 |
|
|
return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num,
|
| 436 |
|
|
referenced, in_ACC40Si,
|
| 437 |
|
|
out_FRk);
|
| 438 |
|
|
}
|
| 439 |
|
|
|
| 440 |
|
|
int
|
| 441 |
|
|
frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
|
| 442 |
|
|
int unit_num, int referenced)
|
| 443 |
|
|
{
|
| 444 |
|
|
int cycles;
|
| 445 |
|
|
int acc;
|
| 446 |
|
|
FRV_PROFILE_STATE *ps;
|
| 447 |
|
|
|
| 448 |
|
|
if (model_insn == FRV_INSN_MODEL_PASS_1)
|
| 449 |
|
|
return 0;
|
| 450 |
|
|
|
| 451 |
|
|
/* The preprocessing can execute right away. */
|
| 452 |
|
|
cycles = idesc->timing->units[unit_num].done;
|
| 453 |
|
|
|
| 454 |
|
|
ps = CPU_PROFILE_STATE (cpu);
|
| 455 |
|
|
|
| 456 |
|
|
/* The post processing must wait for any pending ACC writes. */
|
| 457 |
|
|
ps->post_wait = cycles;
|
| 458 |
|
|
for (acc = 0; acc < 4; acc++)
|
| 459 |
|
|
post_wait_for_ACC (cpu, acc);
|
| 460 |
|
|
for (acc = 8; acc < 12; acc++)
|
| 461 |
|
|
post_wait_for_ACC (cpu, acc);
|
| 462 |
|
|
|
| 463 |
|
|
for (acc = 0; acc < 4; acc++)
|
| 464 |
|
|
{
|
| 465 |
|
|
update_ACC_latency (cpu, acc, ps->post_wait);
|
| 466 |
|
|
update_ACC_ptime (cpu, acc, 2);
|
| 467 |
|
|
}
|
| 468 |
|
|
for (acc = 8; acc < 12; acc++)
|
| 469 |
|
|
{
|
| 470 |
|
|
update_ACC_latency (cpu, acc, ps->post_wait);
|
| 471 |
|
|
update_ACC_ptime (cpu, acc, 2);
|
| 472 |
|
|
}
|
| 473 |
|
|
|
| 474 |
|
|
return cycles;
|
| 475 |
|
|
}
|
| 476 |
|
|
|
| 477 |
|
|
int
|
| 478 |
|
|
frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
|
| 479 |
|
|
int unit_num, int referenced,
|
| 480 |
|
|
INT in_FRi, INT out_FRk)
|
| 481 |
|
|
{
|
| 482 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 483 |
|
|
return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced,
|
| 484 |
|
|
in_FRi, out_FRk);
|
| 485 |
|
|
}
|
| 486 |
|
|
|
| 487 |
|
|
int
|
| 488 |
|
|
frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
|
| 489 |
|
|
int unit_num, int referenced,
|
| 490 |
|
|
INT in_FRinti, INT in_FRintj,
|
| 491 |
|
|
INT out_FCCk)
|
| 492 |
|
|
{
|
| 493 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 494 |
|
|
return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced,
|
| 495 |
|
|
in_FRinti, in_FRintj, out_FCCk);
|
| 496 |
|
|
}
|
| 497 |
|
|
|
| 498 |
|
|
int
|
| 499 |
|
|
frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
|
| 500 |
|
|
int unit_num, int referenced,
|
| 501 |
|
|
INT in_FRi,
|
| 502 |
|
|
INT out_FRk)
|
| 503 |
|
|
{
|
| 504 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 505 |
|
|
return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num,
|
| 506 |
|
|
referenced, in_FRi, out_FRk);
|
| 507 |
|
|
}
|
| 508 |
|
|
|
| 509 |
|
|
int
|
| 510 |
|
|
frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
|
| 511 |
|
|
int unit_num, int referenced,
|
| 512 |
|
|
INT in_FRj,
|
| 513 |
|
|
INT out_FRk)
|
| 514 |
|
|
{
|
| 515 |
|
|
/* Modelling for this unit is the same as for fr400. */
|
| 516 |
|
|
return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num,
|
| 517 |
|
|
referenced, in_FRj, out_FRk);
|
| 518 |
|
|
}
|
| 519 |
|
|
|
| 520 |
|
|
int
|
| 521 |
|
|
frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
|
| 522 |
|
|
int unit_num, int referenced,
|
| 523 |
|
|
INT in_GRi, INT in_GRj)
|
| 524 |
|
|
{
|
| 525 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 526 |
|
|
return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
|
| 527 |
|
|
in_GRi, in_GRj);
|
| 528 |
|
|
}
|
| 529 |
|
|
|
| 530 |
|
|
int
|
| 531 |
|
|
frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
|
| 532 |
|
|
int unit_num, int referenced,
|
| 533 |
|
|
INT in_GRi, INT in_GRj)
|
| 534 |
|
|
{
|
| 535 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 536 |
|
|
return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
|
| 537 |
|
|
in_GRi, in_GRj);
|
| 538 |
|
|
}
|
| 539 |
|
|
|
| 540 |
|
|
int
|
| 541 |
|
|
frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
|
| 542 |
|
|
int unit_num, int referenced,
|
| 543 |
|
|
INT in_GRi, INT in_GRj)
|
| 544 |
|
|
{
|
| 545 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 546 |
|
|
return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
|
| 547 |
|
|
in_GRi, in_GRj);
|
| 548 |
|
|
}
|
| 549 |
|
|
|
| 550 |
|
|
int
|
| 551 |
|
|
frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
|
| 552 |
|
|
int unit_num, int referenced,
|
| 553 |
|
|
INT in_GRi, INT in_GRj)
|
| 554 |
|
|
{
|
| 555 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 556 |
|
|
return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
|
| 557 |
|
|
in_GRi, in_GRj);
|
| 558 |
|
|
}
|
| 559 |
|
|
|
| 560 |
|
|
int
|
| 561 |
|
|
frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
|
| 562 |
|
|
int unit_num, int referenced,
|
| 563 |
|
|
INT in_GRi, INT in_GRj)
|
| 564 |
|
|
{
|
| 565 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 566 |
|
|
return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
|
| 567 |
|
|
in_GRi, in_GRj);
|
| 568 |
|
|
}
|
| 569 |
|
|
|
| 570 |
|
|
int
|
| 571 |
|
|
frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
|
| 572 |
|
|
int unit_num, int referenced,
|
| 573 |
|
|
INT in_GRi, INT in_GRj)
|
| 574 |
|
|
{
|
| 575 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 576 |
|
|
return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
|
| 577 |
|
|
in_GRi, in_GRj);
|
| 578 |
|
|
}
|
| 579 |
|
|
|
| 580 |
|
|
int
|
| 581 |
|
|
frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
|
| 582 |
|
|
int unit_num, int referenced,
|
| 583 |
|
|
INT in_GRi, INT in_GRj)
|
| 584 |
|
|
{
|
| 585 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 586 |
|
|
return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
|
| 587 |
|
|
in_GRi, in_GRj);
|
| 588 |
|
|
}
|
| 589 |
|
|
|
| 590 |
|
|
int
|
| 591 |
|
|
frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
|
| 592 |
|
|
int unit_num, int referenced)
|
| 593 |
|
|
{
|
| 594 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 595 |
|
|
return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
|
| 596 |
|
|
}
|
| 597 |
|
|
|
| 598 |
|
|
int
|
| 599 |
|
|
frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,
|
| 600 |
|
|
int unit_num, int referenced)
|
| 601 |
|
|
{
|
| 602 |
|
|
/* Modelling for this unit is the same as for fr500. */
|
| 603 |
|
|
return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
|
| 604 |
|
|
}
|
| 605 |
|
|
|
| 606 |
|
|
#endif /* WITH_PROFILE_MODEL_P */
|
