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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [frv/] [reset.c] - Blame information for rev 840

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Line No. Rev Author Line
1 24 jeremybenn
/* frv simulator support code
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   Copyright (C) 1999, 2000, 2001, 2003, 2007, 2008
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   Free Software Foundation, Inc.
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   Contributed by Red Hat.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#define WANT_CPU
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "bfd.h"
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/* Initialize the frv simulator.  */
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void
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frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd)
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{
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  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
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  PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
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  FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
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  FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
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  int insn_cache_enabled = CACHE_INITIALIZED (insn_cache);
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  int data_cache_enabled = CACHE_INITIALIZED (data_cache);
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  USI hsr0;
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  /* Initialize the register control information first since some of the
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     register values are used in further configuration.  */
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  frv_register_control_init (current_cpu);
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  /* We need to ensure that the caches are initialized even if they are not
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     initially enabled (via commandline) because they can be enabled by
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     software.  */
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  if (! insn_cache_enabled)
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    frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu));
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  if (! data_cache_enabled)
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    frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu));
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  /* Set the default cpu frequency if it has not been set on the command
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     line.  */
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  if (PROFILE_CPU_FREQ (p) == 0)
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    PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */
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  /* Allocate one cache line of memory containing the address of the reset
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     register Use the largest of the insn cache line size and the data cache
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     line size.  */
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  {
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    int addr = RSTR_ADDRESS;
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    void *aligned_buffer;
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    int bytes;
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    if (CPU_INSN_CACHE (current_cpu)->line_size
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        > CPU_DATA_CACHE (current_cpu)->line_size)
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      bytes = CPU_INSN_CACHE (current_cpu)->line_size;
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    else
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      bytes = CPU_DATA_CACHE (current_cpu)->line_size;
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    /* 'bytes' is a power of 2. Calculate the starting address of the
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       cache line.  */
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    addr &= ~(bytes - 1);
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    aligned_buffer = zalloc (bytes); /* clear */
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    sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes,
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                     0, NULL, aligned_buffer);
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  }
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  PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info;
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  ps->insn_fetch_address = -1;
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  ps->branch_address = -1;
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  cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu),
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                          frvbf_fpu_error);
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  /* Now perform power-on reset.  */
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  frv_power_on_reset (current_cpu);
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  /* Make sure that HSR0.ICE and HSR0.DCE are set properly.  */
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  hsr0 = GET_HSR0 ();
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  if (insn_cache_enabled)
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    SET_HSR0_ICE (hsr0);
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  else
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    CLEAR_HSR0_ICE (hsr0);
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  if (data_cache_enabled)
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    SET_HSR0_DCE (hsr0);
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  else
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    CLEAR_HSR0_DCE (hsr0);
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  SET_HSR0 (hsr0);
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}
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/* Initialize the frv simulator.  */
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void
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frv_term (SIM_DESC sd)
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{
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  /* If the timer is enabled, and model profiling was not originally enabled,
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     then turn it off again.  This is the only place we can currently gain
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     control to do this.  */
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  if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
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    sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0");
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}
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/* Perform a power on reset.  */
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void
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frv_power_on_reset (SIM_CPU *cpu)
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{
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  /* GR, FR and CPR registers are undefined at initialization time.  */
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  frv_initialize_spr (cpu);
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  /* Initialize the RSTR register (in memory).  */
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  if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
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    frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE);
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  else
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    SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE);
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}
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/* Perform a hardware reset.  */
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void
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frv_hardware_reset (SIM_CPU *cpu)
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{
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  /* GR, FR and CPR registers are undefined at hardware reset.  */
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  frv_initialize_spr (cpu);
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  /* Reset the RSTR register (in memory).  */
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  if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
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    frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET);
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  else
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    SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET);
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  /* Reset the insn and data caches.  */
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  frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */);
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  frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */);
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}
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/* Perform a software reset.  */
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void
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frv_software_reset (SIM_CPU *cpu)
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{
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  /* GR, FR and CPR registers are undefined at software reset.  */
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  frv_reset_spr (cpu);
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  /* Reset the RSTR register (in memory).  */
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  if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
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    frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET);
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  else
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    SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET);
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}

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