OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [iq2000/] [arch.h] - Blame information for rev 840

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Simulator header for iq2000.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
This program is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3 of the License, or
12
(at your option) any later version.
13
 
14
This program is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with this program.  If not, see <http://www.gnu.org/licenses/>.
21
 
22
*/
23
 
24
#ifndef IQ2000_ARCH_H
25
#define IQ2000_ARCH_H
26
 
27
#define TARGET_BIG_ENDIAN 1
28
 
29
/* Enum declaration for model types.  */
30
typedef enum model_type {
31
  MODEL_IQ2000, MODEL_MAX
32
} MODEL_TYPE;
33
 
34
#define MAX_MODELS ((int) MODEL_MAX)
35
 
36
/* Enum declaration for unit types.  */
37
typedef enum unit_type {
38
  UNIT_NONE, UNIT_IQ2000_U_EXEC, UNIT_MAX
39
} UNIT_TYPE;
40
 
41
#define MAX_UNITS (1)
42
 
43
#endif /* IQ2000_ARCH_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.