OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [mips/] [tx.igen] - Blame information for rev 827

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
// -*- C -*-
2
//
3
// toshiba specific instructions.
4
//
5
 
6
011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD
7
"madd r, r":RD == 0
8
"madd r, r, r"
9
*r3900
10
{
11
  signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
12
                   + ((signed64) EXTEND32 (GPR[RT])
13
                      * (signed64) EXTEND32 (GPR[RS])));
14
  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
15
  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
16
  LO = EXTEND32 (prod);
17
  HI = EXTEND32 (VH4_8 (prod));
18
  TRACE_ALU_RESULT2 (HI, LO);
19
  if(RD != 0 )
20
    GPR[RD] = LO;
21
}
22
 
23
 
24
011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU
25
"maddu r, r":RD == 0
26
"maddu r, r, r"
27
*r3900
28
{
29
  unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
30
                     + ((unsigned64) VL4_8 (GPR[RS])
31
                        * (unsigned64) VL4_8 (GPR[RT])));
32
  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
33
  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
34
  LO = EXTEND32 (prod);
35
  HI = EXTEND32 (VH4_8 (prod));
36
  TRACE_ALU_RESULT2 (HI, LO);
37
  if(RD != 0)
38
    GPR[RD] = LO;
39
}
40
 
41
000000,CODE.20,001110::CO1:::SDBBP
42
"sdbbp"
43
*r3900:
44
{
45
  SignalException (DebugBreakPoint, instruction);
46
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.