URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-ae-ld2w-i.s] - Blame information for rev 840

Details | Compare with Previous | View Log


.include "t-macros.i"
 
        start
 
        PSW_BITS = 0
        point_dmap_at_imem
        check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w
 
        ldi r10, #0x4000
        ld2w r8, @r10
 
        ldi r10, #0x4001
test_ld2w:
        ld2w r8,@r10
        nop
        exit47

Line No.	Rev	Author	Line
1	24	jeremybenn	`.include "t-macros.i"`
2
3			`start`
4
5			`PSW_BITS = 0`
6			`point_dmap_at_imem`
7			`check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w`
8
9			`ldi r10, #0x4000`
10			`ld2w r8, @r10`
11
12			`ldi r10, #0x4001`
13			`test_ld2w:`
14			`ld2w r8,@r10`
15			`nop`
16			`exit47`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-ae-ld2w-i.s] - Blame information for rev 840