URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-ae-st-id.s] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log


.include "t-macros.i"
 
        start
 
        PSW_BITS = 0
        point_dmap_at_imem
        check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
 
        ldi r10,#0x4001
        st r8, @(1,r10)
test_st:
        st r8,@(2,r10)
        nop
        exit47

Line No.	Rev	Author	Line
1	24	jeremybenn	`.include "t-macros.i"`
2
3			`start`
4
5			`PSW_BITS = 0`
6			`point_dmap_at_imem`
7			`check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st`
8
9			`ldi r10,#0x4001`
10			`st r8, @(1,r10)`
11			`test_st:`
12			`st r8,@(2,r10)`
13			`nop`
14			`exit47`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-ae-st-id.s] - Blame information for rev 856