OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-sp.s] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
.include "t-macros.i"
2
 
3
        start
4
 
5
;;; Read/Write values to SPU/SPI
6
 
7
        loadpsw2 0
8
        ldi sp, 0xdead
9
        loadpsw2 PSW_SM
10
        ldi sp, 0xbeef
11
 
12
        loadpsw2 0
13
        check 1 sp 0xdead
14
        loadpsw2 PSW_SM
15
        check 2 sp 0xbeef
16
 
17
        exit0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.