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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [b.cgs] - Blame information for rev 24

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1 24 jeremybenn
# arm testcase for b$cond $offset24
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# mach: all
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# ??? Still need to test edge cases.
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        .include "testutils.inc"
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        start
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        .global b
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b:
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# b foo
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        b balways1
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        fail
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balways1:
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# beq foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,4
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        cmp r4,r5
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        beq beq1
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        fail
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beq1:
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        mvi_h_gr r5,5
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        cmp r4,r5
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        beq beq2
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        b beq3
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beq2:
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        fail
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beq3:
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# bne foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,5
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        cmp r4,r5
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        bne bne1
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        fail
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bne1:
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        mvi_h_gr r5,4
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        cmp r4,r5
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        bne bne2
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        b bne3
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bne2:
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        fail
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bne3:
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# bcs foo
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        mvi_h_cnvz 1,0,0,0
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        bcs bcs1
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        fail
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bcs1:
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        mvi_h_cnvz 0,0,0,0
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        bcs bcs2
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        b bcs3
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bcs2:
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        fail
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bcs3:
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# bcc foo
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        mvi_h_cnvz 0,0,0,0
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        bcc bcc1
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        fail
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bcc1:
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        mvi_h_cnvz 1,0,0,0
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        bcc bcc2
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        b bcc3
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bcc2:
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        fail
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bcc3:
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# bmi foo
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        mvi_h_cnvz 0,1,0,0
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        bmi bmi1
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        fail
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bmi1:
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        mvi_h_cnvz 0,0,0,0
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        bmi bmi2
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        b bmi3
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bmi2:
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        fail
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bmi3:
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# bpl foo
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        mvi_h_cnvz 0,0,0,0
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        bpl bpl1
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        fail
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bpl1:
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        mvi_h_cnvz 0,1,0,0
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        bpl bpl2
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        b bpl3
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bpl2:
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        fail
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bpl3:
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# bvs foo
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        mvi_h_cnvz 0,0,1,0
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        bvs bvs1
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        fail
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bvs1:
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        mvi_h_cnvz 0,0,0,0
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        bvs bvs2
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        b bvs3
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bvs2:
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        fail
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bvs3:
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# bvc foo
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        mvi_h_cnvz 0,0,0,0
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        bvc bvc1
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        fail
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bvc1:
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        mvi_h_cnvz 0,0,1,0
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        bvc bvc2
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        b bvc3
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bvc2:
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        fail
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bvc3:
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# bhi foo
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        mvi_h_gr r4,5
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        mvi_h_gr r5,4
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        cmp r4,r5
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        bhi bhi1
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        fail
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bhi1:
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        mvi_h_gr r5,5
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        cmp r4,r5
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        bhi bhi2
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        b bhi3
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bhi2:
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        fail
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bhi3:
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        mvi_h_gr r5,6
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        cmp r4,r5
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        bhi bhi4
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        b bhi5
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bhi4:
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        fail
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bhi5:
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# bls foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,5
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        cmp r4,r5
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        bls bls1
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        fail
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bls1:
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        mvi_h_gr r5,4
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        cmp r4,r5
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        bls bls2
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        fail
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bls2:
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        mvi_h_gr r5,3
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        cmp r4,r5
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        bls bls3
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        b bls4
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bls3:
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        fail
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bls4:
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# bge foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,4
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        cmp r4,r5
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        bge bge1
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        fail
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bge1:
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        mvi_h_gr r5,3
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        cmp r4,r5
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        bge bge2
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        fail
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bge2:
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        mvi_h_gr r5,5
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        cmp r4,r5
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        bge bge3
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        b bge4
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bge3:
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        fail
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bge4:
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# blt foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,5
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        cmp r4,r5
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        blt blt1
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        fail
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blt1:
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        mvi_h_gr r5,4
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        cmp r4,r5
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        blt blt2
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        b blt3
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blt2:
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        fail
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blt3:
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        mvi_h_gr r5,3
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        cmp r4,r5
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        blt blt4
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        b blt5
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blt4:
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        fail
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blt5:
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# bgt foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,3
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        cmp r4,r5
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        bgt bgt1
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        fail
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bgt1:
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        mvi_h_gr r5,4
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        cmp r4,r5
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        bgt bgt2
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        b bgt3
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bgt2:
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        fail
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bgt3:
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        mvi_h_gr r5,5
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        cmp r4,r5
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        bgt bgt4
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        b bgt5
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bgt4:
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        fail
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bgt5:
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# ble foo
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        mvi_h_gr r4,4
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        mvi_h_gr r5,4
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        cmp r4,r5
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        ble ble1
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        fail
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ble1:
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        mvi_h_gr r5,5
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        cmp r4,r5
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        ble ble2
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        fail
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ble2:
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        mvi_h_gr r5,3
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        cmp r4,r5
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        ble ble3
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        b ble4
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ble3:
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        fail
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ble4:
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        pass

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