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# arm testcase for b$cond $offset24
# mach: all
 
# ??? Still need to test edge cases.
 
        .include "testutils.inc"
 
        start
 
        .global b
b:
 
# b foo
 
        b balways1
        fail
balways1:
 
# beq foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,4
        cmp r4,r5
        beq beq1
        fail
beq1:
        mvi_h_gr r5,5
        cmp r4,r5
        beq beq2
        b beq3
beq2:
        fail
beq3:
 
# bne foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,5
        cmp r4,r5
        bne bne1
        fail
bne1:
        mvi_h_gr r5,4
        cmp r4,r5
        bne bne2
        b bne3
bne2:
        fail
bne3:
 
# bcs foo
 
        mvi_h_cnvz 1,0,0,0
        bcs bcs1
        fail
bcs1:
        mvi_h_cnvz 0,0,0,0
        bcs bcs2
        b bcs3
bcs2:
        fail
bcs3:
 
# bcc foo
 
        mvi_h_cnvz 0,0,0,0
        bcc bcc1
        fail
bcc1:
        mvi_h_cnvz 1,0,0,0
        bcc bcc2
        b bcc3
bcc2:
        fail
bcc3:
 
# bmi foo
 
        mvi_h_cnvz 0,1,0,0
        bmi bmi1
        fail
bmi1:
        mvi_h_cnvz 0,0,0,0
        bmi bmi2
        b bmi3
bmi2:
        fail
bmi3:
 
# bpl foo
 
        mvi_h_cnvz 0,0,0,0
        bpl bpl1
        fail
bpl1:
        mvi_h_cnvz 0,1,0,0
        bpl bpl2
        b bpl3
bpl2:
        fail
bpl3:
 
# bvs foo
 
        mvi_h_cnvz 0,0,1,0
        bvs bvs1
        fail
bvs1:
        mvi_h_cnvz 0,0,0,0
        bvs bvs2
        b bvs3
bvs2:
        fail
bvs3:
 
# bvc foo
 
        mvi_h_cnvz 0,0,0,0
        bvc bvc1
        fail
bvc1:
        mvi_h_cnvz 0,0,1,0
        bvc bvc2
        b bvc3
bvc2:
        fail
bvc3:
 
# bhi foo
 
        mvi_h_gr r4,5
        mvi_h_gr r5,4
        cmp r4,r5
        bhi bhi1
        fail
bhi1:
        mvi_h_gr r5,5
        cmp r4,r5
        bhi bhi2
        b bhi3
bhi2:
        fail
bhi3:
        mvi_h_gr r5,6
        cmp r4,r5
        bhi bhi4
        b bhi5
bhi4:
        fail
bhi5:
 
# bls foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,5
        cmp r4,r5
        bls bls1
        fail
bls1:
        mvi_h_gr r5,4
        cmp r4,r5
        bls bls2
        fail
bls2:
        mvi_h_gr r5,3
        cmp r4,r5
        bls bls3
        b bls4
bls3:
        fail
bls4:
 
# bge foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,4
        cmp r4,r5
        bge bge1
        fail
bge1:
        mvi_h_gr r5,3
        cmp r4,r5
        bge bge2
        fail
bge2:
        mvi_h_gr r5,5
        cmp r4,r5
        bge bge3
        b bge4
bge3:
        fail
bge4:
 
# blt foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,5
        cmp r4,r5
        blt blt1
        fail
blt1:
        mvi_h_gr r5,4
        cmp r4,r5
        blt blt2
        b blt3
blt2:
        fail
blt3:
        mvi_h_gr r5,3
        cmp r4,r5
        blt blt4
        b blt5
blt4:
        fail
blt5:
 
# bgt foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,3
        cmp r4,r5
        bgt bgt1
        fail
bgt1:
        mvi_h_gr r5,4
        cmp r4,r5
        bgt bgt2
        b bgt3
bgt2:
        fail
bgt3:
        mvi_h_gr r5,5
        cmp r4,r5
        bgt bgt4
        b bgt5
bgt4:
        fail
bgt5:
 
# ble foo
 
        mvi_h_gr r4,4
        mvi_h_gr r5,4
        cmp r4,r5
        ble ble1
        fail
ble1:
        mvi_h_gr r5,5
        cmp r4,r5
        ble ble2
        fail
ble2:
        mvi_h_gr r5,3
        cmp r4,r5
        ble ble3
        b ble4
ble3:
        fail
ble4:
 
        pass

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [b.cgs] - Blame information for rev 24

Line No.	Rev	Author	Line
1	24	jeremybenn	`# arm testcase for b$cond $offset24`
2			`# mach: all`
3
4			`# ??? Still need to test edge cases.`
5
6			`.include "testutils.inc"`
7
8			`start`
9
10			`.global b`
11			`b:`
12
13			`# b foo`
14
15			`b balways1`
16			`fail`
17			`balways1:`
18
19			`# beq foo`
20
21			`mvi_h_gr r4,4`
22			`mvi_h_gr r5,4`
23			`cmp r4,r5`
24			`beq beq1`
25			`fail`
26			`beq1:`
27			`mvi_h_gr r5,5`
28			`cmp r4,r5`
29			`beq beq2`
30			`b beq3`
31			`beq2:`
32			`fail`
33			`beq3:`
34
35			`# bne foo`
36
37			`mvi_h_gr r4,4`
38			`mvi_h_gr r5,5`
39			`cmp r4,r5`
40			`bne bne1`
41			`fail`
42			`bne1:`
43			`mvi_h_gr r5,4`
44			`cmp r4,r5`
45			`bne bne2`
46			`b bne3`
47			`bne2:`
48			`fail`
49			`bne3:`
50
51			`# bcs foo`
52
53			`mvi_h_cnvz 1,0,0,0`
54			`bcs bcs1`
55			`fail`
56			`bcs1:`
57			`mvi_h_cnvz 0,0,0,0`
58			`bcs bcs2`
59			`b bcs3`
60			`bcs2:`
61			`fail`
62			`bcs3:`
63
64			`# bcc foo`
65
66			`mvi_h_cnvz 0,0,0,0`
67			`bcc bcc1`
68			`fail`
69			`bcc1:`
70			`mvi_h_cnvz 1,0,0,0`
71			`bcc bcc2`
72			`b bcc3`
73			`bcc2:`
74			`fail`
75			`bcc3:`
76
77			`# bmi foo`
78
79			`mvi_h_cnvz 0,1,0,0`
80			`bmi bmi1`
81			`fail`
82			`bmi1:`
83			`mvi_h_cnvz 0,0,0,0`
84			`bmi bmi2`
85			`b bmi3`
86			`bmi2:`
87			`fail`
88			`bmi3:`
89
90			`# bpl foo`
91
92			`mvi_h_cnvz 0,0,0,0`
93			`bpl bpl1`
94			`fail`
95			`bpl1:`
96			`mvi_h_cnvz 0,1,0,0`
97			`bpl bpl2`
98			`b bpl3`
99			`bpl2:`
100			`fail`
101			`bpl3:`
102
103			`# bvs foo`
104
105			`mvi_h_cnvz 0,0,1,0`
106			`bvs bvs1`
107			`fail`
108			`bvs1:`
109			`mvi_h_cnvz 0,0,0,0`
110			`bvs bvs2`
111			`b bvs3`
112			`bvs2:`
113			`fail`
114			`bvs3:`
115
116			`# bvc foo`
117
118			`mvi_h_cnvz 0,0,0,0`
119			`bvc bvc1`
120			`fail`
121			`bvc1:`
122			`mvi_h_cnvz 0,0,1,0`
123			`bvc bvc2`
124			`b bvc3`
125			`bvc2:`
126			`fail`
127			`bvc3:`
128
129			`# bhi foo`
130
131			`mvi_h_gr r4,5`
132			`mvi_h_gr r5,4`
133			`cmp r4,r5`
134			`bhi bhi1`
135			`fail`
136			`bhi1:`
137			`mvi_h_gr r5,5`
138			`cmp r4,r5`
139			`bhi bhi2`
140			`b bhi3`
141			`bhi2:`
142			`fail`
143			`bhi3:`
144			`mvi_h_gr r5,6`
145			`cmp r4,r5`
146			`bhi bhi4`
147			`b bhi5`
148			`bhi4:`
149			`fail`
150			`bhi5:`
151
152			`# bls foo`
153
154			`mvi_h_gr r4,4`
155			`mvi_h_gr r5,5`
156			`cmp r4,r5`
157			`bls bls1`
158			`fail`
159			`bls1:`
160			`mvi_h_gr r5,4`
161			`cmp r4,r5`
162			`bls bls2`
163			`fail`
164			`bls2:`
165			`mvi_h_gr r5,3`
166			`cmp r4,r5`
167			`bls bls3`
168			`b bls4`
169			`bls3:`
170			`fail`
171			`bls4:`
172
173			`# bge foo`
174
175			`mvi_h_gr r4,4`
176			`mvi_h_gr r5,4`
177			`cmp r4,r5`
178			`bge bge1`
179			`fail`
180			`bge1:`
181			`mvi_h_gr r5,3`
182			`cmp r4,r5`
183			`bge bge2`
184			`fail`
185			`bge2:`
186			`mvi_h_gr r5,5`
187			`cmp r4,r5`
188			`bge bge3`
189			`b bge4`
190			`bge3:`
191			`fail`
192			`bge4:`
193
194			`# blt foo`
195
196			`mvi_h_gr r4,4`
197			`mvi_h_gr r5,5`
198			`cmp r4,r5`
199			`blt blt1`
200			`fail`
201			`blt1:`
202			`mvi_h_gr r5,4`
203			`cmp r4,r5`
204			`blt blt2`
205			`b blt3`
206			`blt2:`
207			`fail`
208			`blt3:`
209			`mvi_h_gr r5,3`
210			`cmp r4,r5`
211			`blt blt4`
212			`b blt5`
213			`blt4:`
214			`fail`
215			`blt5:`
216
217			`# bgt foo`
218
219			`mvi_h_gr r4,4`
220			`mvi_h_gr r5,3`
221			`cmp r4,r5`
222			`bgt bgt1`
223			`fail`
224			`bgt1:`
225			`mvi_h_gr r5,4`
226			`cmp r4,r5`
227			`bgt bgt2`
228			`b bgt3`
229			`bgt2:`
230			`fail`
231			`bgt3:`
232			`mvi_h_gr r5,5`
233			`cmp r4,r5`
234			`bgt bgt4`
235			`b bgt5`
236			`bgt4:`
237			`fail`
238			`bgt5:`
239
240			`# ble foo`
241
242			`mvi_h_gr r4,4`
243			`mvi_h_gr r5,4`
244			`cmp r4,r5`
245			`ble ble1`
246			`fail`
247			`ble1:`
248			`mvi_h_gr r5,5`
249			`cmp r4,r5`
250			`ble ble2`
251			`fail`
252			`ble2:`
253			`mvi_h_gr r5,3`
254			`cmp r4,r5`
255			`ble ble3`
256			`b ble4`
257			`ble3:`
258			`fail`
259			`ble4:`
260
261			`pass`