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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tinsr.cgs] - Blame information for rev 840

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Line No. Rev Author Line
1 24 jeremybenn
# Intel(r) Wireless MMX(tm) technology testcase for TINSR
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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        .include "testutils.inc"
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        start
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        .global tinsr
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tinsr:
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        # Enable access to CoProcessors 0 & 1 before
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        # we attempt these instructions.
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        mvi_h_gr   r1, 3
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        mcr        p15, 0, r1, cr15, cr1, 0
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        # Test Byte Wide Insertion
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcdef0
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        mvi_h_gr   r2, 0x111111ff
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        tmcrr      wr0, r0, r1
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        tinsrb     wr0, r2, #3
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        tmrrc      r0, r1, wr0
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        test_h_gr  r0, 0xff345678
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        test_h_gr  r1, 0x9abcdef0
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        test_h_gr  r2, 0x111111ff
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        # Test Half Word Wide Insertion
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcdef0
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        mvi_h_gr   r2, 0x111111ff
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        tmcrr      wr0, r0, r1
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        tinsrh     wr0, r2, #2
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        tmrrc      r0, r1, wr0
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abc11ff
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        test_h_gr  r2, 0x111111ff
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        # Test Word Wide Insertion
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcdef0
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        mvi_h_gr   r2, 0x111111ff
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        tmcrr      wr0, r0, r1
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        tinsrw     wr0, r2, #1
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        tmrrc      r0, r1, wr0
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x111111ff
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        test_h_gr  r2, 0x111111ff
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        pass

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