URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [walignr.cgs] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log


# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global walignr
walignr:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test 0 byte align
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r6, 3
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcr       wcgr0, r6
 
        walignr0   wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrc       r6, wcgr0
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0xbcdef012
        test_h_gr  r5, 0x1111119a
        test_h_gr  r6, 3
 
        # Test 1 byte align
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r6, 4
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcr       wcgr1, r6
 
        walignr1   wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrc       r6, wcgr1
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0x9abcdef0
        test_h_gr  r5, 0x11111111
        test_h_gr  r6, 4
 
        # Test 2 byte align
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r6, 2
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcr       wcgr2, r6
 
        walignr2   wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrc       r6, wcgr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0xdef01234
        test_h_gr  r5, 0x11119abc
        test_h_gr  r6, 2
 
        # Test 3 byte align
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r6, 5
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcr       wcgr3, r6
 
        walignr3   wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrc       r6, wcgr3
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0x119abcde
        test_h_gr  r5, 0x00111111
        test_h_gr  r6, 5
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global walignr`
10			`walignr:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test 0 byte align`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcdef0`
21			`mvi_h_gr r2, 0x11111111`
22			`mvi_h_gr r3, 0x00000000`
23			`mvi_h_gr r4, 0`
24			`mvi_h_gr r5, 0`
25			`mvi_h_gr r6, 3`
26
27			`tmcrr wr0, r0, r1`
28			`tmcrr wr1, r2, r3`
29			`tmcrr wr2, r4, r5`
30			`tmcr wcgr0, r6`
31
32			`walignr0 wr2, wr0, wr1`
33
34			`tmrrc r0, r1, wr0`
35			`tmrrc r2, r3, wr1`
36			`tmrrc r4, r5, wr2`
37			`tmrc r6, wcgr0`
38
39			`test_h_gr r0, 0x12345678`
40			`test_h_gr r1, 0x9abcdef0`
41			`test_h_gr r2, 0x11111111`
42			`test_h_gr r3, 0x00000000`
43			`test_h_gr r4, 0xbcdef012`
44			`test_h_gr r5, 0x1111119a`
45			`test_h_gr r6, 3`
46
47			`# Test 1 byte align`
48
49			`mvi_h_gr r0, 0x12345678`
50			`mvi_h_gr r1, 0x9abcdef0`
51			`mvi_h_gr r2, 0x11111111`
52			`mvi_h_gr r3, 0x00000000`
53			`mvi_h_gr r4, 0`
54			`mvi_h_gr r5, 0`
55			`mvi_h_gr r6, 4`
56
57			`tmcrr wr0, r0, r1`
58			`tmcrr wr1, r2, r3`
59			`tmcrr wr2, r4, r5`
60			`tmcr wcgr1, r6`
61
62			`walignr1 wr2, wr0, wr1`
63
64			`tmrrc r0, r1, wr0`
65			`tmrrc r2, r3, wr1`
66			`tmrrc r4, r5, wr2`
67			`tmrc r6, wcgr1`
68
69			`test_h_gr r0, 0x12345678`
70			`test_h_gr r1, 0x9abcdef0`
71			`test_h_gr r2, 0x11111111`
72			`test_h_gr r3, 0x00000000`
73			`test_h_gr r4, 0x9abcdef0`
74			`test_h_gr r5, 0x11111111`
75			`test_h_gr r6, 4`
76
77			`# Test 2 byte align`
78
79			`mvi_h_gr r0, 0x12345678`
80			`mvi_h_gr r1, 0x9abcdef0`
81			`mvi_h_gr r2, 0x11111111`
82			`mvi_h_gr r3, 0x00000000`
83			`mvi_h_gr r4, 0`
84			`mvi_h_gr r5, 0`
85			`mvi_h_gr r6, 2`
86
87			`tmcrr wr0, r0, r1`
88			`tmcrr wr1, r2, r3`
89			`tmcrr wr2, r4, r5`
90			`tmcr wcgr2, r6`
91
92			`walignr2 wr2, wr0, wr1`
93
94			`tmrrc r0, r1, wr0`
95			`tmrrc r2, r3, wr1`
96			`tmrrc r4, r5, wr2`
97			`tmrc r6, wcgr2`
98
99			`test_h_gr r0, 0x12345678`
100			`test_h_gr r1, 0x9abcdef0`
101			`test_h_gr r2, 0x11111111`
102			`test_h_gr r3, 0x00000000`
103			`test_h_gr r4, 0xdef01234`
104			`test_h_gr r5, 0x11119abc`
105			`test_h_gr r6, 2`
106
107			`# Test 3 byte align`
108
109			`mvi_h_gr r0, 0x12345678`
110			`mvi_h_gr r1, 0x9abcdef0`
111			`mvi_h_gr r2, 0x11111111`
112			`mvi_h_gr r3, 0x00000000`
113			`mvi_h_gr r4, 0`
114			`mvi_h_gr r5, 0`
115			`mvi_h_gr r6, 5`
116
117			`tmcrr wr0, r0, r1`
118			`tmcrr wr1, r2, r3`
119			`tmcrr wr2, r4, r5`
120			`tmcr wcgr3, r6`
121
122			`walignr3 wr2, wr0, wr1`
123
124			`tmrrc r0, r1, wr0`
125			`tmrrc r2, r3, wr1`
126			`tmrrc r4, r5, wr2`
127			`tmrc r6, wcgr3`
128
129			`test_h_gr r0, 0x12345678`
130			`test_h_gr r1, 0x9abcdef0`
131			`test_h_gr r2, 0x11111111`
132			`test_h_gr r3, 0x00000000`
133			`test_h_gr r4, 0x119abcde`
134			`test_h_gr r5, 0x00111111`
135			`test_h_gr r6, 5`
136
137			`pass`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [walignr.cgs] - Blame information for rev 24