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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmax.cgs] - Blame information for rev 827

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Line No. Rev Author Line
1 24 jeremybenn
# Intel(r) Wireless MMX(tm) technology testcase for WMAX
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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        .include "testutils.inc"
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        start
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        .global wmax
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wmax:
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        # Enable access to CoProcessors 0 & 1 before
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        # we attempt these instructions.
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        mvi_h_gr   r1, 3
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        mcr        p15, 0, r1, cr15, cr1, 0
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        # Test Unsigned Byte Maximum
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcde00
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        mvi_h_gr   r2, 0x11111111
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        mvi_h_gr   r3, 0x11111111
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        mvi_h_gr   r4, 0
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        mvi_h_gr   r5, 0
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        tmcrr      wr0, r0, r1
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        tmcrr      wr1, r2, r3
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        tmcrr      wr2, r4, r5
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        wmaxub     wr2, wr0, wr1
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        tmrrc      r0, r1, wr0
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        tmrrc      r2, r3, wr1
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        tmrrc      r4, r5, wr2
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abcde00
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        test_h_gr  r2, 0x11111111
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        test_h_gr  r3, 0x11111111
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        test_h_gr  r4, 0x12345678
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        test_h_gr  r5, 0x9abcde11
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        # Test Signed Byte Maximum
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcde00
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        mvi_h_gr   r2, 0x11111111
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        mvi_h_gr   r3, 0x11111111
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        mvi_h_gr   r4, 0
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        mvi_h_gr   r5, 0
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        tmcrr      wr0, r0, r1
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        tmcrr      wr1, r2, r3
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        tmcrr      wr2, r4, r5
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        wmaxsb     wr2, wr0, wr1
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        tmrrc      r0, r1, wr0
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        tmrrc      r2, r3, wr1
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        tmrrc      r4, r5, wr2
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abcde00
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        test_h_gr  r2, 0x11111111
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        test_h_gr  r3, 0x11111111
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        test_h_gr  r4, 0x12345678
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        test_h_gr  r5, 0x11111111
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        # Test Unsigned Halfword Maximum
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcde00
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        mvi_h_gr   r2, 0x11111111
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        mvi_h_gr   r3, 0x11111111
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        mvi_h_gr   r4, 0
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        mvi_h_gr   r5, 0
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        tmcrr      wr0, r0, r1
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        tmcrr      wr1, r2, r3
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        tmcrr      wr2, r4, r5
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        wmaxuh     wr2, wr0, wr1
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        tmrrc      r0, r1, wr0
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        tmrrc      r2, r3, wr1
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        tmrrc      r4, r5, wr2
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abcde00
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        test_h_gr  r2, 0x11111111
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        test_h_gr  r3, 0x11111111
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        test_h_gr  r4, 0x12345678
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        test_h_gr  r5, 0x9abcde00
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        # Test Signed Halfword Maximum
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcde00
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        mvi_h_gr   r2, 0x11111111
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        mvi_h_gr   r3, 0x11111111
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        mvi_h_gr   r4, 0
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        mvi_h_gr   r5, 0
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        tmcrr      wr0, r0, r1
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        tmcrr      wr1, r2, r3
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        tmcrr      wr2, r4, r5
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        wmaxsh     wr2, wr0, wr1
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        tmrrc      r0, r1, wr0
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        tmrrc      r2, r3, wr1
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        tmrrc      r4, r5, wr2
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abcde00
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        test_h_gr  r2, 0x11111111
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        test_h_gr  r3, 0x11111111
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        test_h_gr  r4, 0x12345678
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        test_h_gr  r5, 0x11111111
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        # Test Unsigned Word Maximum
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcde00
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        mvi_h_gr   r2, 0x11111111
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        mvi_h_gr   r3, 0x11111111
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        mvi_h_gr   r4, 0
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        mvi_h_gr   r5, 0
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        tmcrr      wr0, r0, r1
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        tmcrr      wr1, r2, r3
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        tmcrr      wr2, r4, r5
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        wmaxuw     wr2, wr0, wr1
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        tmrrc      r0, r1, wr0
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        tmrrc      r2, r3, wr1
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        tmrrc      r4, r5, wr2
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abcde00
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        test_h_gr  r2, 0x11111111
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        test_h_gr  r3, 0x11111111
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        test_h_gr  r4, 0x12345678
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        test_h_gr  r5, 0x9abcde00
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        # Test Signed Word Maximum
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        mvi_h_gr   r0, 0x12345678
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        mvi_h_gr   r1, 0x9abcde00
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        mvi_h_gr   r2, 0x11111111
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        mvi_h_gr   r3, 0x11111111
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        mvi_h_gr   r4, 0
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        mvi_h_gr   r5, 0
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        tmcrr      wr0, r0, r1
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        tmcrr      wr1, r2, r3
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        tmcrr      wr2, r4, r5
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        wmaxsw     wr2, wr0, wr1
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        tmrrc      r0, r1, wr0
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        tmrrc      r2, r3, wr1
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        tmrrc      r4, r5, wr2
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        test_h_gr  r0, 0x12345678
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        test_h_gr  r1, 0x9abcde00
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        test_h_gr  r2, 0x11111111
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        test_h_gr  r3, 0x11111111
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        test_h_gr  r4, 0x12345678
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        test_h_gr  r5, 0x11111111
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        pass

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