URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmov.cgs] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log


# Intel(r) Wireless MMX(tm) technology testcase for WMOV
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wmov
wmov:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0
        mvi_h_gr   r3, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
 
        wmov       wr1, wr0
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x12345678
        test_h_gr  r3, 0x9abcdef0
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Intel(r) Wireless MMX(tm) technology testcase for WMOV`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wmov`
10			`wmov:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`mvi_h_gr r0, 0x12345678`
18			`mvi_h_gr r1, 0x9abcdef0`
19			`mvi_h_gr r2, 0`
20			`mvi_h_gr r3, 0`
21
22			`tmcrr wr0, r0, r1`
23			`tmcrr wr1, r2, r3`
24
25			`wmov wr1, wr0`
26
27			`tmrrc r0, r1, wr0`
28			`tmrrc r2, r3, wr1`
29
30			`test_h_gr r0, 0x12345678`
31			`test_h_gr r1, 0x9abcdef0`
32			`test_h_gr r2, 0x12345678`
33			`test_h_gr r3, 0x9abcdef0`
34
35			`pass`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmov.cgs] - Blame information for rev 856