URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wsrl.cgs] - Blame information for rev 840

Details | Compare with Previous | View Log


# Intel(r) Wireless MMX(tm) technology testcase for WSRL
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wsrl
wsrl:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Halfword Logical Shift Right
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111104
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsrlh      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111104
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01230567
        test_h_gr  r5, 0x09ab0def
 
        # Test Halfword Logical Shift Right by CG register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111104
        mvi_h_gr   r3, 0
        mvi_h_gr   r4, 0
 
        tmcrr      wr0,   r0, r1
        tmcr       wcgr1, r2
        tmcrr      wr1,   r3, r4
 
        wsrlhg     wr1, wr0, wcgr1
 
        tmrrc      r0, r1, wr0
        tmrc       r2, wcgr1
        tmrrc      r3, r4, wr1
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111104
        test_h_gr  r3, 0x01230567
        test_h_gr  r4, 0x09ab0def
 
        # Test Word Logical Shift Right
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111104
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsrlw      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111104
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x09abcdef
 
        # Test Word Logical Shift Right by CG register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111104
        mvi_h_gr   r3, 0
        mvi_h_gr   r4, 0
 
        tmcrr      wr0,   r0, r1
        tmcr       wcgr2, r2
        tmcrr      wr1,   r3, r4
 
        wsrlwg     wr1, wr0, wcgr2
 
        tmrrc      r0, r1, wr0
        tmrc       r2, wcgr2
        tmrrc      r3, r4, wr1
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111104
        test_h_gr  r3, 0x01234567
        test_h_gr  r4, 0x09abcdef
 
        # Test Double Word Logical Shift Right
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdefc
        mvi_h_gr   r2, 0x11111104
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsrld      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdefc
        test_h_gr  r2, 0x11111104
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0xc1234567
        test_h_gr  r5, 0x09abcdef
 
        # Test Double Word Logical Shift Right by CG register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdefc
        mvi_h_gr   r2, 0x11111104
        mvi_h_gr   r3, 0
        mvi_h_gr   r4, 0
 
        tmcrr      wr0,   r0, r1
        tmcr       wcgr3, r2
        tmcrr      wr1,   r3, r4
 
        wsrldg     wr1, wr0, wcgr3
 
        tmrrc      r0, r1, wr0
        tmrc       r2, wcgr3
        tmrrc      r3, r4, wr1
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdefc
        test_h_gr  r2, 0x11111104
        test_h_gr  r3, 0xc1234567
        test_h_gr  r4, 0x09abcdef
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Intel(r) Wireless MMX(tm) technology testcase for WSRL`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wsrl`
10			`wsrl:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Halfword Logical Shift Right`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcdef0`
21			`mvi_h_gr r2, 0x11111104`
22			`mvi_h_gr r3, 0x11111111`
23			`mvi_h_gr r4, 0`
24			`mvi_h_gr r5, 0`
25
26			`tmcrr wr0, r0, r1`
27			`tmcrr wr1, r2, r3`
28			`tmcrr wr2, r4, r5`
29
30			`wsrlh wr2, wr0, wr1`
31
32			`tmrrc r0, r1, wr0`
33			`tmrrc r2, r3, wr1`
34			`tmrrc r4, r5, wr2`
35
36			`test_h_gr r0, 0x12345678`
37			`test_h_gr r1, 0x9abcdef0`
38			`test_h_gr r2, 0x11111104`
39			`test_h_gr r3, 0x11111111`
40			`test_h_gr r4, 0x01230567`
41			`test_h_gr r5, 0x09ab0def`
42
43			`# Test Halfword Logical Shift Right by CG register`
44
45			`mvi_h_gr r0, 0x12345678`
46			`mvi_h_gr r1, 0x9abcdef0`
47			`mvi_h_gr r2, 0x11111104`
48			`mvi_h_gr r3, 0`
49			`mvi_h_gr r4, 0`
50
51			`tmcrr wr0, r0, r1`
52			`tmcr wcgr1, r2`
53			`tmcrr wr1, r3, r4`
54
55			`wsrlhg wr1, wr0, wcgr1`
56
57			`tmrrc r0, r1, wr0`
58			`tmrc r2, wcgr1`
59			`tmrrc r3, r4, wr1`
60
61			`test_h_gr r0, 0x12345678`
62			`test_h_gr r1, 0x9abcdef0`
63			`test_h_gr r2, 0x11111104`
64			`test_h_gr r3, 0x01230567`
65			`test_h_gr r4, 0x09ab0def`
66
67			`# Test Word Logical Shift Right`
68
69			`mvi_h_gr r0, 0x12345678`
70			`mvi_h_gr r1, 0x9abcdef0`
71			`mvi_h_gr r2, 0x11111104`
72			`mvi_h_gr r3, 0x11111111`
73			`mvi_h_gr r4, 0`
74			`mvi_h_gr r5, 0`
75
76			`tmcrr wr0, r0, r1`
77			`tmcrr wr1, r2, r3`
78			`tmcrr wr2, r4, r5`
79
80			`wsrlw wr2, wr0, wr1`
81
82			`tmrrc r0, r1, wr0`
83			`tmrrc r2, r3, wr1`
84			`tmrrc r4, r5, wr2`
85
86			`test_h_gr r0, 0x12345678`
87			`test_h_gr r1, 0x9abcdef0`
88			`test_h_gr r2, 0x11111104`
89			`test_h_gr r3, 0x11111111`
90			`test_h_gr r4, 0x01234567`
91			`test_h_gr r5, 0x09abcdef`
92
93			`# Test Word Logical Shift Right by CG register`
94
95			`mvi_h_gr r0, 0x12345678`
96			`mvi_h_gr r1, 0x9abcdef0`
97			`mvi_h_gr r2, 0x11111104`
98			`mvi_h_gr r3, 0`
99			`mvi_h_gr r4, 0`
100
101			`tmcrr wr0, r0, r1`
102			`tmcr wcgr2, r2`
103			`tmcrr wr1, r3, r4`
104
105			`wsrlwg wr1, wr0, wcgr2`
106
107			`tmrrc r0, r1, wr0`
108			`tmrc r2, wcgr2`
109			`tmrrc r3, r4, wr1`
110
111			`test_h_gr r0, 0x12345678`
112			`test_h_gr r1, 0x9abcdef0`
113			`test_h_gr r2, 0x11111104`
114			`test_h_gr r3, 0x01234567`
115			`test_h_gr r4, 0x09abcdef`
116
117			`# Test Double Word Logical Shift Right`
118
119			`mvi_h_gr r0, 0x12345678`
120			`mvi_h_gr r1, 0x9abcdefc`
121			`mvi_h_gr r2, 0x11111104`
122			`mvi_h_gr r3, 0x11111111`
123			`mvi_h_gr r4, 0`
124			`mvi_h_gr r5, 0`
125
126			`tmcrr wr0, r0, r1`
127			`tmcrr wr1, r2, r3`
128			`tmcrr wr2, r4, r5`
129
130			`wsrld wr2, wr0, wr1`
131
132			`tmrrc r0, r1, wr0`
133			`tmrrc r2, r3, wr1`
134			`tmrrc r4, r5, wr2`
135
136			`test_h_gr r0, 0x12345678`
137			`test_h_gr r1, 0x9abcdefc`
138			`test_h_gr r2, 0x11111104`
139			`test_h_gr r3, 0x11111111`
140			`test_h_gr r4, 0xc1234567`
141			`test_h_gr r5, 0x09abcdef`
142
143			`# Test Double Word Logical Shift Right by CG register`
144
145			`mvi_h_gr r0, 0x12345678`
146			`mvi_h_gr r1, 0x9abcdefc`
147			`mvi_h_gr r2, 0x11111104`
148			`mvi_h_gr r3, 0`
149			`mvi_h_gr r4, 0`
150
151			`tmcrr wr0, r0, r1`
152			`tmcr wcgr3, r2`
153			`tmcrr wr1, r3, r4`
154
155			`wsrldg wr1, wr0, wcgr3`
156
157			`tmrrc r0, r1, wr0`
158			`tmrc r2, wcgr3`
159			`tmrrc r3, r4, wr1`
160
161			`test_h_gr r0, 0x12345678`
162			`test_h_gr r1, 0x9abcdefc`
163			`test_h_gr r2, 0x11111104`
164			`test_h_gr r3, 0xc1234567`
165			`test_h_gr r4, 0x09abcdef`
166
167			`pass`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wsrl.cgs] - Blame information for rev 840