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# Intel(r) Wireless MMX(tm) technology testcase for WSUB
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wsub
wsub:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Unsaturated Byte subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubb      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abcdef
 
        # Test Unsigned saturated Byte subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubbus    wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abcd00
 
        # Test Signed saturated Byte subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubbss    wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abcdef
 
        # Test Unsaturated Halfword subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubh      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abccef
 
        # Test Unsigned saturated Halfword subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubhus    wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abccef
 
        # Test Signed saturated Halfword subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubhss    wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abccef
 
        # Test Unsaturated Word subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubw      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abccef
 
        # Test Unsigned saturated Word subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubwus    wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abccef
 
        # Test Signed saturated Word subtraction
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcde00
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x11111111
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wsubwss    wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcde00
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x11111111
        test_h_gr  r4, 0x01234567
        test_h_gr  r5, 0x89abccef
 
        pass

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wsub.cgs] - Blame information for rev 816

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Intel(r) Wireless MMX(tm) technology testcase for WSUB`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wsub`
10			`wsub:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Unsaturated Byte subtraction`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcde00`
21			`mvi_h_gr r2, 0x11111111`
22			`mvi_h_gr r3, 0x11111111`
23			`mvi_h_gr r4, 0`
24			`mvi_h_gr r5, 0`
25
26			`tmcrr wr0, r0, r1`
27			`tmcrr wr1, r2, r3`
28			`tmcrr wr2, r4, r5`
29
30			`wsubb wr2, wr0, wr1`
31
32			`tmrrc r0, r1, wr0`
33			`tmrrc r2, r3, wr1`
34			`tmrrc r4, r5, wr2`
35
36			`test_h_gr r0, 0x12345678`
37			`test_h_gr r1, 0x9abcde00`
38			`test_h_gr r2, 0x11111111`
39			`test_h_gr r3, 0x11111111`
40			`test_h_gr r4, 0x01234567`
41			`test_h_gr r5, 0x89abcdef`
42
43			`# Test Unsigned saturated Byte subtraction`
44
45			`mvi_h_gr r0, 0x12345678`
46			`mvi_h_gr r1, 0x9abcde00`
47			`mvi_h_gr r2, 0x11111111`
48			`mvi_h_gr r3, 0x11111111`
49			`mvi_h_gr r4, 0`
50			`mvi_h_gr r5, 0`
51
52			`tmcrr wr0, r0, r1`
53			`tmcrr wr1, r2, r3`
54			`tmcrr wr2, r4, r5`
55
56			`wsubbus wr2, wr0, wr1`
57
58			`tmrrc r0, r1, wr0`
59			`tmrrc r2, r3, wr1`
60			`tmrrc r4, r5, wr2`
61
62			`test_h_gr r0, 0x12345678`
63			`test_h_gr r1, 0x9abcde00`
64			`test_h_gr r2, 0x11111111`
65			`test_h_gr r3, 0x11111111`
66			`test_h_gr r4, 0x01234567`
67			`test_h_gr r5, 0x89abcd00`
68
69			`# Test Signed saturated Byte subtraction`
70
71			`mvi_h_gr r0, 0x12345678`
72			`mvi_h_gr r1, 0x9abcde00`
73			`mvi_h_gr r2, 0x11111111`
74			`mvi_h_gr r3, 0x11111111`
75			`mvi_h_gr r4, 0`
76			`mvi_h_gr r5, 0`
77
78			`tmcrr wr0, r0, r1`
79			`tmcrr wr1, r2, r3`
80			`tmcrr wr2, r4, r5`
81
82			`wsubbss wr2, wr0, wr1`
83
84			`tmrrc r0, r1, wr0`
85			`tmrrc r2, r3, wr1`
86			`tmrrc r4, r5, wr2`
87
88			`test_h_gr r0, 0x12345678`
89			`test_h_gr r1, 0x9abcde00`
90			`test_h_gr r2, 0x11111111`
91			`test_h_gr r3, 0x11111111`
92			`test_h_gr r4, 0x01234567`
93			`test_h_gr r5, 0x89abcdef`
94
95			`# Test Unsaturated Halfword subtraction`
96
97			`mvi_h_gr r0, 0x12345678`
98			`mvi_h_gr r1, 0x9abcde00`
99			`mvi_h_gr r2, 0x11111111`
100			`mvi_h_gr r3, 0x11111111`
101			`mvi_h_gr r4, 0`
102			`mvi_h_gr r5, 0`
103
104			`tmcrr wr0, r0, r1`
105			`tmcrr wr1, r2, r3`
106			`tmcrr wr2, r4, r5`
107
108			`wsubh wr2, wr0, wr1`
109
110			`tmrrc r0, r1, wr0`
111			`tmrrc r2, r3, wr1`
112			`tmrrc r4, r5, wr2`
113
114			`test_h_gr r0, 0x12345678`
115			`test_h_gr r1, 0x9abcde00`
116			`test_h_gr r2, 0x11111111`
117			`test_h_gr r3, 0x11111111`
118			`test_h_gr r4, 0x01234567`
119			`test_h_gr r5, 0x89abccef`
120
121			`# Test Unsigned saturated Halfword subtraction`
122
123			`mvi_h_gr r0, 0x12345678`
124			`mvi_h_gr r1, 0x9abcde00`
125			`mvi_h_gr r2, 0x11111111`
126			`mvi_h_gr r3, 0x11111111`
127			`mvi_h_gr r4, 0`
128			`mvi_h_gr r5, 0`
129
130			`tmcrr wr0, r0, r1`
131			`tmcrr wr1, r2, r3`
132			`tmcrr wr2, r4, r5`
133
134			`wsubhus wr2, wr0, wr1`
135
136			`tmrrc r0, r1, wr0`
137			`tmrrc r2, r3, wr1`
138			`tmrrc r4, r5, wr2`
139
140			`test_h_gr r0, 0x12345678`
141			`test_h_gr r1, 0x9abcde00`
142			`test_h_gr r2, 0x11111111`
143			`test_h_gr r3, 0x11111111`
144			`test_h_gr r4, 0x01234567`
145			`test_h_gr r5, 0x89abccef`
146
147			`# Test Signed saturated Halfword subtraction`
148
149			`mvi_h_gr r0, 0x12345678`
150			`mvi_h_gr r1, 0x9abcde00`
151			`mvi_h_gr r2, 0x11111111`
152			`mvi_h_gr r3, 0x11111111`
153			`mvi_h_gr r4, 0`
154			`mvi_h_gr r5, 0`
155
156			`tmcrr wr0, r0, r1`
157			`tmcrr wr1, r2, r3`
158			`tmcrr wr2, r4, r5`
159
160			`wsubhss wr2, wr0, wr1`
161
162			`tmrrc r0, r1, wr0`
163			`tmrrc r2, r3, wr1`
164			`tmrrc r4, r5, wr2`
165
166			`test_h_gr r0, 0x12345678`
167			`test_h_gr r1, 0x9abcde00`
168			`test_h_gr r2, 0x11111111`
169			`test_h_gr r3, 0x11111111`
170			`test_h_gr r4, 0x01234567`
171			`test_h_gr r5, 0x89abccef`
172
173			`# Test Unsaturated Word subtraction`
174
175			`mvi_h_gr r0, 0x12345678`
176			`mvi_h_gr r1, 0x9abcde00`
177			`mvi_h_gr r2, 0x11111111`
178			`mvi_h_gr r3, 0x11111111`
179			`mvi_h_gr r4, 0`
180			`mvi_h_gr r5, 0`
181
182			`tmcrr wr0, r0, r1`
183			`tmcrr wr1, r2, r3`
184			`tmcrr wr2, r4, r5`
185
186			`wsubw wr2, wr0, wr1`
187
188			`tmrrc r0, r1, wr0`
189			`tmrrc r2, r3, wr1`
190			`tmrrc r4, r5, wr2`
191
192			`test_h_gr r0, 0x12345678`
193			`test_h_gr r1, 0x9abcde00`
194			`test_h_gr r2, 0x11111111`
195			`test_h_gr r3, 0x11111111`
196			`test_h_gr r4, 0x01234567`
197			`test_h_gr r5, 0x89abccef`
198
199			`# Test Unsigned saturated Word subtraction`
200
201			`mvi_h_gr r0, 0x12345678`
202			`mvi_h_gr r1, 0x9abcde00`
203			`mvi_h_gr r2, 0x11111111`
204			`mvi_h_gr r3, 0x11111111`
205			`mvi_h_gr r4, 0`
206			`mvi_h_gr r5, 0`
207
208			`tmcrr wr0, r0, r1`
209			`tmcrr wr1, r2, r3`
210			`tmcrr wr2, r4, r5`
211
212			`wsubwus wr2, wr0, wr1`
213
214			`tmrrc r0, r1, wr0`
215			`tmrrc r2, r3, wr1`
216			`tmrrc r4, r5, wr2`
217
218			`test_h_gr r0, 0x12345678`
219			`test_h_gr r1, 0x9abcde00`
220			`test_h_gr r2, 0x11111111`
221			`test_h_gr r3, 0x11111111`
222			`test_h_gr r4, 0x01234567`
223			`test_h_gr r5, 0x89abccef`
224
225			`# Test Signed saturated Word subtraction`
226
227			`mvi_h_gr r0, 0x12345678`
228			`mvi_h_gr r1, 0x9abcde00`
229			`mvi_h_gr r2, 0x11111111`
230			`mvi_h_gr r3, 0x11111111`
231			`mvi_h_gr r4, 0`
232			`mvi_h_gr r5, 0`
233
234			`tmcrr wr0, r0, r1`
235			`tmcrr wr1, r2, r3`
236			`tmcrr wr2, r4, r5`
237
238			`wsubwss wr2, wr0, wr1`
239
240			`tmrrc r0, r1, wr0`
241			`tmrrc r2, r3, wr1`
242			`tmrrc r4, r5, wr2`
243
244			`test_h_gr r0, 0x12345678`
245			`test_h_gr r1, 0x9abcde00`
246			`test_h_gr r2, 0x11111111`
247			`test_h_gr r3, 0x11111111`
248			`test_h_gr r4, 0x01234567`
249			`test_h_gr r5, 0x89abccef`
250
251			`pass`