OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [movecrt10.ms] - Blame information for rev 840

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
#mach: crisv10
2
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
3
#output: Basic clock cycles, total @: 82\n
4
#output: Memory source stall cycles: 0\n
5
#output: Memory read-after-write stall cycles: 0\n
6
#output: Movem source stall cycles: 0\n
7
#output: Movem destination stall cycles: 0\n
8
#output: Movem address stall cycles: 0\n
9
#output: Multiplication source stall cycles: 0\n
10
#output: Jump source stall cycles: 0\n
11
#output: Branch misprediction stall cycles: 0\n
12
#output: Jump target stall cycles: 0\n
13
#sim: --cris-cycles=basic
14
 .include "movecr.ms"
15
 
16
# This test-case is accidentally the same; gets the same cycle
17
# count as movecrt32.ms, but please keep them separate.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.