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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [movecrt10.ms] - Blame information for rev 856

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Line No. Rev Author Line
1 24 jeremybenn
#mach: crisv10
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#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
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#output: Basic clock cycles, total @: 82\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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 .include "movecr.ms"
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# This test-case is accidentally the same; gets the same cycle
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# count as movecrt32.ms, but please keep them separate.

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