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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [raw10.ms] - Blame information for rev 840

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Line No. Rev Author Line
1 24 jeremybenn
; Checking read-after-write: swrite-then-read 2 cycles.
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#mach: crisv32
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#output: Basic clock cycles, total @: 4\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 2\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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 .include "testutils.inc"
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 startnostack
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 .lcomm x,4
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 .lcomm y,4
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 move.d x,$r0
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 move.d y,$r1
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 clear.d [$r0]
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 move [$r1],$srp
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 break 15

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