OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [x6-v10.ms] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
#mach: crisv10
2
#ld: --section-start=.text=0
3
#sim: --cris-trace=basic
4
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
5
#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
6
#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
7
#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
8
#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
9
#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
10
#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
11
 .include "tmulv10.ms"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.