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# fr30 testcase for addc $Rj,$Ri
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global add
add:
        mvi_h_gr        1,r7
        mvi_h_gr        2,r8
        set_cc          0x0e            ; Make sure carry bit is off
        addc            r7,r8
        test_cc         0 0 0 0
        test_h_gr       3,r8
 
        mvi_h_gr        0x7fffffff,r7
        mvi_h_gr        1,r8
        set_cc          0x04            ; Make sure carry bit is off
        addc            r7,r8
        test_cc         1 0 1 0
        test_h_gr       0x80000000,r8
 
        set_cc          0x08            ; Make sure carry bit is off
        addc            r8,r8
        test_cc         0 1 1 1
        test_h_gr       0,r8
 
        mvi_h_gr        1,r7
        mvi_h_gr        2,r8
        set_cc          0x0f            ; Make sure carry bit is on
        addc            r7,r8
        test_cc         0 0 0 0
        test_h_gr       4,r8
 
        mvi_h_gr        0x7fffffff,r7
        mvi_h_gr        0,r8
        set_cc          0x05            ; Make sure carry bit is on
        addc            r7,r8
        test_cc         1 0 1 0
        test_h_gr       0x80000000,r8
 
        mvi_h_gr        0x7fffffff,r7
        set_cc          0x0b            ; Make sure carry bit is on
        addc            r7,r8
        test_cc         0 1 0 1;
        test_h_gr       0,r8
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# fr30 testcase for addc $Rj,$Ri`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global add`
10			`add:`
11			`mvi_h_gr 1,r7`
12			`mvi_h_gr 2,r8`
13			`set_cc 0x0e ; Make sure carry bit is off`
14			`addc r7,r8`
15			`test_cc 0 0 0 0`
16			`test_h_gr 3,r8`
17
18			`mvi_h_gr 0x7fffffff,r7`
19			`mvi_h_gr 1,r8`
20			`set_cc 0x04 ; Make sure carry bit is off`
21			`addc r7,r8`
22			`test_cc 1 0 1 0`
23			`test_h_gr 0x80000000,r8`
24
25			`set_cc 0x08 ; Make sure carry bit is off`
26			`addc r8,r8`
27			`test_cc 0 1 1 1`
28			`test_h_gr 0,r8`
29
30			`mvi_h_gr 1,r7`
31			`mvi_h_gr 2,r8`
32			`set_cc 0x0f ; Make sure carry bit is on`
33			`addc r7,r8`
34			`test_cc 0 0 0 0`
35			`test_h_gr 4,r8`
36
37			`mvi_h_gr 0x7fffffff,r7`
38			`mvi_h_gr 0,r8`
39			`set_cc 0x05 ; Make sure carry bit is on`
40			`addc r7,r8`
41			`test_cc 1 0 1 0`
42			`test_h_gr 0x80000000,r8`
43
44			`mvi_h_gr 0x7fffffff,r7`
45			`set_cc 0x0b ; Make sure carry bit is on`
46			`addc r7,r8`
47			`test_cc 0 1 0 1;`
48			`test_h_gr 0,r8`
49
50			`pass`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [addc.cgs] - Blame information for rev 856