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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbnolr.cgs] - Blame information for rev 840

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Line No. Rev Author Line
1 24 jeremybenn 
# frv testcase for fcbnolr
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# mach: all
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        .include "testutils.inc"
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        start
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        .global fcbnolr
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fcbnolr:
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        ; ccond is true
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        set_spr_immed   128,lcr
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        set_spr_addr    bad,lr
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        set_fcc         0x0 0
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        fcbnolr
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        set_fcc         0x1 1
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        fcbnolr
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        set_fcc         0x2 2
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        fcbnolr
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        set_fcc         0x3 3
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        fcbnolr
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        set_fcc         0x4 0
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        fcbnolr
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        set_fcc         0x5 1
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        fcbnolr
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        set_fcc         0x6 2
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        fcbnolr
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        set_fcc         0x7 3
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        fcbnolr
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        set_fcc         0x8 0
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        fcbnolr
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        set_fcc         0x9 1
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        fcbnolr
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        set_fcc         0xa 2
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        fcbnolr
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        set_fcc         0xb 3
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        fcbnolr
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        set_fcc         0xc 0
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        fcbnolr
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        set_fcc         0xd 1
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        fcbnolr
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        set_fcc         0xe 2
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        fcbnolr
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        set_fcc         0xf 3
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        fcbnolr
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        ; ccond is true
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        set_spr_immed   1,lcr
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        set_fcc         0x0 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x1 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x2 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x3 3
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x4 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x5 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x6 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x7 3
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x8 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x9 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xa 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xb 3
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xc 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xd 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xe 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xf 3
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        fcbnolr
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        ; ccond is false
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        set_spr_immed   128,lcr
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        set_fcc         0x0 0
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        fcbnolr
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        set_fcc         0x1 1
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        fcbnolr
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        set_fcc         0x2 2
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        fcbnolr
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        set_fcc         0x3 3
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        fcbnolr
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        set_fcc         0x4 0
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        fcbnolr
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        set_fcc         0x5 1
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        fcbnolr
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        set_fcc         0x6 2
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        fcbnolr
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        set_fcc         0x7 3
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        fcbnolr
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        set_fcc         0x8 0
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        fcbnolr
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        set_fcc         0x9 1
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        fcbnolr
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        set_fcc         0xa 2
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        fcbnolr
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        set_fcc         0xb 3
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        fcbnolr
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        set_fcc         0xc 0
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        fcbnolr
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        set_fcc         0xd 1
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        fcbnolr
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        set_fcc         0xe 2
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        fcbnolr
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        set_fcc         0xf 3
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        fcbnolr
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        ; ccond is false
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        set_spr_immed   1,lcr
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        set_fcc         0x0 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x1 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x2 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x3 3
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x4 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x5 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x6 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x7 3
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x8 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0x9 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xa 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xb 3
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xc 0
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xd 1
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xe 2
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        fcbnolr
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        set_spr_immed   1,lcr
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        set_fcc         0xf 3
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        fcbnolr
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        pass
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bad:
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        fail

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