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jeremybenn |
# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
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# mach: frv fr500
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.include "../testutils.inc"
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start
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.global msubhss
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msubhss:
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set_spr_immed 0x1b1b,cccr
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12 |
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0xdead,0x0000,fr11
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14 |
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set_fr_iimmed 0x0000,0x0000,fr12
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15 |
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set_fr_iimmed 0x0000,0xbeef,fr13
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cmqsubhss fr10,fr12,fr14,cc0,1
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test_fr_limmed 0x0000,0x0000,fr14
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test_fr_limmed 0xdead,0x4111,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0x1234,0x5678,fr11
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set_fr_iimmed 0xbeef,0x0000,fr12
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set_fr_iimmed 0x1111,0x1111,fr13
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cmqsubhss fr10,fr12,fr14,cc0,1
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test_fr_limmed 0x4111,0xdead,fr14
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test_fr_limmed 0x0123,0x4567,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x7ffe,0x7ffe,fr11
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set_fr_iimmed 0xffff,0xffff,fr12
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set_fr_iimmed 0xfffe,0xffff,fr13
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cmqsubhss fr10,fr12,fr14,cc0,1
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test_fr_limmed 0x1235,0x5679,fr14
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test_fr_limmed 0x7fff,0x7fff,fr15
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test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0x8001,0x8001,fr11
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set_fr_iimmed 0x0001,0x0002,fr12
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set_fr_iimmed 0x0002,0x0001,fr13
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cmqsubhss fr10,fr12,fr14,cc4,1
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test_fr_limmed 0x8000,0x8000,fr14
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test_fr_limmed 0x8000,0x8000,fr15
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test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0xffff,0xffff,fr11
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set_fr_iimmed 0x8000,0x8000,fr12
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set_fr_iimmed 0x8000,0x8000,fr13
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cmqsubhss.p fr10,fr10,fr14,cc4,1
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cmqsubhss fr12,fr10,fr16,cc4,1
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test_fr_limmed 0x0000,0x0000,fr14
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test_fr_limmed 0x0000,0x0000,fr15
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test_fr_limmed 0x8000,0x8000,fr16
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test_fr_limmed 0x8001,0x8001,fr17
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set
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test_spr_bits 2,1,1,msr1 ; msr1.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0xdead,0x0000,fr11
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set_fr_iimmed 0x0000,0x0000,fr12
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set_fr_iimmed 0x0000,0xbeef,fr13
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cmqsubhss fr10,fr12,fr14,cc1,0
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test_fr_limmed 0x0000,0x0000,fr14
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test_fr_limmed 0xdead,0x4111,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0x1234,0x5678,fr11
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set_fr_iimmed 0xbeef,0x0000,fr12
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set_fr_iimmed 0x1111,0x1111,fr13
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cmqsubhss fr10,fr12,fr14,cc1,0
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test_fr_limmed 0x4111,0xdead,fr14
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test_fr_limmed 0x0123,0x4567,fr15
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x7ffe,0x7ffe,fr11
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110 |
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set_fr_iimmed 0xffff,0xffff,fr12
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set_fr_iimmed 0xfffe,0xffff,fr13
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cmqsubhss fr10,fr12,fr14,cc1,0
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test_fr_limmed 0x1235,0x5679,fr14
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test_fr_limmed 0x7fff,0x7fff,fr15
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test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0x8001,0x8001,fr11
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set_fr_iimmed 0x0001,0x0002,fr12
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set_fr_iimmed 0x0002,0x0001,fr13
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cmqsubhss fr10,fr12,fr14,cc5,0
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test_fr_limmed 0x8000,0x8000,fr14
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test_fr_limmed 0x8000,0x8000,fr15
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test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0xffff,0xffff,fr11
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set_fr_iimmed 0x8000,0x8000,fr12
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set_fr_iimmed 0x8000,0x8000,fr13
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cmqsubhss.p fr10,fr10,fr14,cc5,0
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cmqsubhss fr12,fr10,fr16,cc5,0
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test_fr_limmed 0x0000,0x0000,fr14
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test_fr_limmed 0x0000,0x0000,fr15
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test_fr_limmed 0x8000,0x8000,fr16
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test_fr_limmed 0x8001,0x8001,fr17
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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146 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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147 |
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test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set
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test_spr_bits 2,1,1,msr1 ; msr1.ovf set
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149 |
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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150 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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151 |
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set_fr_iimmed 0x1111,0x1111,fr14
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153 |
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set_fr_iimmed 0x2222,0x2222,fr15
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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156 |
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set_fr_iimmed 0x0000,0x0000,fr10
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157 |
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set_fr_iimmed 0xdead,0x0000,fr11
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158 |
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set_fr_iimmed 0x0000,0x0000,fr12
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159 |
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set_fr_iimmed 0x0000,0xbeef,fr13
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160 |
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cmqsubhss fr10,fr12,fr14,cc0,0
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161 |
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test_fr_limmed 0x1111,0x1111,fr14
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162 |
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test_fr_limmed 0x2222,0x2222,fr15
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163 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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164 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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165 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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166 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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167 |
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0x1234,0x5678,fr11
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170 |
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set_fr_iimmed 0xbeef,0x0000,fr12
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171 |
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set_fr_iimmed 0x1111,0x1111,fr13
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172 |
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cmqsubhss fr10,fr12,fr14,cc0,0
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173 |
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test_fr_limmed 0x1111,0x1111,fr14
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174 |
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test_fr_limmed 0x2222,0x2222,fr15
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175 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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176 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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177 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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178 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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179 |
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180 |
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set_spr_immed 0,msr0
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set_fr_iimmed 0x1234,0x5678,fr10
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182 |
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set_fr_iimmed 0x7ffe,0x7ffe,fr11
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183 |
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set_fr_iimmed 0xffff,0xffff,fr12
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184 |
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set_fr_iimmed 0xfffe,0xffff,fr13
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185 |
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cmqsubhss fr10,fr12,fr14,cc0,0
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186 |
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test_fr_limmed 0x1111,0x1111,fr14
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187 |
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test_fr_limmed 0x2222,0x2222,fr15
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188 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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189 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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190 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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191 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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192 |
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193 |
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set_spr_immed 0,msr0
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194 |
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set_fr_iimmed 0x8001,0x8001,fr10
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195 |
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set_fr_iimmed 0x8001,0x8001,fr11
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196 |
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set_fr_iimmed 0x0001,0x0002,fr12
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197 |
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set_fr_iimmed 0x0002,0x0001,fr13
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198 |
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cmqsubhss fr10,fr12,fr14,cc4,0
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199 |
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test_fr_limmed 0x1111,0x1111,fr14
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200 |
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test_fr_limmed 0x2222,0x2222,fr15
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201 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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202 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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203 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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204 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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205 |
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206 |
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set_fr_iimmed 0x3333,0x3333,fr16
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207 |
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set_fr_iimmed 0x4444,0x4444,fr17
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208 |
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set_spr_immed 0,msr0
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209 |
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set_spr_immed 0,msr1
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210 |
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set_fr_iimmed 0x0001,0x0001,fr10
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211 |
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set_fr_iimmed 0xffff,0xffff,fr11
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212 |
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set_fr_iimmed 0x8000,0x8000,fr12
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213 |
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set_fr_iimmed 0x8000,0x8000,fr13
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214 |
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cmqsubhss.p fr10,fr10,fr14,cc4,0
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215 |
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cmqsubhss fr12,fr10,fr16,cc4,0
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216 |
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test_fr_limmed 0x1111,0x1111,fr14
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217 |
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test_fr_limmed 0x2222,0x2222,fr15
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218 |
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test_fr_limmed 0x3333,0x3333,fr16
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219 |
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test_fr_limmed 0x4444,0x4444,fr17
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220 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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221 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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222 |
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test_spr_bits 2,1,0,msr1 ; msr1.ovf not set
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223 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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224 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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225 |
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226 |
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set_fr_iimmed 0x1111,0x1111,fr14
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227 |
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set_fr_iimmed 0x2222,0x2222,fr15
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228 |
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set_spr_immed 0,msr0
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229 |
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set_spr_immed 0,msr1
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230 |
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set_fr_iimmed 0x0000,0x0000,fr10
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231 |
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set_fr_iimmed 0xdead,0x0000,fr11
|
232 |
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set_fr_iimmed 0x0000,0x0000,fr12
|
233 |
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set_fr_iimmed 0x0000,0xbeef,fr13
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234 |
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cmqsubhss fr10,fr12,fr14,cc1,1
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235 |
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test_fr_limmed 0x1111,0x1111,fr14
|
236 |
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test_fr_limmed 0x2222,0x2222,fr15
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237 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
238 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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239 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
240 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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241 |
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242 |
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set_fr_iimmed 0x0000,0xdead,fr10
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243 |
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set_fr_iimmed 0x1234,0x5678,fr11
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244 |
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set_fr_iimmed 0xbeef,0x0000,fr12
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245 |
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set_fr_iimmed 0x1111,0x1111,fr13
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246 |
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cmqsubhss fr10,fr12,fr14,cc1,1
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247 |
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test_fr_limmed 0x1111,0x1111,fr14
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248 |
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test_fr_limmed 0x2222,0x2222,fr15
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249 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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250 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
251 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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252 |
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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253 |
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|
254 |
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set_spr_immed 0,msr0
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255 |
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set_fr_iimmed 0x1234,0x5678,fr10
|
256 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr11
|
257 |
|
|
set_fr_iimmed 0xffff,0xffff,fr12
|
258 |
|
|
set_fr_iimmed 0xfffe,0xffff,fr13
|
259 |
|
|
cmqsubhss fr10,fr12,fr14,cc1,1
|
260 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
261 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
262 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
263 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
264 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
265 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
266 |
|
|
|
267 |
|
|
set_spr_immed 0,msr0
|
268 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
269 |
|
|
set_fr_iimmed 0x8001,0x8001,fr11
|
270 |
|
|
set_fr_iimmed 0x0001,0x0002,fr12
|
271 |
|
|
set_fr_iimmed 0x0002,0x0001,fr13
|
272 |
|
|
cmqsubhss fr10,fr12,fr14,cc5,1
|
273 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
274 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
275 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
276 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
277 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
278 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
279 |
|
|
|
280 |
|
|
set_fr_iimmed 0x3333,0x3333,fr16
|
281 |
|
|
set_fr_iimmed 0x4444,0x4444,fr17
|
282 |
|
|
set_spr_immed 0,msr0
|
283 |
|
|
set_spr_immed 0,msr1
|
284 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
285 |
|
|
set_fr_iimmed 0xffff,0xffff,fr11
|
286 |
|
|
set_fr_iimmed 0x8000,0x8000,fr12
|
287 |
|
|
set_fr_iimmed 0x8000,0x8000,fr13
|
288 |
|
|
cmqsubhss.p fr10,fr10,fr14,cc5,1
|
289 |
|
|
cmqsubhss fr12,fr10,fr16,cc5,1
|
290 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
291 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
292 |
|
|
test_fr_limmed 0x3333,0x3333,fr16
|
293 |
|
|
test_fr_limmed 0x4444,0x4444,fr17
|
294 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
295 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
296 |
|
|
test_spr_bits 2,1,0,msr1 ; msr1.ovf not set
|
297 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
298 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
299 |
|
|
|
300 |
|
|
set_fr_iimmed 0x1111,0x1111,fr14
|
301 |
|
|
set_fr_iimmed 0x2222,0x2222,fr15
|
302 |
|
|
set_spr_immed 0,msr0
|
303 |
|
|
set_spr_immed 0,msr1
|
304 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
305 |
|
|
set_fr_iimmed 0xdead,0x0000,fr11
|
306 |
|
|
set_fr_iimmed 0x0000,0x0000,fr12
|
307 |
|
|
set_fr_iimmed 0x0000,0xbeef,fr13
|
308 |
|
|
cmqsubhss fr10,fr12,fr14,cc2,1
|
309 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
310 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
311 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
312 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
313 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
314 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
315 |
|
|
|
316 |
|
|
set_fr_iimmed 0x0000,0xdead,fr10
|
317 |
|
|
set_fr_iimmed 0x1234,0x5678,fr11
|
318 |
|
|
set_fr_iimmed 0xbeef,0x0000,fr12
|
319 |
|
|
set_fr_iimmed 0x1111,0x1111,fr13
|
320 |
|
|
cmqsubhss fr10,fr12,fr14,cc2,0
|
321 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
322 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
323 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
324 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
325 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
326 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
327 |
|
|
|
328 |
|
|
set_spr_immed 0,msr0
|
329 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
330 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr11
|
331 |
|
|
set_fr_iimmed 0xffff,0xffff,fr12
|
332 |
|
|
set_fr_iimmed 0xfffe,0xffff,fr13
|
333 |
|
|
cmqsubhss fr10,fr12,fr14,cc2,1
|
334 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
335 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
336 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
337 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
338 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
339 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
340 |
|
|
|
341 |
|
|
set_spr_immed 0,msr0
|
342 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
343 |
|
|
set_fr_iimmed 0x8001,0x8001,fr11
|
344 |
|
|
set_fr_iimmed 0x0001,0x0002,fr12
|
345 |
|
|
set_fr_iimmed 0x0002,0x0001,fr13
|
346 |
|
|
cmqsubhss fr10,fr12,fr14,cc6,0
|
347 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
348 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
349 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
350 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
351 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
352 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
353 |
|
|
|
354 |
|
|
set_fr_iimmed 0x3333,0x3333,fr16
|
355 |
|
|
set_fr_iimmed 0x4444,0x4444,fr17
|
356 |
|
|
set_spr_immed 0,msr0
|
357 |
|
|
set_spr_immed 0,msr1
|
358 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
359 |
|
|
set_fr_iimmed 0xffff,0xffff,fr11
|
360 |
|
|
set_fr_iimmed 0x8000,0x8000,fr12
|
361 |
|
|
set_fr_iimmed 0x8000,0x8000,fr13
|
362 |
|
|
cmqsubhss.p fr10,fr10,fr14,cc6,1
|
363 |
|
|
cmqsubhss fr12,fr10,fr16,cc6,0
|
364 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
365 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
366 |
|
|
test_fr_limmed 0x3333,0x3333,fr16
|
367 |
|
|
test_fr_limmed 0x4444,0x4444,fr17
|
368 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
369 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
370 |
|
|
test_spr_bits 2,1,0,msr1 ; msr1.ovf not set
|
371 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
372 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
373 |
|
|
|
374 |
|
|
set_fr_iimmed 0x1111,0x1111,fr14
|
375 |
|
|
set_fr_iimmed 0x2222,0x2222,fr15
|
376 |
|
|
set_spr_immed 0,msr0
|
377 |
|
|
set_spr_immed 0,msr1
|
378 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
379 |
|
|
set_fr_iimmed 0xdead,0x0000,fr11
|
380 |
|
|
set_fr_iimmed 0x0000,0x0000,fr12
|
381 |
|
|
set_fr_iimmed 0x0000,0xbeef,fr13
|
382 |
|
|
cmqsubhss fr10,fr12,fr14,cc3,1
|
383 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
384 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
385 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
386 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
387 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
388 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
389 |
|
|
|
390 |
|
|
set_fr_iimmed 0x0000,0xdead,fr10
|
391 |
|
|
set_fr_iimmed 0x1234,0x5678,fr11
|
392 |
|
|
set_fr_iimmed 0xbeef,0x0000,fr12
|
393 |
|
|
set_fr_iimmed 0x1111,0x1111,fr13
|
394 |
|
|
cmqsubhss fr10,fr12,fr14,cc3,0
|
395 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
396 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
397 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
398 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
399 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
400 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
401 |
|
|
|
402 |
|
|
set_spr_immed 0,msr0
|
403 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
404 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr11
|
405 |
|
|
set_fr_iimmed 0xffff,0xffff,fr12
|
406 |
|
|
set_fr_iimmed 0xfffe,0xffff,fr13
|
407 |
|
|
cmqsubhss fr10,fr12,fr14,cc3,1
|
408 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
409 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
410 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
411 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
412 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
413 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
414 |
|
|
|
415 |
|
|
set_spr_immed 0,msr0
|
416 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
417 |
|
|
set_fr_iimmed 0x8001,0x8001,fr11
|
418 |
|
|
set_fr_iimmed 0x0001,0x0002,fr12
|
419 |
|
|
set_fr_iimmed 0x0002,0x0001,fr13
|
420 |
|
|
cmqsubhss fr10,fr12,fr14,cc7,0
|
421 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
422 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
423 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
424 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
425 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
426 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
427 |
|
|
|
428 |
|
|
set_fr_iimmed 0x3333,0x3333,fr16
|
429 |
|
|
set_fr_iimmed 0x4444,0x4444,fr17
|
430 |
|
|
set_spr_immed 0,msr0
|
431 |
|
|
set_spr_immed 0,msr1
|
432 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
433 |
|
|
set_fr_iimmed 0xffff,0xffff,fr11
|
434 |
|
|
set_fr_iimmed 0x8000,0x8000,fr12
|
435 |
|
|
set_fr_iimmed 0x8000,0x8000,fr13
|
436 |
|
|
cmqsubhss.p fr10,fr10,fr14,cc7,1
|
437 |
|
|
cmqsubhss fr12,fr10,fr16,cc7,0
|
438 |
|
|
test_fr_limmed 0x1111,0x1111,fr14
|
439 |
|
|
test_fr_limmed 0x2222,0x2222,fr15
|
440 |
|
|
test_fr_limmed 0x3333,0x3333,fr16
|
441 |
|
|
test_fr_limmed 0x4444,0x4444,fr17
|
442 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
443 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
444 |
|
|
test_spr_bits 2,1,0,msr1 ; msr1.ovf not set
|
445 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
446 |
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
447 |
|
|
|
448 |
|
|
pass
|