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jeremybenn |
# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond
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# mach: all
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.include "../testutils.inc"
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start
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.global maddhss
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maddhss:
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set_spr_immed 0x1b1b,cccr
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmaddhss fr10,fr11,fr12,cc0,1
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0xdead,0x0000,fr10
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set_fr_iimmed 0x0000,0xbeef,fr11
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cmaddhss fr10,fr11,fr12,cc0,1
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test_fr_limmed 0xdead,0xbeef,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0xbeef,0x0000,fr11
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cmaddhss fr10,fr11,fr12,cc0,1
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test_fr_limmed 0xbeef,0xdead,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x1111,0x1111,fr11
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cmaddhss fr10,fr11,fr12,cc0,1
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test_fr_limmed 0x2345,0x6789,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0xffff,0xffff,fr11
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cmaddhss fr10,fr11,fr12,cc0,1
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test_fr_limmed 0x1233,0x5677,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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cmaddhss fr10,fr11,fr12,cc4,1
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test_fr_limmed 0x7fff,0x7fff,fr12
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0xffff,0xfffe,fr11
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cmaddhss fr10,fr11,fr12,cc4,1
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test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
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test_fr_limmed 0x8000,0x8000,fr12
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0xfffe,0xfffe,fr11
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cmaddhss fr10,fr11,fr12,cc4,1
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test_fr_limmed 0x8000,0x8000,fr12
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x7fff,0x7fff,fr11
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cmaddhss.p fr10,fr10,fr12,cc4,1
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cmaddhss fr11,fr11,fr13,cc4,1
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test_fr_limmed 0x0002,0x0002,fr12
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test_fr_limmed 0x7fff,0x7fff,fr13
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmaddhss fr10,fr11,fr12,cc1,0
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0xdead,0x0000,fr10
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set_fr_iimmed 0x0000,0xbeef,fr11
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cmaddhss fr10,fr11,fr12,cc1,0
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test_fr_limmed 0xdead,0xbeef,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0xbeef,0x0000,fr11
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cmaddhss fr10,fr11,fr12,cc1,0
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test_fr_limmed 0xbeef,0xdead,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x1111,0x1111,fr11
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cmaddhss fr10,fr11,fr12,cc1,0
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test_fr_limmed 0x2345,0x6789,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0xffff,0xffff,fr11
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cmaddhss fr10,fr11,fr12,cc1,0
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test_fr_limmed 0x1233,0x5677,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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cmaddhss fr10,fr11,fr12,cc5,0
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test_fr_limmed 0x7fff,0x7fff,fr12
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0xffff,0xfffe,fr11
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cmaddhss fr10,fr11,fr12,cc5,0
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test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
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test_fr_limmed 0x8000,0x8000,fr12
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0xfffe,0xfffe,fr11
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cmaddhss fr10,fr11,fr12,cc5,0
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test_fr_limmed 0x8000,0x8000,fr12
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x7fff,0x7fff,fr11
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cmaddhss.p fr10,fr10,fr12,cc5,0
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cmaddhss fr11,fr11,fr13,cc5,0
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test_fr_limmed 0x0002,0x0002,fr12
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test_fr_limmed 0x7fff,0x7fff,fr13
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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185 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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186 |
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set_fr_iimmed 0xdead,0xbeef,fr12
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmaddhss fr10,fr11,fr12,cc0,0
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test_fr_limmed 0xdead,0xbeef,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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194 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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195 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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196 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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197 |
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set_fr_iimmed 0xdead,0x0000,fr10
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set_fr_iimmed 0x0000,0xbeef,fr11
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200 |
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cmaddhss fr10,fr11,fr12,cc0,0
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201 |
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test_fr_limmed 0xdead,0xbeef,fr12
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202 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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203 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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204 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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205 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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206 |
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207 |
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set_fr_iimmed 0x0000,0xdead,fr10
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208 |
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set_fr_iimmed 0xbeef,0x0000,fr11
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209 |
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cmaddhss fr10,fr11,fr12,cc0,0
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210 |
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test_fr_limmed 0xdead,0xbeef,fr12
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211 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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212 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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213 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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214 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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215 |
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216 |
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set_fr_iimmed 0x1234,0x5678,fr10
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217 |
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set_fr_iimmed 0x1111,0x1111,fr11
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218 |
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cmaddhss fr10,fr11,fr12,cc0,0
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219 |
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test_fr_limmed 0xdead,0xbeef,fr12
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220 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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221 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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222 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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223 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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224 |
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225 |
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set_fr_iimmed 0x1234,0x5678,fr10
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226 |
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set_fr_iimmed 0xffff,0xffff,fr11
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227 |
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cmaddhss fr10,fr11,fr12,cc0,0
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228 |
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test_fr_limmed 0xdead,0xbeef,fr12
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229 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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230 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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231 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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232 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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233 |
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234 |
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set_spr_immed 0,msr0
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235 |
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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236 |
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set_fr_iimmed 0x0002,0x0001,fr11
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237 |
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cmaddhss fr10,fr11,fr12,cc4,0
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238 |
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test_fr_limmed 0xdead,0xbeef,fr12
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239 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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240 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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241 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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242 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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243 |
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244 |
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set_spr_immed 0,msr0
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245 |
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set_fr_iimmed 0x8001,0x8001,fr10
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246 |
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set_fr_iimmed 0xffff,0xfffe,fr11
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247 |
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cmaddhss fr10,fr11,fr12,cc4,0
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248 |
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test_fr_limmed 0xdead,0xbeef,fr12
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249 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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250 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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251 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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252 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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253 |
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|
|
254 |
|
|
set_spr_immed 0,msr0
|
255 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
256 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr11
|
257 |
|
|
cmaddhss fr10,fr11,fr12,cc4,0
|
258 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
259 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
260 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
261 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
262 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
263 |
|
|
|
264 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
265 |
|
|
set_spr_immed 0,msr0
|
266 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
267 |
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
268 |
|
|
cmaddhss.p fr10,fr10,fr12,cc4,0
|
269 |
|
|
cmaddhss fr11,fr11,fr13,cc4,0
|
270 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
271 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
272 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
273 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
274 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
275 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
276 |
|
|
|
277 |
|
|
set_fr_iimmed 0xdead,0xbeef,fr12
|
278 |
|
|
set_spr_immed 0,msr0
|
279 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
280 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
281 |
|
|
cmaddhss fr10,fr11,fr12,cc1,1
|
282 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
283 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
284 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
285 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
286 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
287 |
|
|
|
288 |
|
|
set_fr_iimmed 0xdead,0x0000,fr10
|
289 |
|
|
set_fr_iimmed 0x0000,0xbeef,fr11
|
290 |
|
|
cmaddhss fr10,fr11,fr12,cc1,1
|
291 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
292 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
293 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
294 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
295 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
296 |
|
|
|
297 |
|
|
set_fr_iimmed 0x0000,0xdead,fr10
|
298 |
|
|
set_fr_iimmed 0xbeef,0x0000,fr11
|
299 |
|
|
cmaddhss fr10,fr11,fr12,cc1,1
|
300 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
301 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
302 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
303 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
304 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
305 |
|
|
|
306 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
307 |
|
|
set_fr_iimmed 0x1111,0x1111,fr11
|
308 |
|
|
cmaddhss fr10,fr11,fr12,cc1,1
|
309 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
310 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
311 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
312 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
313 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
314 |
|
|
|
315 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
316 |
|
|
set_fr_iimmed 0xffff,0xffff,fr11
|
317 |
|
|
cmaddhss fr10,fr11,fr12,cc1,1
|
318 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
319 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
320 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
321 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
322 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
323 |
|
|
|
324 |
|
|
set_spr_immed 0,msr0
|
325 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
326 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
327 |
|
|
cmaddhss fr10,fr11,fr12,cc5,1
|
328 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
329 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
330 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
331 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
332 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
333 |
|
|
|
334 |
|
|
set_spr_immed 0,msr0
|
335 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
336 |
|
|
set_fr_iimmed 0xffff,0xfffe,fr11
|
337 |
|
|
cmaddhss fr10,fr11,fr12,cc5,1
|
338 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
339 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
340 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
341 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
342 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
343 |
|
|
|
344 |
|
|
set_spr_immed 0,msr0
|
345 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
346 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr11
|
347 |
|
|
cmaddhss fr10,fr11,fr12,cc5,1
|
348 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
349 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
350 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
351 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
352 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
353 |
|
|
|
354 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
355 |
|
|
set_spr_immed 0,msr0
|
356 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
357 |
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
358 |
|
|
cmaddhss.p fr10,fr10,fr12,cc5,1
|
359 |
|
|
cmaddhss fr11,fr11,fr13,cc5,1
|
360 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
361 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
362 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
363 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
364 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
365 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
366 |
|
|
|
367 |
|
|
set_fr_iimmed 0xdead,0xbeef,fr12
|
368 |
|
|
set_spr_immed 0,msr0
|
369 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
370 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
371 |
|
|
cmaddhss fr10,fr11,fr12,cc2,1
|
372 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
373 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
374 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
375 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
376 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
377 |
|
|
|
378 |
|
|
set_fr_iimmed 0xdead,0x0000,fr10
|
379 |
|
|
set_fr_iimmed 0x0000,0xbeef,fr11
|
380 |
|
|
cmaddhss fr10,fr11,fr12,cc2,0
|
381 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
382 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
383 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
384 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
385 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
386 |
|
|
|
387 |
|
|
set_fr_iimmed 0x0000,0xdead,fr10
|
388 |
|
|
set_fr_iimmed 0xbeef,0x0000,fr11
|
389 |
|
|
cmaddhss fr10,fr11,fr12,cc2,1
|
390 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
391 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
392 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
393 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
394 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
395 |
|
|
|
396 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
397 |
|
|
set_fr_iimmed 0x1111,0x1111,fr11
|
398 |
|
|
cmaddhss fr10,fr11,fr12,cc2,0
|
399 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
400 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
401 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
402 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
403 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
404 |
|
|
|
405 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
406 |
|
|
set_fr_iimmed 0xffff,0xffff,fr11
|
407 |
|
|
cmaddhss fr10,fr11,fr12,cc2,1
|
408 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
409 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
410 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
411 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
412 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
413 |
|
|
|
414 |
|
|
set_spr_immed 0,msr0
|
415 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
416 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
417 |
|
|
cmaddhss fr10,fr11,fr12,cc6,0
|
418 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
419 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
420 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
421 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
422 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
423 |
|
|
|
424 |
|
|
set_spr_immed 0,msr0
|
425 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
426 |
|
|
set_fr_iimmed 0xffff,0xfffe,fr11
|
427 |
|
|
cmaddhss fr10,fr11,fr12,cc6,1
|
428 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
429 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
430 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
431 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
432 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
433 |
|
|
|
434 |
|
|
set_spr_immed 0,msr0
|
435 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
436 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr11
|
437 |
|
|
cmaddhss fr10,fr11,fr12,cc6,0
|
438 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
439 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
440 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
441 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
442 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
443 |
|
|
|
444 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
445 |
|
|
set_spr_immed 0,msr0
|
446 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
447 |
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
448 |
|
|
cmaddhss.p fr10,fr10,fr12,cc6,1
|
449 |
|
|
cmaddhss fr11,fr11,fr13,cc6,0
|
450 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
451 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
452 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
453 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
454 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
455 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
456 |
|
|
;
|
457 |
|
|
set_fr_iimmed 0xdead,0xbeef,fr12
|
458 |
|
|
set_spr_immed 0,msr0
|
459 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
460 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
461 |
|
|
cmaddhss fr10,fr11,fr12,cc3,1
|
462 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
463 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
464 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
465 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
466 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
467 |
|
|
|
468 |
|
|
set_fr_iimmed 0xdead,0x0000,fr10
|
469 |
|
|
set_fr_iimmed 0x0000,0xbeef,fr11
|
470 |
|
|
cmaddhss fr10,fr11,fr12,cc3,0
|
471 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
472 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
473 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
474 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
475 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
476 |
|
|
|
477 |
|
|
set_fr_iimmed 0x0000,0xdead,fr10
|
478 |
|
|
set_fr_iimmed 0xbeef,0x0000,fr11
|
479 |
|
|
cmaddhss fr10,fr11,fr12,cc3,1
|
480 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
481 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
482 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
483 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
484 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
485 |
|
|
|
486 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
487 |
|
|
set_fr_iimmed 0x1111,0x1111,fr11
|
488 |
|
|
cmaddhss fr10,fr11,fr12,cc3,0
|
489 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
490 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
491 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
492 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
493 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
494 |
|
|
|
495 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
496 |
|
|
set_fr_iimmed 0xffff,0xffff,fr11
|
497 |
|
|
cmaddhss fr10,fr11,fr12,cc3,1
|
498 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
499 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
500 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
501 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
502 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
503 |
|
|
|
504 |
|
|
set_spr_immed 0,msr0
|
505 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
506 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
507 |
|
|
cmaddhss fr10,fr11,fr12,cc7,0
|
508 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
509 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
510 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
511 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
512 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
513 |
|
|
|
514 |
|
|
set_spr_immed 0,msr0
|
515 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
516 |
|
|
set_fr_iimmed 0xffff,0xfffe,fr11
|
517 |
|
|
cmaddhss fr10,fr11,fr12,cc7,1
|
518 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
519 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
520 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
521 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
522 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
523 |
|
|
|
524 |
|
|
set_spr_immed 0,msr0
|
525 |
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
526 |
|
|
set_fr_iimmed 0xfffe,0xfffe,fr11
|
527 |
|
|
cmaddhss fr10,fr11,fr12,cc7,0
|
528 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
529 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
530 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
531 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
532 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
533 |
|
|
|
534 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
535 |
|
|
set_spr_immed 0,msr0
|
536 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
537 |
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
538 |
|
|
cmaddhss.p fr10,fr10,fr12,cc7,1
|
539 |
|
|
cmaddhss fr11,fr11,fr13,cc7,0
|
540 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
541 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
542 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
543 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
544 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
545 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
546 |
|
|
|
547 |
|
|
pass
|