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jeremybenn |
# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
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# mach: all
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.include "../testutils.inc"
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start
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.global cmsubhus
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cmsubhus:
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set_spr_immed 0x1b1b,cccr
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmsubhus fr10,fr11,fr12,cc0,1
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0xdead,0xbeef,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmsubhus fr10,fr11,fr12,cc0,1
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test_fr_limmed 0xdead,0xbeef,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x1111,0x1111,fr11
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cmsubhus fr10,fr11,fr12,cc0,1
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test_fr_limmed 0x0123,0x4567,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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cmsubhus fr10,fr11,fr12,cc0,1
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test_fr_limmed 0x7ffc,0x7ffd,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x0001,0x0002,fr11
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cmsubhus fr10,fr11,fr12,cc4,1
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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cmsubhus fr10,fr11,fr12,cc4,1
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x0002,0x0002,fr11
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cmsubhus.p fr10,fr10,fr12,cc4,1
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cmsubhus fr10,fr11,fr13,cc4,1
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test_fr_limmed 0x0000,0x0000,fr12
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test_fr_limmed 0x0000,0x0000,fr13
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmsubhus fr10,fr11,fr12,cc1,0
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0xdead,0xbeef,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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cmsubhus fr10,fr11,fr12,cc1,0
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test_fr_limmed 0xdead,0xbeef,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x1111,0x1111,fr11
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cmsubhus fr10,fr11,fr12,cc1,0
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test_fr_limmed 0x0123,0x4567,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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cmsubhus fr10,fr11,fr12,cc1,0
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test_fr_limmed 0x7ffc,0x7ffd,fr12
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| 111 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 113 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x0001,0x0002,fr11
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cmsubhus fr10,fr11,fr12,cc5,0
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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| 123 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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cmsubhus fr10,fr11,fr12,cc5,0
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x0002,0x0002,fr11
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cmsubhus.p fr10,fr10,fr12,cc5,0
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cmsubhus fr10,fr11,fr13,cc5,0
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test_fr_limmed 0x0000,0x0000,fr12
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test_fr_limmed 0x0000,0x0000,fr13
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| 142 |
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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| 143 |
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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| 144 |
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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| 145 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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| 146 |
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| 147 |
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set_fr_iimmed 0xdead,0xbeef,fr12
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set_spr_immed 0,msr0
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| 149 |
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set_fr_iimmed 0x0000,0x0000,fr10
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| 150 |
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set_fr_iimmed 0x0000,0x0000,fr11
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| 151 |
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cmsubhus fr10,fr11,fr12,cc0,0
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| 152 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 153 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 154 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 155 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 156 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 157 |
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| 158 |
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set_fr_iimmed 0xbeef,0xdead,fr10
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| 159 |
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set_fr_iimmed 0x0000,0x0000,fr11
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| 160 |
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cmsubhus fr10,fr11,fr12,cc0,0
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| 161 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 162 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 163 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 164 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 165 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 166 |
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| 167 |
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set_fr_iimmed 0x1234,0x5678,fr10
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| 168 |
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set_fr_iimmed 0x1111,0x1111,fr11
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| 169 |
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cmsubhus fr10,fr11,fr12,cc0,0
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| 170 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 171 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 172 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 173 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 174 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 175 |
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| 176 |
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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| 177 |
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set_fr_iimmed 0x0002,0x0001,fr11
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| 178 |
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cmsubhus fr10,fr11,fr12,cc0,0
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| 179 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 180 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 181 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 182 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 183 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 184 |
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| 185 |
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set_fr_iimmed 0x0001,0x0001,fr10
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| 186 |
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set_fr_iimmed 0x0001,0x0002,fr11
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| 187 |
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cmsubhus fr10,fr11,fr12,cc4,0
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| 188 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 189 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 190 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 191 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 192 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 193 |
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| 194 |
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set_spr_immed 0,msr0
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| 195 |
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set_fr_iimmed 0x0001,0x0001,fr10
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| 196 |
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set_fr_iimmed 0x0002,0x0001,fr11
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| 197 |
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cmsubhus fr10,fr11,fr12,cc4,0
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| 198 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 199 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 200 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 201 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 202 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 203 |
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| 204 |
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set_fr_iimmed 0xbeef,0xdead,fr13
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| 205 |
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set_spr_immed 0,msr0
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| 206 |
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set_fr_iimmed 0x0001,0x0001,fr10
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| 207 |
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set_fr_iimmed 0x0002,0x0002,fr11
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| 208 |
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cmsubhus.p fr10,fr10,fr12,cc4,0
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| 209 |
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cmsubhus fr10,fr11,fr13,cc4,0
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| 210 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 211 |
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test_fr_limmed 0xbeef,0xdead,fr13
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| 212 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 213 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 214 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 215 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 216 |
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| 217 |
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set_fr_iimmed 0xdead,0xbeef,fr12
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| 218 |
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set_spr_immed 0,msr0
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| 219 |
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set_fr_iimmed 0x0000,0x0000,fr10
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| 220 |
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set_fr_iimmed 0x0000,0x0000,fr11
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| 221 |
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cmsubhus fr10,fr11,fr12,cc1,1
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| 222 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 223 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 224 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 225 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 226 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 227 |
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| 228 |
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set_fr_iimmed 0xbeef,0xdead,fr10
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| 229 |
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set_fr_iimmed 0x0000,0x0000,fr11
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| 230 |
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cmsubhus fr10,fr11,fr12,cc1,1
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| 231 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 232 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 233 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 234 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 235 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 236 |
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| 237 |
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set_fr_iimmed 0x1234,0x5678,fr10
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| 238 |
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set_fr_iimmed 0x1111,0x1111,fr11
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| 239 |
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cmsubhus fr10,fr11,fr12,cc1,1
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| 240 |
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test_fr_limmed 0xdead,0xbeef,fr12
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| 241 |
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 242 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 243 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 244 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 245 |
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| 246 |
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
| 247 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
| 248 |
|
|
cmsubhus fr10,fr11,fr12,cc1,1
|
| 249 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 250 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 251 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 252 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 253 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 254 |
|
|
|
| 255 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 256 |
|
|
set_fr_iimmed 0x0001,0x0002,fr11
|
| 257 |
|
|
cmsubhus fr10,fr11,fr12,cc5,1
|
| 258 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 259 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 260 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 261 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 262 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 263 |
|
|
|
| 264 |
|
|
set_spr_immed 0,msr0
|
| 265 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 266 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
| 267 |
|
|
cmsubhus fr10,fr11,fr12,cc5,1
|
| 268 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 269 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 270 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 271 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 272 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 273 |
|
|
|
| 274 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
| 275 |
|
|
set_spr_immed 0,msr0
|
| 276 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 277 |
|
|
set_fr_iimmed 0x0002,0x0002,fr11
|
| 278 |
|
|
cmsubhus.p fr10,fr10,fr12,cc5,1
|
| 279 |
|
|
cmsubhus fr10,fr11,fr13,cc5,1
|
| 280 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 281 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
| 282 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 283 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 284 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 285 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 286 |
|
|
|
| 287 |
|
|
set_fr_iimmed 0xdead,0xbeef,fr12
|
| 288 |
|
|
set_spr_immed 0,msr0
|
| 289 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
| 290 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
| 291 |
|
|
cmsubhus fr10,fr11,fr12,cc2,0
|
| 292 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 293 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 294 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 295 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 296 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 297 |
|
|
|
| 298 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr10
|
| 299 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
| 300 |
|
|
cmsubhus fr10,fr11,fr12,cc2,1
|
| 301 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 302 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 303 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 304 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 305 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 306 |
|
|
|
| 307 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
| 308 |
|
|
set_fr_iimmed 0x1111,0x1111,fr11
|
| 309 |
|
|
cmsubhus fr10,fr11,fr12,cc2,0
|
| 310 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 311 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 312 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 313 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 314 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 315 |
|
|
|
| 316 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
| 317 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
| 318 |
|
|
cmsubhus fr10,fr11,fr12,cc2,1
|
| 319 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 320 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 321 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 322 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 323 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 324 |
|
|
|
| 325 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 326 |
|
|
set_fr_iimmed 0x0001,0x0002,fr11
|
| 327 |
|
|
cmsubhus fr10,fr11,fr12,cc6,0
|
| 328 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 329 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 330 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 331 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 332 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 333 |
|
|
|
| 334 |
|
|
set_spr_immed 0,msr0
|
| 335 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 336 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
| 337 |
|
|
cmsubhus fr10,fr11,fr12,cc6,1
|
| 338 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 339 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 340 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 341 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 342 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 343 |
|
|
|
| 344 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
| 345 |
|
|
set_spr_immed 0,msr0
|
| 346 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 347 |
|
|
set_fr_iimmed 0x0002,0x0002,fr11
|
| 348 |
|
|
cmsubhus.p fr10,fr10,fr12,cc6,0
|
| 349 |
|
|
cmsubhus fr10,fr11,fr13,cc6,1
|
| 350 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 351 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
| 352 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 353 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 354 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 355 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 356 |
|
|
;
|
| 357 |
|
|
set_fr_iimmed 0xdead,0xbeef,fr12
|
| 358 |
|
|
set_spr_immed 0,msr0
|
| 359 |
|
|
set_fr_iimmed 0x0000,0x0000,fr10
|
| 360 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
| 361 |
|
|
cmsubhus fr10,fr11,fr12,cc3,0
|
| 362 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 363 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 364 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 365 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 366 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 367 |
|
|
|
| 368 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr10
|
| 369 |
|
|
set_fr_iimmed 0x0000,0x0000,fr11
|
| 370 |
|
|
cmsubhus fr10,fr11,fr12,cc3,1
|
| 371 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 372 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 373 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 374 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 375 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 376 |
|
|
|
| 377 |
|
|
set_fr_iimmed 0x1234,0x5678,fr10
|
| 378 |
|
|
set_fr_iimmed 0x1111,0x1111,fr11
|
| 379 |
|
|
cmsubhus fr10,fr11,fr12,cc3,0
|
| 380 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 381 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 382 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 383 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 384 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 385 |
|
|
|
| 386 |
|
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10
|
| 387 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
| 388 |
|
|
cmsubhus fr10,fr11,fr12,cc3,1
|
| 389 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 390 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 391 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 392 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 393 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 394 |
|
|
|
| 395 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 396 |
|
|
set_fr_iimmed 0x0001,0x0002,fr11
|
| 397 |
|
|
cmsubhus fr10,fr11,fr12,cc7,0
|
| 398 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 399 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 400 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 401 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 402 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 403 |
|
|
|
| 404 |
|
|
set_spr_immed 0,msr0
|
| 405 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 406 |
|
|
set_fr_iimmed 0x0002,0x0001,fr11
|
| 407 |
|
|
cmsubhus fr10,fr11,fr12,cc7,1
|
| 408 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 409 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 410 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 411 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 412 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 413 |
|
|
|
| 414 |
|
|
set_fr_iimmed 0xbeef,0xdead,fr13
|
| 415 |
|
|
set_spr_immed 0,msr0
|
| 416 |
|
|
set_fr_iimmed 0x0001,0x0001,fr10
|
| 417 |
|
|
set_fr_iimmed 0x0002,0x0002,fr11
|
| 418 |
|
|
cmsubhus.p fr10,fr10,fr12,cc7,0
|
| 419 |
|
|
cmsubhus fr10,fr11,fr13,cc7,1
|
| 420 |
|
|
test_fr_limmed 0xdead,0xbeef,fr12
|
| 421 |
|
|
test_fr_limmed 0xbeef,0xdead,fr13
|
| 422 |
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
| 423 |
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
| 424 |
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
| 425 |
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
|
| 426 |
|
|
|
| 427 |
|
|
pass
|
