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jeremybenn |
# frv testcase for mmachs $GRi,$GRj,$ACCk
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# mach: all
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.include "../testutils.inc"
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start
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.global mmachs
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mmachs:
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; Positive operands
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set_fr_iimmed 2,3,fr7 ; multiply small numbers
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set_fr_iimmed 3,2,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_immed 6,acc0
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test_accg_immed 0,accg1
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test_acc_immed 6,acc1
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set_fr_iimmed 0,1,fr7 ; multiply by 0
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set_fr_iimmed 2,0,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_immed 6,acc0
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test_accg_immed 0,accg1
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test_acc_immed 6,acc1
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set_fr_iimmed 2,1,fr7 ; multiply by 1
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set_fr_iimmed 1,2,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_immed 8,acc0
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test_accg_immed 0,accg1
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test_acc_immed 8,acc1
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set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
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set_fr_iimmed 2,0x3fff,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0,0x8006,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0,0x8006,acc1
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set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
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set_fr_iimmed 2,0x4000,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0001,0x0006,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0001,0x0006,acc1
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set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
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set_fr_iimmed 0x7fff,0x7fff,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x4000,0x0007,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x4000,0x0007,acc1
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; Mixed operands
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set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
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set_fr_iimmed 0xfffd,2,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x4000,0x0001,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x4000,0x0001,acc1
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set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
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set_fr_iimmed 1,0xfffe,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x3fff,0xffff,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x3fff,0xffff,acc1
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set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
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set_fr_iimmed 0,0xfffe,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x3fff,0xffff,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x3fff,0xffff,acc1
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set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
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set_fr_iimmed 0xfffe,0x2001,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x3fff,0xbffd,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x3fff,0xbffd,acc1
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set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
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set_fr_iimmed 0xfffe,0x4000,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg0
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test_acc_limmed 0x3fff,0x3ffd,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x3fff,0x3ffd,acc1
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set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
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set_fr_iimmed 0x8000,0x7fff,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0xff,accg0
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test_acc_limmed 0xffff,0xbffd,acc0
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test_accg_immed 0xff,accg1
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test_acc_limmed 0xffff,0xbffd,acc1
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; Negative operands
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set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
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set_fr_iimmed 0xfffd,0xfffe,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 161 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 162 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 163 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0xff,accg0
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test_acc_limmed 0xffff,0xc003,acc0
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test_accg_immed 0xff,accg1
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test_acc_limmed 0xffff,0xc003,acc1
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set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
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set_fr_iimmed 0xfffe,0xffff,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 175 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 176 |
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test_accg_immed 0xff,accg0
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test_acc_limmed 0xffff,0xc005,acc0
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| 178 |
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test_accg_immed 0xff,accg1
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test_acc_limmed 0xffff,0xc005,acc1
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| 181 |
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set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
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set_fr_iimmed 0x8001,0x8001,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 185 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 186 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 187 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 188 |
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test_accg_immed 0,accg0
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| 189 |
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test_acc_immed 0x3ffec006,acc0
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test_accg_immed 0,accg1
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| 191 |
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test_acc_immed 0x3ffec006,acc1
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set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr8
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mmachs fr7,fr8,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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| 197 |
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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| 198 |
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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| 199 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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| 200 |
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test_accg_immed 0,accg0
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| 201 |
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test_acc_immed 0x7ffec006,acc0
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| 202 |
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test_accg_immed 0,accg1
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| 203 |
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test_acc_immed 0x7ffec006,acc1
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| 204 |
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| 205 |
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set_accg_immed 0x7f,accg0 ; saturation
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| 206 |
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set_acc_immed 0xffffffff,acc0
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| 207 |
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set_accg_immed 0x7f,accg1
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| 208 |
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set_acc_immed 0xffffffff,acc1
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| 209 |
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set_fr_iimmed 1,1,fr7
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| 210 |
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set_fr_iimmed 1,1,fr8
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| 211 |
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mmachs fr7,fr8,acc0
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| 212 |
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test_accg_immed 0x7f,accg0
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| 213 |
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test_acc_limmed 0xffff,0xffff,acc0
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| 214 |
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test_accg_immed 0x7f,accg1
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| 215 |
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test_acc_limmed 0xffff,0xffff,acc1
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| 216 |
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| 217 |
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set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
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| 218 |
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set_fr_iimmed 0x7fff,0x7fff,fr8
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| 219 |
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mmachs fr7,fr8,acc0
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| 220 |
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test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
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| 221 |
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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| 222 |
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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| 223 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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| 224 |
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test_accg_immed 0x7f,accg0
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| 225 |
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test_acc_limmed 0xffff,0xffff,acc0
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| 226 |
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test_accg_immed 0x7f,accg1
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| 227 |
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test_acc_limmed 0xffff,0xffff,acc1
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| 228 |
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| 229 |
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set_accg_immed 0x80,accg0 ; saturation
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| 230 |
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set_acc_immed 0,acc0
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| 231 |
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set_accg_immed 0x80,accg1
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| 232 |
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set_acc_immed 0,acc1
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| 233 |
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set_fr_iimmed 0xffff,0,fr7
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| 234 |
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set_fr_iimmed 1,0xffff,fr8
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| 235 |
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mmachs fr7,fr8,acc0
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| 236 |
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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| 237 |
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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| 238 |
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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| 239 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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| 240 |
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test_accg_immed 0x80,accg0
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| 241 |
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test_acc_immed 0,acc0
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| 242 |
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test_accg_immed 0x80,accg1
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| 243 |
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test_acc_immed 0,acc1
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| 244 |
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| 245 |
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set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
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| 246 |
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set_fr_iimmed 0x7fff,0x7fff,fr8
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| 247 |
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mmachs fr7,fr8,acc0
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| 248 |
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test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
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| 249 |
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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| 250 |
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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| 251 |
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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| 252 |
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test_accg_immed 0x80,accg0
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| 253 |
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test_acc_immed 0,acc0
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| 254 |
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test_accg_immed 0x80,accg1
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| 255 |
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test_acc_immed 0,acc1
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| 256 |
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| 257 |
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pass
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| 258 |
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| 259 |
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