URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [ftug.cgs] - Blame information for rev 840

Details | Compare with Previous | View Log


# frv testcase for ftug $FCCi_2,$GRi,$GRj
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global ftug
ftug:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
        set_gr_immed    4,gr8
 
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok1,lr
        set_fcc         0x1 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok1:
        set_psr_et      1
        set_spr_addr    ok2,lr
        set_fcc         0x2 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok2:
        set_psr_et      1
        set_spr_addr    ok3,lr
        set_fcc         0x3 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok3:
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok5,lr
        set_fcc         0x5 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok5:
        set_psr_et      1
        set_spr_addr    ok6,lr
        set_fcc         0x6 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok6:
        set_psr_et      1
        set_spr_addr    ok7,lr
        set_fcc         0x7 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok7:
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok9,lr
        set_fcc         0x9 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
ok9:
        set_psr_et      1
        set_spr_addr    oka,lr
        set_fcc         0xa 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
oka:
        set_psr_et      1
        set_spr_addr    okb,lr
        set_fcc         0xb 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
okb:
        set_spr_addr    bad,lr
        set_fcc         0xc 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    okd,lr
        set_fcc         0xd 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
okd:
        set_psr_et      1
        set_spr_addr    oke,lr
        set_fcc         0xe 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
oke:
        set_psr_et      1
        set_spr_addr    okf,lr
        set_fcc         0xf 0
        ftug            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
        fail
okf:
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	24	jeremybenn	`# frv testcase for ftug $FCCi_2,$GRi,$GRj`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global ftug`
9			`ftug:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17			`set_gr_immed 4,gr8`
18
19			`set_spr_addr bad,lr`
20			`set_fcc 0x0 0`
21			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
22
23			`set_psr_et 1`
24			`set_spr_addr ok1,lr`
25			`set_fcc 0x1 0`
26			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
27			`fail`
28			`ok1:`
29			`set_psr_et 1`
30			`set_spr_addr ok2,lr`
31			`set_fcc 0x2 0`
32			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
33			`fail`
34			`ok2:`
35			`set_psr_et 1`
36			`set_spr_addr ok3,lr`
37			`set_fcc 0x3 0`
38			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
39			`fail`
40			`ok3:`
41			`set_spr_addr bad,lr`
42			`set_fcc 0x4 0`
43			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
44
45			`set_psr_et 1`
46			`set_spr_addr ok5,lr`
47			`set_fcc 0x5 0`
48			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
49			`fail`
50			`ok5:`
51			`set_psr_et 1`
52			`set_spr_addr ok6,lr`
53			`set_fcc 0x6 0`
54			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
55			`fail`
56			`ok6:`
57			`set_psr_et 1`
58			`set_spr_addr ok7,lr`
59			`set_fcc 0x7 0`
60			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
61			`fail`
62			`ok7:`
63			`set_spr_addr bad,lr`
64			`set_fcc 0x8 0`
65			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
66
67			`set_psr_et 1`
68			`set_spr_addr ok9,lr`
69			`set_fcc 0x9 0`
70			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
71			`fail`
72			`ok9:`
73			`set_psr_et 1`
74			`set_spr_addr oka,lr`
75			`set_fcc 0xa 0`
76			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
77			`fail`
78			`oka:`
79			`set_psr_et 1`
80			`set_spr_addr okb,lr`
81			`set_fcc 0xb 0`
82			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
83			`fail`
84			`okb:`
85			`set_spr_addr bad,lr`
86			`set_fcc 0xc 0`
87			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
88
89			`set_psr_et 1`
90			`set_spr_addr okd,lr`
91			`set_fcc 0xd 0`
92			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
93			`fail`
94			`okd:`
95			`set_psr_et 1`
96			`set_spr_addr oke,lr`
97			`set_fcc 0xe 0`
98			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
99			`fail`
100			`oke:`
101			`set_psr_et 1`
102			`set_spr_addr okf,lr`
103			`set_fcc 0xf 0`
104			`ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16`
105			`fail`
106			`okf:`
107			`pass`
108			`bad:`
109			`fail`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [ftug.cgs] - Blame information for rev 840