OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [icpl.cgs] - Blame information for rev 840

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# FRV testcase for icpl GRi,GRj,lock
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global icpl
9
        ; keep this at least 64 bytes away from doit2
10
        bra             icpl
11
doit1:  add             gr11,gr12,gr11
12
        bralr
13
 
14
icpl:
15
        or_spr_immed    0x80000000,hsr0 ; insn cache: enable
16
        and_spr_immed   0xbfffffff,hsr0 ; data cache: disable
17
        set_gr_immed    0,gr11
18
        set_gr_immed    1,gr12
19
        set_gr_immed    2,gr13
20
 
21
        set_gr_addr     doit1,gr10
22
        icpl            gr10,gr0,0      ; preload insns at doit1
23
        set_mem_immed   0x9600b00d,gr10 ; change to add gr11,gr13,gr11
24
 
25
        set_gr_addr     doit2,gr10
26
        set_mem_immed   0x9600b00d,gr10 ; change to add gr11,gr13,gr11
27
 
28
        set_spr_addr    ok1,lr
29
        bra             doit1
30
ok1:    test_gr_immed   1,gr11          ; used preloaded add of 1
31
 
32
        set_spr_addr    ok2,lr
33
        bra             doit2
34
ok2:    test_gr_immed   3,gr11          ; used changed add of 2
35
 
36
        pass
37
 
38
doit2:  add             gr11,gr12,gr11
39
        bralr

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.