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jeremybenn |
# frv testcase for mqmachs $GRi,$GRj,$ACCk
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# mach: frv fr500 fr400
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.include "testutils.inc"
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start
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.global mqmachs
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mqmachs:
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; Positive operands
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set_fr_iimmed 2,3,fr8 ; multiply small numbers
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set_fr_iimmed 3,2,fr10
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set_fr_iimmed 0,1,fr9 ; multiply by 0
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set_fr_iimmed 2,0,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_immed 6,acc0
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test_accg_immed 0,accg1
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test_acc_immed 6,acc1
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test_accg_immed 0,accg2
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test_acc_immed 0,acc2
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test_accg_immed 0,accg3
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test_acc_immed 0,acc3
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set_fr_iimmed 2,1,fr8 ; multiply by 1
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set_fr_iimmed 1,2,fr10
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set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
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set_fr_iimmed 2,0x3fff,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_immed 8,acc0
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test_accg_immed 0,accg1
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test_acc_immed 8,acc1
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test_accg_immed 0,accg2
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test_acc_limmed 0,0x7ffe,acc2
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test_accg_immed 0,accg3
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test_acc_limmed 0,0x7ffe,acc3
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set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
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set_fr_iimmed 2,0x4000,fr10
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set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
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set_fr_iimmed 0x7fff,0x7fff,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0x8008,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x8008,acc1
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test_accg_immed 0,accg2
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test_acc_limmed 0x3fff,0x7fff,acc2
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test_accg_immed 0,accg3
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test_acc_limmed 0x3fff,0x7fff,acc3
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; Mixed operands
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set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
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set_fr_iimmed 0xfffd,2,fr10
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set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
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set_fr_iimmed 1,0xfffe,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0x8002,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x8002,acc1
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test_accg_immed 0,accg2
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test_acc_limmed 0x3fff,0x7ffd,acc2
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test_accg_immed 0,accg3
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test_acc_limmed 0x3fff,0x7ffd,acc3
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set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
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set_fr_iimmed 0,0xfffe,fr10
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set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
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set_fr_iimmed 0xfffe,0x2001,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0x8002,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x8002,acc1
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test_accg_immed 0,accg2
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test_acc_limmed 0x3fff,0x3ffb,acc2
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test_accg_immed 0,accg3
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test_acc_limmed 0x3fff,0x3ffb,acc3
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set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
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set_fr_iimmed 0xfffe,0x4000,fr10
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set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
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set_fr_iimmed 0x8000,0x7fff,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0x0002,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x0002,acc1
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test_accg_immed 0xff,accg2
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test_acc_limmed 0xffff,0xbffb,acc2
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test_accg_immed 0xff,accg3
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test_acc_limmed 0xffff,0xbffb,acc3
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; Negative operands
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set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
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set_fr_iimmed 0xfffd,0xfffe,fr10
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set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
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set_fr_iimmed 0xfffe,0xffff,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0x0008,acc0
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x0008,acc1
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test_accg_immed 0xff,accg2
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test_acc_limmed 0xffff,0xbffd,acc2
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test_accg_immed 0xff,accg3
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test_acc_limmed 0xffff,0xbffd,acc3
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set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
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set_fr_iimmed 0x8001,0x8001,fr10
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set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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test_accg_immed 0,accg0
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test_acc_immed 0x3fff0009,acc0
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test_accg_immed 0,accg1
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test_acc_immed 0x3fff0009,acc1
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test_accg_immed 0,accg2
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test_acc_immed 0x3fffbffd,acc2
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test_accg_immed 0,accg3
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test_acc_immed 0x3fffbffd,acc3
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set_accg_immed 0x7f,accg0 ; saturation
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set_acc_immed 0xffffffff,acc0
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set_accg_immed 0x7f,accg1
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set_acc_immed 0xffffffff,acc1
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set_accg_immed 0x7f,accg2 ; saturation
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set_acc_immed 0xffffffff,acc2
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set_accg_immed 0x7f,accg3
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set_acc_immed 0xffffffff,acc3
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set_fr_iimmed 1,1,fr8
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set_fr_iimmed 1,1,fr10
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set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
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set_fr_iimmed 0x7fff,0x7fff,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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test_accg_immed 0x7f,accg0
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test_acc_limmed 0xffff,0xffff,acc0
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test_accg_immed 0x7f,accg1
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test_acc_limmed 0xffff,0xffff,acc1
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test_accg_immed 0x7f,accg2
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test_acc_limmed 0xffff,0xffff,acc2
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test_accg_immed 0x7f,accg3
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test_acc_limmed 0xffff,0xffff,acc3
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set_accg_immed 0x80,accg0 ; saturation
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set_acc_immed 0,acc0
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set_accg_immed 0x80,accg1
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set_acc_immed 0,acc1
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set_accg_immed 0x80,accg2 ; saturation
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set_acc_immed 0,acc2
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set_accg_immed 0x80,accg3
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set_acc_immed 0,acc3
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set_fr_iimmed 0xffff,0,fr8
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set_fr_iimmed 1,0xffff,fr10
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set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
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set_fr_iimmed 0x7fff,0x7fff,fr11
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mqmachs fr8,fr10,acc0
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test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
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test_accg_immed 0x80,accg0
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test_acc_immed 0,acc0
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test_accg_immed 0x80,accg1
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test_acc_immed 0,acc1
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test_accg_immed 0x80,accg2
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test_acc_immed 0,acc2
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test_accg_immed 0x80,accg3
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test_acc_immed 0,acc3
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pass
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