URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tihi.cgs] - Blame information for rev 827

Go to most recent revision | Details | Compare with Previous | View Log


# frv testcase for tihi $ICCi_2,$GRi,$s12
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global tihi
tihi:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
 
        set_psr_et      1
        set_spr_addr    ok0,lr
        set_icc         0x0 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok0:
        set_spr_addr    bad,lr
        set_icc         0x1 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok2,lr
        set_icc         0x2 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok2:
        set_spr_addr    bad,lr
        set_icc         0x3 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x4 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x5 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x6 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0x7 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok8,lr
        set_icc         0x8 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok8:
        set_spr_addr    bad,lr
        set_icc         0x9 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    oka,lr
        set_icc         0xa 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oka:
        set_spr_addr    bad,lr
        set_icc         0xb 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0xc 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0xd 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0xe 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_spr_addr    bad,lr
        set_icc         0xf 0
        tihi            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	24	jeremybenn	`# frv testcase for tihi $ICCi_2,$GRi,$s12`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global tihi`
9			`tihi:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17
18			`set_psr_et 1`
19			`set_spr_addr ok0,lr`
20			`set_icc 0x0 0`
21			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
22			`fail`
23			`ok0:`
24			`set_spr_addr bad,lr`
25			`set_icc 0x1 0`
26			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
27
28			`set_psr_et 1`
29			`set_spr_addr ok2,lr`
30			`set_icc 0x2 0`
31			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
32			`fail`
33			`ok2:`
34			`set_spr_addr bad,lr`
35			`set_icc 0x3 0`
36			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
37
38			`set_spr_addr bad,lr`
39			`set_icc 0x4 0`
40			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
41
42			`set_spr_addr bad,lr`
43			`set_icc 0x5 0`
44			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
45
46			`set_spr_addr bad,lr`
47			`set_icc 0x6 0`
48			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
49
50			`set_spr_addr bad,lr`
51			`set_icc 0x7 0`
52			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
53
54			`set_psr_et 1`
55			`set_spr_addr ok8,lr`
56			`set_icc 0x8 0`
57			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
58			`fail`
59			`ok8:`
60			`set_spr_addr bad,lr`
61			`set_icc 0x9 0`
62			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
63
64			`set_psr_et 1`
65			`set_spr_addr oka,lr`
66			`set_icc 0xa 0`
67			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
68			`fail`
69			`oka:`
70			`set_spr_addr bad,lr`
71			`set_icc 0xb 0`
72			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
73
74			`set_spr_addr bad,lr`
75			`set_icc 0xc 0`
76			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
77
78			`set_spr_addr bad,lr`
79			`set_icc 0xd 0`
80			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
81
82			`set_spr_addr bad,lr`
83			`set_icc 0xe 0`
84			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
85
86			`set_spr_addr bad,lr`
87			`set_icc 0xf 0`
88			`tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
89
90			`pass`
91			`bad:`
92			`fail`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tihi.cgs] - Blame information for rev 827