OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tno.cgs] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# frv testcase for tno
2 
# mach: all
3 
 
4 
        .include "testutils.inc"
5 
 
6 
        start
7 
 
8 
        .global tno
9 
tno:
10 
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11 
        set_gr_spr      tbr,gr7
12 
        inc_gr_immed    2112,gr7                ; address of exception handler
13 
        set_mem_limmed  0x0038,0x2000,gr7       ; bctrlr 0,0
14 
 
15 
        set_spr_immed   128,lcr
16 
        set_spr_addr    bad,lr
17 
        set_gr_immed    0,gr7
18 
        set_gr_immed    4,gr8
19 
 
20 
        set_icc         0x0 0
21 
        tno                     ; should branch to tbr + (128 + 4)*16
22 
        set_icc         0x1 0
23 
        tno                     ; should branch to tbr + (128 + 4)*16
24 
        set_icc         0x2 0
25 
        tno                     ; should branch to tbr + (128 + 4)*16
26 
        set_icc         0x3 0
27 
        tno                     ; should branch to tbr + (128 + 4)*16
28 
        set_icc         0x4 0
29 
        tno                     ; should branch to tbr + (128 + 4)*16
30 
        set_icc         0x5 0
31 
        tno                     ; should branch to tbr + (128 + 4)*16
32 
        set_icc         0x6 0
33 
        tno                     ; should branch to tbr + (128 + 4)*16
34 
        set_icc         0x7 0
35 
        tno                     ; should branch to tbr + (128 + 4)*16
36 
        set_icc         0x8 0
37 
        tno                     ; should branch to tbr + (128 + 4)*16
38 
        set_icc         0x9 0
39 
        tno                     ; should branch to tbr + (128 + 4)*16
40 
        set_icc         0xa 0
41 
        tno                     ; should branch to tbr + (128 + 4)*16
42 
        set_icc         0xb 0
43 
        tno                     ; should branch to tbr + (128 + 4)*16
44 
        set_icc         0xc 0
45 
        tno                     ; should branch to tbr + (128 + 4)*16
46 
        set_icc         0xd 0
47 
        tno                     ; should branch to tbr + (128 + 4)*16
48 
        set_icc         0xe 0
49 
        tno                     ; should branch to tbr + (128 + 4)*16
50 
        set_icc         0xf 0
51 
        tno                     ; should branch to tbr + (128 + 4)*16
52 
        pass
53 
bad:
54 
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.