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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [bset.s] - Blame information for rev 840

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Line No. Rev Author Line
1 24 jeremybenn
# Hitachi H8 testcase 'bset', 'bclr'
2
# mach(): all
3
# as(h8300):    --defsym sim_cpu=0
4
# as(h8300h):   --defsym sim_cpu=1
5
# as(h8300s):   --defsym sim_cpu=2
6
# as(h8sx):     --defsym sim_cpu=3
7
# ld(h8300h):   -m h8300helf
8
# ld(h8300s):   -m h8300self
9
# ld(h8sx):     -m h8300sxelf
10
 
11
        .include "testutils.inc"
12
 
13
        # Instructions tested:
14
        #
15
        # bset xx:3, rd8        ;                   7 0 ?xxx rd8
16
        # bclr xx:3, rd8        ;                   7 2 ?xxx rd8
17
        # bset xx:3, @erd       ; 7 d 0rd ????      7 0 ?xxx ????
18
        # bclr xx:3, @erd       ; 7 d 0rd ????      7 2 ?xxx ????
19
        # bset xx:3, @abs16     ; 6 a 1 1??? aa:16  7 0 ?xxx ????
20
        # bclr xx:3, @abs16     ; 6 a 1 1??? aa:16  7 2 ?xxx ???? 
21
        # bset reg8, rd8        ;                   6 0 rs8  rd8
22
        # bclr reg8, rd8        ;                   6 2 rs8  rd8
23
        # bset reg8, @erd       ; 7 d 0rd ????      6 0 rs8  ????
24
        # bclr reg8, @erd       ; 7 d 0rd ????      6 2 rs8  ????
25
        # bset reg8, @abs32     ; 6 a 3 1??? aa:32  6 0 rs8  ????
26
        # bclr reg8, @abs32     ; 6 a 3 1??? aa:32  6 2 rs8  ???? 
27
        #
28
        # bset/eq xx:3, rd8
29
        # bclr/eq xx:3, rd8
30
        # bset/ne xx:3, rd8
31
        # bclr/ne xx:3, rd8
32
 
33
        .data
34
byte_dst:       .byte 0
35
 
36
        start
37
 
38
bset_imm3_reg8:
39
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
40
 
41
        ;;  bset xx:3, rd8
42
        mov     #0, r1l
43
        set_ccr_zero
44
        bset    #0, r1l
45
        test_cc_clear
46
        test_h_gr8 1 r1l
47
 
48
        set_ccr_zero
49
        bset    #1, r1l
50
        test_cc_clear
51
        test_h_gr8 3 r1l
52
 
53
        set_ccr_zero
54
        bset    #2, r1l
55
        test_cc_clear
56
        test_h_gr8 7 r1l
57
 
58
        set_ccr_zero
59
        bset    #3, r1l
60
        test_cc_clear
61
        test_h_gr8 15 r1l
62
 
63
        set_ccr_zero
64
        bset    #4, r1l
65
        test_cc_clear
66
        test_h_gr8 31 r1l
67
 
68
        set_ccr_zero
69
        bset    #5, r1l
70
        test_cc_clear
71
        test_h_gr8 63 r1l
72
 
73
        set_ccr_zero
74
        bset    #6, r1l
75
        test_cc_clear
76
        test_h_gr8 127 r1l
77
 
78
        set_ccr_zero
79
        bset    #7, r1l
80
        test_cc_clear
81
        test_h_gr8 255 r1l
82
 
83
.if (sim_cpu == h8300)
84
        test_h_gr16 0xa5ff, r1
85
.else
86
        test_h_gr32  0xa5a5a5ff er1
87
.endif
88
 
89
bclr_imm3_reg8:
90
        set_ccr_zero
91
        bclr    #7, r1l
92
        test_cc_clear
93
        test_h_gr8 127 r1l
94
 
95
        set_ccr_zero
96
        bclr    #6, r1l
97
        test_cc_clear
98
        test_h_gr8 63 r1l
99
 
100
        set_ccr_zero
101
        bclr    #5, r1l
102
        test_cc_clear
103
        test_h_gr8 31 r1l
104
 
105
        set_ccr_zero
106
        bclr    #4, r1l
107
        test_cc_clear
108
        test_h_gr8 15 r1l
109
 
110
        set_ccr_zero
111
        bclr    #3, r1l
112
        test_cc_clear
113
        test_h_gr8 7 r1l
114
 
115
        set_ccr_zero
116
        bclr    #2, r1l
117
        test_cc_clear
118
        test_h_gr8 3 r1l
119
 
120
        set_ccr_zero
121
        bclr    #1, r1l
122
        test_cc_clear
123
        test_h_gr8 1 r1l
124
 
125
        set_ccr_zero
126
        bclr    #0, r1l
127
        test_cc_clear
128
        test_h_gr8 0 r1l
129
 
130
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
131
.if (sim_cpu == h8300)
132
        test_h_gr16 0xa500 r1
133
.else
134
        test_h_gr32  0xa5a5a500 er1
135
.endif
136
        test_gr_a5a5 2
137
        test_gr_a5a5 3
138
        test_gr_a5a5 4
139
        test_gr_a5a5 5
140
        test_gr_a5a5 6
141
        test_gr_a5a5 7
142
 
143
.if (sim_cpu)
144
bset_imm3_ind:
145
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
146
 
147
        ;;  bset xx:3, @erd
148
        mov     #byte_dst, er1
149
        set_ccr_zero
150
        bset    #0, @er1
151
        test_cc_clear
152
        mov     @er1, r2l
153
        test_h_gr8 1 r2l
154
 
155
        set_ccr_zero
156
        bset    #1, @er1
157
        test_cc_clear
158
        mov     @er1, r2l
159
        test_h_gr8 3 r2l
160
 
161
        set_ccr_zero
162
        bset    #2, @er1
163
        test_cc_clear
164
        mov     @er1, r2l
165
        test_h_gr8 7 r2l
166
 
167
        set_ccr_zero
168
        bset    #3, @er1
169
        test_cc_clear
170
        mov     @er1, r2l
171
        test_h_gr8 15 r2l
172
 
173
        set_ccr_zero
174
        bset    #4, @er1
175
        test_cc_clear
176
        mov     @er1, r2l
177
        test_h_gr8 31 r2l
178
 
179
        set_ccr_zero
180
        bset    #5, @er1
181
        test_cc_clear
182
        mov     @er1, r2l
183
        test_h_gr8 63 r2l
184
 
185
        set_ccr_zero
186
        bset    #6, @er1
187
        test_cc_clear
188
        mov     @er1, r2l
189
        test_h_gr8 127 r2l
190
 
191
        set_ccr_zero
192
        bset    #7, @er1
193
        test_cc_clear
194
        mov     @er1, r2l
195
        test_h_gr8 255 r2l
196
 
197
.if (sim_cpu == h8300)
198
        test_h_gr16  0xa5ff r2
199
.else
200
        test_h_gr32  0xa5a5a5ff er2
201
.endif
202
 
203
bclr_imm3_ind:
204
        set_ccr_zero
205
        bclr    #7, @er1
206
        test_cc_clear
207
        mov     @er1, r2l
208
        test_h_gr8 127 r2l
209
 
210
        set_ccr_zero
211
        bclr    #6, @er1
212
        test_cc_clear
213
        mov     @er1, r2l
214
        test_h_gr8 63 r2l
215
 
216
        set_ccr_zero
217
        bclr    #5, @er1
218
        test_cc_clear
219
        mov     @er1, r2l
220
        test_h_gr8 31 r2l
221
 
222
        set_ccr_zero
223
        bclr    #4, @er1
224
        test_cc_clear
225
        mov     @er1, r2l
226
        test_h_gr8 15 r2l
227
 
228
        set_ccr_zero
229
        bclr    #3, @er1
230
        test_cc_clear
231
        mov     @er1, r2l
232
        test_h_gr8 7  r2l
233
 
234
        set_ccr_zero
235
        bclr    #2, @er1
236
        test_cc_clear
237
        mov     @er1, r2l
238
        test_h_gr8 3  r2l
239
 
240
        set_ccr_zero
241
        bclr    #1, @er1
242
        test_cc_clear
243
        mov     @er1, r2l
244
        test_h_gr8 1  r2l
245
 
246
        set_ccr_zero
247
        bclr    #0, @er1
248
        test_cc_clear
249
        mov     @er1, r2l
250
        test_h_gr8 0  r2l
251
 
252
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
253
.if (sim_cpu == h8300)
254
        test_h_gr16  byte_dst r1
255
        test_h_gr16  0xa500   r2
256
.else
257
        test_h_gr32  byte_dst   er1
258
        test_h_gr32  0xa5a5a500 er2
259
.endif
260
        test_gr_a5a5 3
261
        test_gr_a5a5 4
262
        test_gr_a5a5 5
263
        test_gr_a5a5 6
264
        test_gr_a5a5 7
265
 
266
.if (sim_cpu > h8300h)
267
bset_imm3_abs16:
268
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
269
 
270
        ;;  bset xx:3, @aa:16
271
        set_ccr_zero
272
        bset    #0, @byte_dst:16
273
        test_cc_clear
274
        mov     @byte_dst, r2l
275
        test_h_gr8 1 r2l
276
 
277
        set_ccr_zero
278
        bset    #1, @byte_dst:16
279
        test_cc_clear
280
        mov     @byte_dst, r2l
281
        test_h_gr8 3 r2l
282
 
283
        set_ccr_zero
284
        bset    #2, @byte_dst:16
285
        test_cc_clear
286
        mov     @byte_dst, r2l
287
        test_h_gr8 7 r2l
288
 
289
        set_ccr_zero
290
        bset    #3, @byte_dst:16
291
        test_cc_clear
292
        mov     @byte_dst, r2l
293
        test_h_gr8 15 r2l
294
 
295
        set_ccr_zero
296
        bset    #4, @byte_dst:16
297
        test_cc_clear
298
        mov     @byte_dst, r2l
299
        test_h_gr8 31 r2l
300
 
301
        set_ccr_zero
302
        bset    #5, @byte_dst:16
303
        test_cc_clear
304
        mov     @byte_dst, r2l
305
        test_h_gr8 63 r2l
306
 
307
        set_ccr_zero
308
        bset    #6, @byte_dst:16
309
        test_cc_clear
310
        mov     @byte_dst, r2l
311
        test_h_gr8 127 r2l
312
 
313
        set_ccr_zero
314
        bset    #7, @byte_dst:16
315
        test_cc_clear
316
        mov     @byte_dst, r2l
317
        test_h_gr8 255 r2l
318
 
319
.if (sim_cpu == h8300)
320
        test_h_gr16  0xa5ff r2
321
.else
322
        test_h_gr32  0xa5a5a5ff er2
323
.endif
324
 
325
bclr_imm3_abs16:
326
        set_ccr_zero
327
        bclr    #7, @byte_dst:16
328
        test_cc_clear
329
        mov     @byte_dst, r2l
330
        test_h_gr8 127 r2l
331
 
332
        set_ccr_zero
333
        bclr    #6, @byte_dst:16
334
        test_cc_clear
335
        mov     @byte_dst, r2l
336
        test_h_gr8 63 r2l
337
 
338
        set_ccr_zero
339
        bclr    #5, @byte_dst:16
340
        test_cc_clear
341
        mov     @byte_dst, r2l
342
        test_h_gr8 31 r2l
343
 
344
        set_ccr_zero
345
        bclr    #4, @byte_dst:16
346
        test_cc_clear
347
        mov     @byte_dst, r2l
348
        test_h_gr8 15 r2l
349
 
350
        set_ccr_zero
351
        bclr    #3, @byte_dst:16
352
        test_cc_clear
353
        mov     @byte_dst, r2l
354
        test_h_gr8 7  r2l
355
 
356
        set_ccr_zero
357
        bclr    #2, @byte_dst:16
358
        test_cc_clear
359
        mov     @byte_dst, r2l
360
        test_h_gr8 3  r2l
361
 
362
        set_ccr_zero
363
        bclr    #1, @byte_dst:16
364
        test_cc_clear
365
        mov     @byte_dst, r2l
366
        test_h_gr8 1  r2l
367
 
368
        set_ccr_zero
369
        bclr    #0, @byte_dst:16
370
        test_cc_clear
371
        mov     @byte_dst, r2l
372
        test_h_gr8 0  r2l
373
 
374
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
375
        test_gr_a5a5 1
376
.if (sim_cpu == h8300)
377
        test_h_gr16  0xa500   r2
378
.else
379
        test_h_gr32  0xa5a5a500 er2
380
.endif
381
        test_gr_a5a5 3
382
        test_gr_a5a5 4
383
        test_gr_a5a5 5
384
        test_gr_a5a5 6
385
        test_gr_a5a5 7
386
.endif
387
.endif
388
 
389
bset_rs8_rd8:
390
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
391
 
392
        ;;  bset rs8, rd8
393
        mov     #0, r1h
394
        mov     #0, r1l
395
        set_ccr_zero
396
        bset    r1h, r1l
397
        test_cc_clear
398
        test_h_gr8 1 r1l
399
 
400
        mov     #1, r1h
401
        set_ccr_zero
402
        bset    r1h, r1l
403
        test_cc_clear
404
        test_h_gr8 3 r1l
405
 
406
        mov     #2, r1h
407
        set_ccr_zero
408
        bset    r1h, r1l
409
        test_cc_clear
410
        test_h_gr8 7 r1l
411
 
412
        mov     #3, r1h
413
        set_ccr_zero
414
        bset    r1h, r1l
415
        test_cc_clear
416
        test_h_gr8 15 r1l
417
 
418
        mov     #4, r1h
419
        set_ccr_zero
420
        bset    r1h, r1l
421
        test_cc_clear
422
        test_h_gr8 31 r1l
423
 
424
        mov     #5, r1h
425
        set_ccr_zero
426
        bset    r1h, r1l
427
        test_cc_clear
428
        test_h_gr8 63 r1l
429
 
430
        mov     #6, r1h
431
        set_ccr_zero
432
        bset    r1h, r1l
433
        test_cc_clear
434
        test_h_gr8 127 r1l
435
 
436
        mov     #7, r1h
437
        set_ccr_zero
438
        bset    r1h, r1l
439
        test_cc_clear
440
        test_h_gr8 255 r1l
441
 
442
.if (sim_cpu == h8300)
443
        test_h_gr16 0x07ff, r1
444
.else
445
        test_h_gr32  0xa5a507ff er1
446
.endif
447
 
448
bclr_rs8_rd8:
449
        mov     #7, r1h
450
        set_ccr_zero
451
        bclr    r1h, r1l
452
        test_cc_clear
453
        test_h_gr8 127 r1l
454
 
455
        mov     #6, r1h
456
        set_ccr_zero
457
        bclr    r1h, r1l
458
        test_cc_clear
459
        test_h_gr8 63 r1l
460
 
461
        mov     #5, r1h
462
        set_ccr_zero
463
        bclr    r1h, r1l
464
        test_cc_clear
465
        test_h_gr8 31 r1l
466
 
467
        mov     #4, r1h
468
        set_ccr_zero
469
        bclr    r1h, r1l
470
        test_cc_clear
471
        test_h_gr8 15 r1l
472
 
473
        mov     #3, r1h
474
        set_ccr_zero
475
        bclr    r1h, r1l
476
        test_cc_clear
477
        test_h_gr8 7 r1l
478
 
479
        mov     #2, r1h
480
        set_ccr_zero
481
        bclr    r1h, r1l
482
        test_cc_clear
483
        test_h_gr8 3 r1l
484
 
485
        mov     #1, r1h
486
        set_ccr_zero
487
        bclr    r1h, r1l
488
        test_cc_clear
489
        test_h_gr8 1 r1l
490
 
491
        mov     #0, r1h
492
        set_ccr_zero
493
        bclr    r1h, r1l
494
        test_cc_clear
495
        test_h_gr8 0 r1l
496
 
497
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
498
.if (sim_cpu == h8300)
499
        test_h_gr16 0x0000 r1
500
.else
501
        test_h_gr32  0xa5a50000 er1
502
.endif
503
        test_gr_a5a5 2
504
        test_gr_a5a5 3
505
        test_gr_a5a5 4
506
        test_gr_a5a5 5
507
        test_gr_a5a5 6
508
        test_gr_a5a5 7
509
 
510
.if (sim_cpu)
511
bset_rs8_ind:
512
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
513
 
514
        ;;  bset rs8, @erd
515
        mov     #byte_dst, er1
516
        mov     #0, r2h
517
        set_ccr_zero
518
        bset    r2h, @er1
519
        test_cc_clear
520
        mov     @er1, r2l
521
        test_h_gr8 1 r2l
522
 
523
        mov     #1, r2h
524
        set_ccr_zero
525
        bset    r2h, @er1
526
        test_cc_clear
527
        mov     @er1, r2l
528
        test_h_gr8 3 r2l
529
 
530
        mov     #2, r2h
531
        set_ccr_zero
532
        bset    r2h, @er1
533
        test_cc_clear
534
        mov     @er1, r2l
535
        test_h_gr8 7 r2l
536
 
537
        mov     #3, r2h
538
        set_ccr_zero
539
        bset    r2h, @er1
540
        test_cc_clear
541
        mov     @er1, r2l
542
        test_h_gr8 15 r2l
543
 
544
        mov     #4, r2h
545
        set_ccr_zero
546
        bset    r2h, @er1
547
        test_cc_clear
548
        mov     @er1, r2l
549
        test_h_gr8 31 r2l
550
 
551
        mov     #5, r2h
552
        set_ccr_zero
553
        bset    r2h, @er1
554
        test_cc_clear
555
        mov     @er1, r2l
556
        test_h_gr8 63 r2l
557
 
558
        mov     #6, r2h
559
        set_ccr_zero
560
        bset    r2h, @er1
561
        test_cc_clear
562
        mov     @er1, r2l
563
        test_h_gr8 127 r2l
564
 
565
        mov     #7, r2h
566
        set_ccr_zero
567
        bset    r2h, @er1
568
        test_cc_clear
569
        mov     @er1, r2l
570
        test_h_gr8 255 r2l
571
 
572
.if (sim_cpu == h8300)
573
        test_h_gr16  0x07ff r2
574
.else
575
        test_h_gr32  0xa5a507ff er2
576
.endif
577
 
578
bclr_rs8_ind:
579
        mov     #7, r2h
580
        set_ccr_zero
581
        bclr    r2h, @er1
582
        test_cc_clear
583
        mov     @er1, r2l
584
        test_h_gr8 127 r2l
585
 
586
        mov     #6, r2h
587
        set_ccr_zero
588
        bclr    r2h, @er1
589
        test_cc_clear
590
        mov     @er1, r2l
591
        test_h_gr8 63 r2l
592
 
593
        mov     #5, r2h
594
        set_ccr_zero
595
        bclr    r2h, @er1
596
        test_cc_clear
597
        mov     @er1, r2l
598
        test_h_gr8 31 r2l
599
 
600
        mov     #4, r2h
601
        set_ccr_zero
602
        bclr    r2h, @er1
603
        test_cc_clear
604
        mov     @er1, r2l
605
        test_h_gr8 15 r2l
606
 
607
        mov     #3, r2h
608
        set_ccr_zero
609
        bclr    r2h, @er1
610
        test_cc_clear
611
        mov     @er1, r2l
612
        test_h_gr8 7  r2l
613
 
614
        mov     #2, r2h
615
        set_ccr_zero
616
        bclr    r2h, @er1
617
        test_cc_clear
618
        mov     @er1, r2l
619
        test_h_gr8 3  r2l
620
 
621
        mov     #1, r2h
622
        set_ccr_zero
623
        bclr    r2h, @er1
624
        test_cc_clear
625
        mov     @er1, r2l
626
        test_h_gr8 1  r2l
627
 
628
        mov     #0, r2h
629
        set_ccr_zero
630
        bclr    r2h, @er1
631
        test_cc_clear
632
        mov     @er1, r2l
633
        test_h_gr8 0  r2l
634
 
635
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
636
.if (sim_cpu == h8300)
637
        test_h_gr16  byte_dst r1
638
        test_h_gr16  0x0000   r2
639
.else
640
        test_h_gr32  byte_dst   er1
641
        test_h_gr32  0xa5a50000 er2
642
.endif
643
        test_gr_a5a5 3
644
        test_gr_a5a5 4
645
        test_gr_a5a5 5
646
        test_gr_a5a5 6
647
        test_gr_a5a5 7
648
 
649
.if (sim_cpu > h8300h)
650
bset_rs8_abs32:
651
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
652
 
653
        ;;  bset rs8, @aa:32
654
        mov     #0, r2h
655
        set_ccr_zero
656
        bset    r2h, @byte_dst:32
657
        test_cc_clear
658
        mov     @byte_dst, r2l
659
        test_h_gr8 1 r2l
660
 
661
        mov     #1, r2h
662
        set_ccr_zero
663
        bset    r2h, @byte_dst:32
664
        test_cc_clear
665
        mov     @byte_dst, r2l
666
        test_h_gr8 3 r2l
667
 
668
        mov     #2, r2h
669
        set_ccr_zero
670
        bset    r2h, @byte_dst:32
671
        test_cc_clear
672
        mov     @byte_dst, r2l
673
        test_h_gr8 7 r2l
674
 
675
        mov     #3, r2h
676
        set_ccr_zero
677
        bset    r2h, @byte_dst:32
678
        test_cc_clear
679
        mov     @byte_dst, r2l
680
        test_h_gr8 15 r2l
681
 
682
        mov     #4, r2h
683
        set_ccr_zero
684
        bset    r2h, @byte_dst:32
685
        test_cc_clear
686
        mov     @byte_dst, r2l
687
        test_h_gr8 31 r2l
688
 
689
        mov     #5, r2h
690
        set_ccr_zero
691
        bset    r2h, @byte_dst:32
692
        test_cc_clear
693
        mov     @byte_dst, r2l
694
        test_h_gr8 63 r2l
695
 
696
        mov     #6, r2h
697
        set_ccr_zero
698
        bset    r2h, @byte_dst:32
699
        test_cc_clear
700
        mov     @byte_dst, r2l
701
        test_h_gr8 127 r2l
702
 
703
        mov     #7, r2h
704
        set_ccr_zero
705
        bset    r2h, @byte_dst:32
706
        test_cc_clear
707
        mov     @byte_dst, r2l
708
        test_h_gr8 255 r2l
709
 
710
.if (sim_cpu == h8300)
711
        test_h_gr16  0x07ff r2
712
.else
713
        test_h_gr32  0xa5a507ff er2
714
.endif
715
 
716
bclr_rs8_abs32:
717
        mov     #7, r2h
718
        set_ccr_zero
719
        bclr    r2h, @byte_dst:32
720
        test_cc_clear
721
        mov     @byte_dst, r2l
722
        test_h_gr8 127 r2l
723
 
724
        mov     #6, r2h
725
        set_ccr_zero
726
        bclr    r2h, @byte_dst:32
727
        test_cc_clear
728
        mov     @byte_dst, r2l
729
        test_h_gr8 63 r2l
730
 
731
        mov     #5, r2h
732
        set_ccr_zero
733
        bclr    r2h, @byte_dst:32
734
        test_cc_clear
735
        mov     @byte_dst, r2l
736
        test_h_gr8 31 r2l
737
 
738
        mov     #4, r2h
739
        set_ccr_zero
740
        bclr    r2h, @byte_dst:32
741
        test_cc_clear
742
        mov     @byte_dst, r2l
743
        test_h_gr8 15 r2l
744
 
745
        mov     #3, r2h
746
        set_ccr_zero
747
        bclr    r2h, @byte_dst:32
748
        test_cc_clear
749
        mov     @byte_dst, r2l
750
        test_h_gr8 7  r2l
751
 
752
        mov     #2, r2h
753
        set_ccr_zero
754
        bclr    r2h, @byte_dst:32
755
        test_cc_clear
756
        mov     @byte_dst, r2l
757
        test_h_gr8 3  r2l
758
 
759
        mov     #1, r2h
760
        set_ccr_zero
761
        bclr    r2h, @byte_dst:32
762
        test_cc_clear
763
        mov     @byte_dst, r2l
764
        test_h_gr8 1  r2l
765
 
766
        mov     #0, r2h
767
        set_ccr_zero
768
        bclr    r2h, @byte_dst:32
769
        test_cc_clear
770
        mov     @byte_dst, r2l
771
        test_h_gr8 0  r2l
772
 
773
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
774
        test_gr_a5a5 1
775
.if (sim_cpu == h8300)
776
        test_h_gr16  0x0000   r2
777
.else
778
        test_h_gr32  0xa5a50000 er2
779
.endif
780
        test_gr_a5a5 3
781
        test_gr_a5a5 4
782
        test_gr_a5a5 5
783
        test_gr_a5a5 6
784
        test_gr_a5a5 7
785
.endif
786
.endif
787
 
788
.if (sim_cpu == h8sx)
789
bset_eq_imm3_abs16:
790
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
791
 
792
        ;;  bset/eq xx:3, rd8
793
        mov     #0, @byte_dst
794
        set_ccr_zero
795
        bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect.
796
        test_cc_clear
797
        mov     @byte_dst, r1l
798
        test_h_gr8 0 r1l
799
 
800
        set_ccr_zero
801
        orc     #4, ccr         ; Set zero flag
802
        bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed.
803
 
804
        test_neg_clear
805
        test_zero_set
806
        test_ovf_clear
807
        test_carry_clear
808
 
809
        mov     @byte_dst, r1l
810
        test_h_gr8 1 r1l
811
 
812
bclr_eq_imm3_abs32:
813
        mov     #1, @byte_dst
814
        set_ccr_zero
815
        bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect.
816
        test_cc_clear
817
        mov     @byte_dst, r1l
818
        test_h_gr8 1 r1l
819
 
820
        set_ccr_zero
821
        orc     #4, ccr         ; Set zero flag
822
        bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed.
823
        test_neg_clear
824
        test_zero_set
825
        test_ovf_clear
826
        test_carry_clear
827
        mov     @byte_dst, r1l
828
        test_h_gr8 0 r1l
829
 
830
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
831
        test_h_gr32  0xa5a5a500 er1
832
        test_gr_a5a5 2
833
        test_gr_a5a5 3
834
        test_gr_a5a5 4
835
        test_gr_a5a5 5
836
        test_gr_a5a5 6
837
        test_gr_a5a5 7
838
 
839
bset_ne_imm3_abs16:
840
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
841
 
842
        ;;  bset/ne xx:3, aa:16
843
        mov     #0, @byte_dst
844
        set_ccr_zero
845
        orc     #4, ccr         ; Set zero flag
846
        bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect.
847
        test_zero_set
848
        test_neg_clear
849
        test_ovf_clear
850
        test_carry_clear
851
        mov     @byte_dst, r1l
852
        test_h_gr8 0 r1l
853
 
854
        set_ccr_zero
855
        bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed.
856
        test_cc_clear
857
        mov     @byte_dst, r1l
858
        test_h_gr8 1 r1l
859
 
860
bclr_ne_imm3_abs32:
861
        mov     #1, @byte_dst
862
        set_ccr_zero
863
        orc     #4, ccr         ; Set zero flag
864
        ;; bclr/ne xx:3, aa:16
865
        bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect.
866
        test_neg_clear
867
        test_zero_set
868
        test_ovf_clear
869
        test_carry_clear
870
        mov     @byte_dst, r1l
871
        test_h_gr8 1 r1l
872
 
873
        set_ccr_zero
874
        bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed.
875
        test_cc_clear
876
        mov     @byte_dst, r1l
877
        test_h_gr8 0 r1l
878
 
879
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
880
        test_h_gr32  0xa5a5a500 er1
881
        test_gr_a5a5 2
882
        test_gr_a5a5 3
883
        test_gr_a5a5 4
884
        test_gr_a5a5 5
885
        test_gr_a5a5 6
886
        test_gr_a5a5 7
887
.endif
888
 
889
        pass
890
        exit 0

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