URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [jmp.s] - Blame information for rev 157

Go to most recent revision | Details | Compare with Previous | View Log


# Hitachi H8 testcase 'jmp'
# mach(): all
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        .data
vector_area:
        .fill   0x400, 1, 0
 
        start
 
.if (sim_cpu == h8sx)
jmp_8:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        mov.l   #.Ltgt_8:32, @0x20
        set_ccr_zero
        ;;  jmp @@aa:8          ; 8-bit displacement
        jmp @@0x20
        fail
 
.Ltgt_8:
        test_cc_clear
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
jmp_7:                          ; vector jump
        mov.l   #vector_area, er0
        ldc.l   er0, vbr
        set_grs_a5a5
        mov.l   #.Ltgt_7:32, @vector_area+0x300
        set_ccr_zero
 
        jmp     @@0x300
        fail
.Ltgt_7:
        test_cc_clear
        test_grs_a5a5
        stc.l   vbr, er0
        test_h_gr32 vector_area, er0
 
.endif                          ; h8sx
 
jmp_24:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  jmp @aa:24          ; 24-bit address
        jmp @.Ltgt_24:24
        fail
 
.Ltgt_24:
        test_cc_clear
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu)                   ; Non-zero means h8300h, h8300s, or h8sx
jmp_reg:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  jmp @ern            ; register indirect
        mov.l   #.Ltgt_reg, er5
        jmp     @er5
        fail
 
.Ltgt_reg:
        test_cc_clear
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_h_gr32 .Ltgt_reg er5
        test_gr_a5a5 6
        test_gr_a5a5 7
.endif                          ; not h8300
 
.if (sim_cpu == h8sx)
jmp_32:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  jmp @aa:32          ; 32-bit address
;       jmp @.Ltgt_32:32        ; NOTE: hard-coded to avoid relaxing
        .word   0x5908
        .long   .Ltgt_32
        fail
 
.Ltgt_32:
        test_cc_clear
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
.endif                          ; h8sx
 
        pass
        exit 0
 
 

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Hitachi H8 testcase 'jmp'`
2			`# mach(): all`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`.data`
14			`vector_area:`
15			`.fill 0x400, 1, 0`
16
17			`start`
18
19			`.if (sim_cpu == h8sx)`
20			`jmp_8:`
21			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
22			`mov.l #.Ltgt_8:32, @0x20`
23			`set_ccr_zero`
24			`;; jmp @@aa:8 ; 8-bit displacement`
25			`jmp @@0x20`
26			`fail`
27
28			`.Ltgt_8:`
29			`test_cc_clear`
30			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
31			`test_gr_a5a5 1`
32			`test_gr_a5a5 2`
33			`test_gr_a5a5 3`
34			`test_gr_a5a5 4`
35			`test_gr_a5a5 5`
36			`test_gr_a5a5 6`
37			`test_gr_a5a5 7`
38
39			`jmp_7: ; vector jump`
40			`mov.l #vector_area, er0`
41			`ldc.l er0, vbr`
42			`set_grs_a5a5`
43			`mov.l #.Ltgt_7:32, @vector_area+0x300`
44			`set_ccr_zero`
45
46			`jmp @@0x300`
47			`fail`
48			`.Ltgt_7:`
49			`test_cc_clear`
50			`test_grs_a5a5`
51			`stc.l vbr, er0`
52			`test_h_gr32 vector_area, er0`
53
54			`.endif ; h8sx`
55
56			`jmp_24:`
57			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
58			`set_ccr_zero`
59
60			`;; jmp @aa:24 ; 24-bit address`
61			`jmp @.Ltgt_24:24`
62			`fail`
63
64			`.Ltgt_24:`
65			`test_cc_clear`
66			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
67			`test_gr_a5a5 1`
68			`test_gr_a5a5 2`
69			`test_gr_a5a5 3`
70			`test_gr_a5a5 4`
71			`test_gr_a5a5 5`
72			`test_gr_a5a5 6`
73			`test_gr_a5a5 7`
74
75			`.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx`
76			`jmp_reg:`
77			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
78			`set_ccr_zero`
79
80			`;; jmp @ern ; register indirect`
81			`mov.l #.Ltgt_reg, er5`
82			`jmp @er5`
83			`fail`
84
85			`.Ltgt_reg:`
86			`test_cc_clear`
87			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
88			`test_gr_a5a5 1`
89			`test_gr_a5a5 2`
90			`test_gr_a5a5 3`
91			`test_gr_a5a5 4`
92			`test_h_gr32 .Ltgt_reg er5`
93			`test_gr_a5a5 6`
94			`test_gr_a5a5 7`
95			`.endif ; not h8300`
96
97			`.if (sim_cpu == h8sx)`
98			`jmp_32:`
99			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
100			`set_ccr_zero`
101
102			`;; jmp @aa:32 ; 32-bit address`
103			`; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing`
104			`.word 0x5908`
105			`.long .Ltgt_32`
106			`fail`
107
108			`.Ltgt_32:`
109			`test_cc_clear`
110			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
111			`test_gr_a5a5 1`
112			`test_gr_a5a5 2`
113			`test_gr_a5a5 3`
114			`test_gr_a5a5 4`
115			`test_gr_a5a5 5`
116			`test_gr_a5a5 6`
117			`test_gr_a5a5 7`
118			`.endif ; h8sx`
119
120			`pass`
121			`exit 0`
122
123

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [jmp.s] - Blame information for rev 157