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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [shal.s] - Blame information for rev 840

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Line No. Rev Author Line
1 24 jeremybenn 
# Hitachi H8 testcase 'shal'
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# mach(): all
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# as(h8300):    --defsym sim_cpu=0
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# as(h8300h):   --defsym sim_cpu=1
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# as(h8300s):   --defsym sim_cpu=2
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# as(h8sx):     --defsym sim_cpu=3
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# ld(h8300h):   -m h8300helf
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# ld(h8300s):   -m h8300self
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# ld(h8sx):     -m h8300sxelf
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        .include "testutils.inc"
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        start
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        .data
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byte_dest:      .byte   0xa5
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        .align 2
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word_dest:      .word   0xa5a5
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        .align 4
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long_dest:      .long   0xa5a5a5a5
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        .text
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shal_b_reg8_1:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        shal.b  r0l             ; shift left arithmetic by one
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;;;     .word   0x1088
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        test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
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        test_zero_clear
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;       test_ovf_clear          ; FIXME
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        test_neg_clear
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        test_h_gr16 0xa54a r0   ; 1010 0101 -> 0100 1010
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.if (sim_cpu)
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        test_h_gr32 0xa5a5a54a er0
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.endif
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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shal_b_reg8_2:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        shal.b  #2, r0l         ; shift left arithmetic by two
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;;;     .word   0x10c8
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        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_zero_clear
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;       test_ovf_clear          ; FIXME
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        test_neg_set
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        test_h_gr16 0xa594 r0   ; 1010 0101 -> 1001 0100
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.if (sim_cpu)
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        test_h_gr32 0xa5a5a594 er0
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.endif
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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.if (sim_cpu)                   ; Not available in h8300 mode
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shal_w_reg16_1:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        shal.w  r0              ; shift left arithmetic by one
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;;;     .word   0x1090
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        test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
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        test_zero_clear
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;       test_ovf_clear          ; FIXME
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        test_neg_clear
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        test_h_gr16 0x4b4a r0   ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
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        test_h_gr32 0xa5a54b4a er0
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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shal_w_reg16_2:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        shal.w  #2, r0          ; shift left arithmetic by two
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;;;     .word   0x10d0
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        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_zero_clear
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;       test_ovf_clear          ; FIXME
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        test_neg_set
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        test_h_gr16 0x9694 r0   ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
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        test_h_gr32 0xa5a59694 er0
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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shal_l_reg32_1:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        shal.l  er0             ; shift left arithmetic by one
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;;;     .word   10b0
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        test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
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        test_zero_clear
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;       test_ovf_clear          ; FIXME
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        test_neg_clear
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        ; 1010 0101 1010 0101 1010 0101 1010 0101
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        ; -> 0100 1011 0100 1011 0100 1011 0100 1010
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        test_h_gr32 0x4b4b4b4a er0
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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shal_l_reg32_2:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        shal.l  #2, er0         ; shift left arithmetic by two
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;;;     .word   0x10f0
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        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_zero_clear
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;       test_ovf_clear          ; FIXME
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        test_neg_set
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        ; 1010 0101 1010 0101 1010 0101 1010 0101
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        ; -> 1001 0110 1001 0110 1001 0110 1001 0100
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        test_h_gr32 0x96969694 er0
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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.endif
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        pass
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        exit 0
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