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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [stc.s] - Blame information for rev 827

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Line No. Rev Author Line
1 24 jeremybenn
# Hitachi H8 testcase 'stc'
2
# mach(): all
3
# as(h8300):    --defsym sim_cpu=0
4
# as(h8300h):   --defsym sim_cpu=1
5
# as(h8300s):   --defsym sim_cpu=2
6
# as(h8sx):     --defsym sim_cpu=3
7
# ld(h8300h):   -m h8300helf
8
# ld(h8300s):   -m h8300self
9
# ld(h8sx):     -m h8300sxelf
10
 
11
        .include "testutils.inc"
12
        .data
13
byte_dest1:
14
        .byte   0
15
        .byte   0
16
byte_dest2:
17
        .byte   0
18
        .byte   0
19
byte_dest3:
20
        .byte   0
21
        .byte   0
22
byte_dest4:
23
        .byte   0
24
        .byte   0
25
byte_dest5:
26
        .byte   0
27
        .byte   0
28
byte_dest6:
29
        .byte   0
30
        .byte   0
31
byte_dest7:
32
        .byte   0
33
        .byte   0
34
byte_dest8:
35
        .byte   0
36
        .byte   0
37
byte_dest9:
38
        .byte   0
39
        .byte   0
40
byte_dest10:
41
        .byte   0
42
        .byte   0
43
byte_dest11:
44
        .byte   0
45
        .byte   0
46
byte_dest12:
47
        .byte   0
48
        .byte   0
49
 
50
        start
51
 
52
stc_ccr_reg8:
53
        set_grs_a5a5
54
        set_ccr_zero
55
 
56
        ldc     #0xff, ccr      ; test value
57
        stc     ccr, r0h        ; copy test value to r0h
58
 
59
        test_h_gr16  0xffa5 r0  ; ff in r0h, a5 in r0l
60
.if (sim_cpu)                   ; h/s/sx
61
        test_h_gr32  0xa5a5ffa5 er0     ; ff in r0h, a5 everywhere else
62
.endif
63
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
64
        test_gr_a5a5 2
65
        test_gr_a5a5 3
66
        test_gr_a5a5 4
67
        test_gr_a5a5 5
68
        test_gr_a5a5 6
69
        test_gr_a5a5 7
70
 
71
.if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
72
stc_exr_reg8:
73
        set_grs_a5a5
74
        set_ccr_zero
75
 
76
        ldc     #0x87, exr      ; set exr to 0x87
77
        stc     exr, r0l        ; retrieve and check exr value
78
        cmp.b   #0x87, r0l
79
        beq     .L21
80
        fail
81
.L21:
82
        test_h_gr32  0xa5a5a587 er0     ; Register 0 modified by test procedure.
83
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
84
        test_gr_a5a5 2
85
        test_gr_a5a5 3
86
        test_gr_a5a5 4
87
        test_gr_a5a5 5
88
        test_gr_a5a5 6
89
        test_gr_a5a5 7
90
 
91
stc_ccr_abs16:
92
        set_grs_a5a5
93
        set_ccr_zero
94
 
95
        ldc     #0xff, ccr
96
        stc     ccr, @byte_dest1:16     ; abs16 dest
97
 
98
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
99
        test_gr_a5a5 1
100
        test_gr_a5a5 2
101
        test_gr_a5a5 3
102
        test_gr_a5a5 4
103
        test_gr_a5a5 5
104
        test_gr_a5a5 6
105
        test_gr_a5a5 7
106
 
107
stc_exr_abs16:
108
        set_grs_a5a5
109
        set_ccr_zero
110
 
111
        ldc     #0x87, exr
112
        stc     exr, @byte_dest2:16     ; abs16 dest
113
 
114
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
115
        test_gr_a5a5 1
116
        test_gr_a5a5 2
117
        test_gr_a5a5 3
118
        test_gr_a5a5 4
119
        test_gr_a5a5 5
120
        test_gr_a5a5 6
121
        test_gr_a5a5 7
122
 
123
stc_ccr_abs32:
124
        set_grs_a5a5
125
        set_ccr_zero
126
 
127
        ldc     #0xff, ccr
128
        stc     ccr, @byte_dest3:32     ; abs32 dest
129
 
130
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
131
        test_gr_a5a5 1
132
        test_gr_a5a5 2
133
        test_gr_a5a5 3
134
        test_gr_a5a5 4
135
        test_gr_a5a5 5
136
        test_gr_a5a5 6
137
        test_gr_a5a5 7
138
 
139
stc_exr_abs32:
140
        set_grs_a5a5
141
        set_ccr_zero
142
 
143
        ldc     #0x87, exr
144
        stc     exr, @byte_dest4:32     ; abs32 dest
145
 
146
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
147
        test_gr_a5a5 1
148
        test_gr_a5a5 2
149
        test_gr_a5a5 3
150
        test_gr_a5a5 4
151
        test_gr_a5a5 5
152
        test_gr_a5a5 6
153
        test_gr_a5a5 7
154
 
155
stc_ccr_disp16:
156
        set_grs_a5a5
157
        set_ccr_zero
158
 
159
        mov     #byte_dest5-1, er1
160
        ldc     #0xff, ccr
161
        stc     ccr, @(1:16,er1)        ; disp16 dest (5)
162
 
163
        test_h_gr32 byte_dest5-1, er1   ; er1 still contains address
164
 
165
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
166
        test_gr_a5a5 2
167
        test_gr_a5a5 3
168
        test_gr_a5a5 4
169
        test_gr_a5a5 5
170
        test_gr_a5a5 6
171
        test_gr_a5a5 7
172
 
173
stc_exr_disp16:
174
        set_grs_a5a5
175
        set_ccr_zero
176
 
177
        mov     #byte_dest6+1, er1
178
        ldc     #0x87, exr
179
        stc     exr, @(-1:16,er1)       ; disp16 dest (6)
180
 
181
        test_h_gr32 byte_dest6+1, er1   ; er1 still contains address
182
 
183
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
184
        test_gr_a5a5 2
185
        test_gr_a5a5 3
186
        test_gr_a5a5 4
187
        test_gr_a5a5 5
188
        test_gr_a5a5 6
189
        test_gr_a5a5 7
190
 
191
stc_ccr_disp32:
192
        set_grs_a5a5
193
        set_ccr_zero
194
 
195
        mov     #byte_dest7-1, er1
196
        ldc     #0xff, ccr
197
        stc     ccr, @(1:32,er1)        ; disp32 dest (7)
198
 
199
        test_h_gr32 byte_dest7-1, er1   ; er1 still contains address
200
 
201
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
202
        test_gr_a5a5 2
203
        test_gr_a5a5 3
204
        test_gr_a5a5 4
205
        test_gr_a5a5 5
206
        test_gr_a5a5 6
207
        test_gr_a5a5 7
208
 
209
stc_exr_disp32:
210
        set_grs_a5a5
211
        set_ccr_zero
212
 
213
        mov     #byte_dest8+1, er1
214
        ldc     #0x87, exr
215
        stc     exr, @(-1:32,er1)       ; disp16 dest (8)
216
 
217
        test_h_gr32 byte_dest8+1, er1   ; er1 still contains address
218
 
219
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
220
        test_gr_a5a5 3
221
        test_gr_a5a5 4
222
        test_gr_a5a5 5
223
        test_gr_a5a5 6
224
        test_gr_a5a5 7
225
 
226
stc_ccr_predecr:
227
        set_grs_a5a5
228
        set_ccr_zero
229
 
230
        mov     #byte_dest9+2, er1
231
        ldc     #0xff, ccr
232
        stc     ccr, @-er1      ; predecr dest (9)
233
 
234
        test_h_gr32  byte_dest9 er1     ; er1 still contains address
235
 
236
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
237
        test_gr_a5a5 2
238
        test_gr_a5a5 3
239
        test_gr_a5a5 4
240
        test_gr_a5a5 5
241
        test_gr_a5a5 6
242
        test_gr_a5a5 7
243
 
244
stc_exr_predecr:
245
        set_grs_a5a5
246
        set_ccr_zero
247
 
248
        mov     #byte_dest10+2, er1
249
        ldc     #0x87, exr
250
        stc     exr, @-er1      ; predecr dest (10)
251
 
252
        test_h_gr32 byte_dest10, er1    ; er1 still contains address
253
 
254
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
255
        test_gr_a5a5 2
256
        test_gr_a5a5 3
257
        test_gr_a5a5 4
258
        test_gr_a5a5 5
259
        test_gr_a5a5 6
260
        test_gr_a5a5 7
261
 
262
stc_ccr_ind:
263
        set_grs_a5a5
264
        set_ccr_zero
265
 
266
        mov     #byte_dest11, er1
267
        ldc     #0xff, ccr
268
        stc     ccr, @er1       ; postinc dest (11)
269
 
270
        test_h_gr32 byte_dest11, er1    ; er1 still contains address
271
 
272
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
273
        test_gr_a5a5 2
274
        test_gr_a5a5 3
275
        test_gr_a5a5 4
276
        test_gr_a5a5 5
277
        test_gr_a5a5 6
278
        test_gr_a5a5 7
279
 
280
stc_exr_ind:
281
        set_grs_a5a5
282
        set_ccr_zero
283
 
284
        mov     #byte_dest12, er1
285
        ldc     #0x87, exr
286
        stc     exr, @er1, exr  ; postinc dest (12)
287
 
288
        test_h_gr32 byte_dest12, er1    ; er1 still contains address
289
 
290
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
291
        test_gr_a5a5 2
292
        test_gr_a5a5 3
293
        test_gr_a5a5 4
294
        test_gr_a5a5 5
295
        test_gr_a5a5 6
296
        test_gr_a5a5 7
297
 
298
.endif
299
 
300
.if (sim_cpu == h8sx)           ; New vbr and sbr registers for h8sx
301
stc_sbr_reg:
302
        set_grs_a5a5
303
        set_ccr_zero
304
 
305
        mov     #0xaaaaaaaa, er0
306
        ldc     er0, sbr        ; set sbr to 0xaaaaaaaa
307
        stc     sbr, er1        ; retreive and check sbr value
308
 
309
        test_h_gr32 0xaaaaaaaa er1
310
        test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
311
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
312
        test_gr_a5a5 3
313
        test_gr_a5a5 4
314
        test_gr_a5a5 5
315
        test_gr_a5a5 6
316
        test_gr_a5a5 7
317
 
318
stc_vbr_reg:
319
        set_grs_a5a5
320
        set_ccr_zero
321
 
322
        mov     #0xaaaaaaaa, er0
323
        ldc     er0, vbr        ; set sbr to 0xaaaaaaaa
324
        stc     vbr, er1        ; retreive and check sbr value
325
 
326
        test_h_gr32 0xaaaaaaaa er1
327
        test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
328
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
329
        test_gr_a5a5 3
330
        test_gr_a5a5 4
331
        test_gr_a5a5 5
332
        test_gr_a5a5 6
333
        test_gr_a5a5 7
334
 
335
check_results:
336
        ;; Now check results
337
        mov @byte_dest1, r0h
338
        cmp.b   #0xff, r0h
339
        beq .L1
340
        fail
341
 
342
.L1:    mov @byte_dest2, r0h
343
        cmp.b   #0x87, r0h
344
        beq .L2
345
        fail
346
 
347
.L2:    mov @byte_dest3, r0h
348
        cmp.b   #0xff, r0h
349
        beq .L3
350
        fail
351
 
352
.L3:    mov @byte_dest4, r0h
353
        cmp.b   #0x87, r0h
354
        beq .L4
355
        fail
356
 
357
.L4:    mov @byte_dest5, r0h
358
        cmp.b   #0xff, r0h
359
        beq .L5
360
        fail
361
 
362
.L5:    mov @byte_dest6, r0h
363
        cmp.b   #0x87, r0h
364
        beq .L6
365
        fail
366
 
367
.L6:    mov @byte_dest7, r0h
368
        cmp.b   #0xff, r0h
369
        beq .L7
370
        fail
371
 
372
.L7:    mov @byte_dest8, r0h
373
        cmp.b   #0x87, r0h
374
        beq .L8
375
        fail
376
 
377
.L8:    mov @byte_dest9, r0h
378
        cmp.b   #0xff, r0h
379
        beq .L9
380
        fail
381
 
382
.L9:    mov @byte_dest10, r0h
383
        cmp.b   #0x87, r0h
384
        beq .L10
385
        fail
386
 
387
.L10:   mov @byte_dest11, r0h
388
        cmp.b   #0xff, r0h
389
        beq .L11
390
        fail
391
 
392
.L11:   mov @byte_dest12, r0h
393
        cmp.b   #0x87, r0h
394
        beq .L12
395
        fail
396
 
397
.L12:
398
.endif
399
        pass
400
 
401
        exit 0

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