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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [subb.s] - Blame information for rev 856

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Line No. Rev Author Line
1 24 jeremybenn
# Hitachi H8 testcase 'sub.b'
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# mach(): all
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# as(h8300):    --defsym sim_cpu=0
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# as(h8300h):   --defsym sim_cpu=1
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# as(h8300s):   --defsym sim_cpu=2
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# as(h8sx):     --defsym sim_cpu=3
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# ld(h8300h):   -m h8300helf
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# ld(h8300s):   -m h8300self
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# ld(h8sx):     -m h8300sxelf
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        .include "testutils.inc"
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        # Instructions tested:
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        # sub.b #xx:8, rd       ; <illegal>
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        # sub.b #xx:8, @erd     ;         7 d rd ???? a ???? xxxxxxxx
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        # sub.b #xx:8, @erd+    ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
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        # sub.b #xx:8, @erd-    ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
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        # sub.b rs, rd          ;                     1 8 rs rd
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        # sub.b reg8, @erd      ;         7 d rd ???? 1 8 rs ????
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        # sub.b reg8, @erd+     ;         0 1 7     9 8 rd 3 rs
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        # sub.b reg8, @erd-     ;         0 1 7     9 a rd 3 rs
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        #
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        # Coming soon:
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        # sub.b #xx:8, @+erd    ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
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        # sub.b #xx:8, @-erd    ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
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        # sub.b reg8, @+erd     ;         0 1 7     9 9 rd 3 rs
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        # sub.b reg8, @-erd     ;         0 1 7     9 b rd 3 rs
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        # ...
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.data
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pre_byte:       .byte 0
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byte_dest:      .byte 0xa5
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post_byte:      .byte 0
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        start
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.if (0)                          ; Guess what?  Sub.b immediate reg8 is illegal!
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sub_b_imm8_reg:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        ;;  fixme set ccr
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43
        ;;  sub.b #xx:8,Rd
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        sub.b   #5, r0l         ; Immediate 8-bit operand
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46
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
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        test_h_gr16 0xa5a0 r0   ; sub result:   a5 - 5
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.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
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        test_h_gr32 0xa5a5a5a0 er0      ; sub result:    a5 - 5
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.endif
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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.endif
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.if (sim_cpu == h8sx)
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sub_b_imm8_rdind:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        ;;  sub.b #xx:8,@eRd
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        mov     #byte_dest, er0
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        sub.b   #5:8, @er0      ; Immediate 8-bit src, reg indirect dst
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;;;     .word   0x7d00
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;;;     .word   0xa105
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71
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_ovf_clear
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        test_zero_clear
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        test_neg_set
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76
        test_h_gr32 byte_dest, er0      ; er0 still contains address
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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        ;; Now check the result of the sub to memory.
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        sub.b   r0l, r0l
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        mov.b   @byte_dest, r0l
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        cmp.b   #0xa0, r0l
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        beq     .L1
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        fail
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.L1:
92
 
93
sub_b_imm8_rdpostinc:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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97
        ;;  sub.b #xx:8,@eRd+
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        mov     #byte_dest, er0
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        sub.b   #5:8, @er0+     ; Immediate 8-bit src, reg post-incr dest
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;;;     .word   0x0174
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;;;     .word   0x6c08
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;;;     .word   0xa105
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        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_ovf_clear
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        test_zero_clear
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        test_neg_set
108
 
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        test_h_gr32 post_byte, er0      ; er0 still contains address plus one
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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118
        ;; Now check the result of the sub to memory.
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        sub.b   r0l, r0l
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        mov.b   @byte_dest, r0l
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        cmp.b   #0x9b, r0l
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        beq     .L2
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        fail
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.L2:
125
 
126
sub_b_imm8_rdpostdec:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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130
        ;;  sub.b #xx:8,@eRd-
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        mov     #byte_dest, er0
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        sub.b   #5:8, @er0-     ; Immediate 8-bit src, reg post-decr dest
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;;;     .word   0x0176
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;;;     .word   0x6c08
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;;;     .word   0xa105
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137
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_ovf_clear
139
        test_zero_clear
140
        test_neg_set
141
 
142
        test_h_gr32 pre_byte, er0       ; er0 still contains address minus one
143
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
144
        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
148
        test_gr_a5a5 6
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        test_gr_a5a5 7
150
 
151
        ;; Now check the result of the sub to memory.
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        sub.b   r0l, r0l
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        mov.b   @byte_dest, r0l
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        cmp.b   #0x96, r0l
155
        beq     .L3
156
        fail
157
.L3:
158
 
159
.endif
160
 
161
sub_b_reg8_reg8:
162
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        ;;  fixme set ccr
164
 
165
        ;;  sub.b Rs,Rd
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        mov.b   #5, r0h
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        sub.b   r0h, r0l        ; Register operand
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169
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
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        test_h_gr16 0x05a0 r0   ; sub result:   a5 - 5
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.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
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        test_h_gr32 0xa5a505a0 er0      ; sub result:   a5 - 5
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.endif
174
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
177
        test_gr_a5a5 4
178
        test_gr_a5a5 5
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        test_gr_a5a5 6
180
        test_gr_a5a5 7
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182
.if (sim_cpu == h8sx)
183
sub_b_reg8_rdind:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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187
        ;;  sub.b rs8,@eRd      ; Subx to register indirect
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        mov     #byte_dest, er0
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        mov     #5, r1l
190
        sub.b   r1l, @er0       ; reg8 src, reg indirect dest
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;;;     .word   0x7d00
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;;;     .word   0x1890
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194
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
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        test_ovf_clear
196
        test_zero_clear
197
        test_neg_set
198
 
199
        test_h_gr32 byte_dest er0       ; er0 still contains address
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        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
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202
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
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        test_gr_a5a5 3
204
        test_gr_a5a5 4
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        test_gr_a5a5 5
206
        test_gr_a5a5 6
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        test_gr_a5a5 7
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209
        ;; Now check the result of the sub to memory.
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        sub.b   r0l, r0l
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        mov.b   @byte_dest, r0l
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        cmp.b   #0x91, r0l
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        beq     .L4
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        fail
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.L4:
216
 
217
sub_b_reg8_rdpostinc:
218
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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221
        ;;  sub.b rs8,@eRd+     ; Subx to register indirect
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        mov     #byte_dest, er0
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        mov     #5, r1l
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        sub.b   r1l, @er0+      ; reg8 src, reg indirect dest
225
;;;     .word   0x0179
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;;;     .word   0x8039
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228
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
229
        test_ovf_clear
230
        test_zero_clear
231
        test_neg_set
232
 
233
        test_h_gr32 post_byte er0       ; er0 still contains address plus one
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        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
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236
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
242
 
243
        ;; Now check the result of the sub to memory.
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        sub.b   r0l, r0l
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        mov.b   @byte_dest, r0l
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        cmp.b   #0x8c, r0l
247
        beq     .L5
248
        fail
249
.L5:
250
 
251
sub_b_reg8_rdpostdec:
252
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
253
        set_ccr_zero
254
 
255
        ;;  sub.b rs8,@eRd-     ; Subx to register indirect
256
        mov     #byte_dest, er0
257
        mov     #5, r1l
258
        sub.b   r1l, @er0-      ; reg8 src, reg indirect dest
259
;;;     .word   0x0179
260
;;;     .word   0xa039
261
 
262
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
263
        test_ovf_clear
264
        test_zero_clear
265
        test_neg_set
266
 
267
        test_h_gr32 pre_byte er0        ; er0 still contains address minus one
268
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
269
 
270
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
271
        test_gr_a5a5 3
272
        test_gr_a5a5 4
273
        test_gr_a5a5 5
274
        test_gr_a5a5 6
275
        test_gr_a5a5 7
276
 
277
        ;; Now check the result of the sub to memory.
278
        sub.b   r0l, r0l
279
        mov.b   @byte_dest, r0l
280
        cmp.b   #0x87, r0l
281
        beq     .L6
282
        fail
283
.L6:
284
 
285
.endif
286
 
287
        pass
288
 
289
        exit 0

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