URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [xorb.s] - Blame information for rev 840

Details | Compare with Previous | View Log


# Hitachi H8 testcase 'xor.b'
# mach(): all
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        # Instructions tested:
        # xor.b #xx:8, rd       ;                     d rd   xxxxxxxx
        # xor.b #xx:8, @erd     ;         7 d rd ???? d ???? xxxxxxxx
        # xor.b #xx:8, @erd+    ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx
        # xor.b #xx:8, @erd-    ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx
        # xor.b #xx:8, @+erd    ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx
        # xor.b #xx:8, @-erd    ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx
        # xor.b rs, rd          ;                     1 5 rs rd
        # xor.b reg8, @erd      ;         7 d rd ???? 1 5 rs ????
        # xor.b reg8, @erd+     ;         0 1 7     9 8 rd 5 rs
        # xor.b reg8, @erd-     ;         0 1 7     9 a rd 5 rs
        # xor.b reg8, @+erd     ;         0 1 7     9 9 rd 5 rs
        # xor.b reg8, @-erd     ;         0 1 7     9 b rd 5 rs
        #
        # xorc #xx:8, ccr       ; 
        # xorc #xx:8, exr       ; 
 
        # Coming soon:
        # ...
 
.data
pre_byte:       .byte 0
byte_dest:      .byte 0xa5
post_byte:      .byte 0
 
        start
 
xor_b_imm8_reg:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  xor.b #xx:8,Rd
        xor.b   #0xff, r0l      ; Immediate 8-bit operand
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr16 0xa55a r0   ; xor result:   a5 ^ ff
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
        test_h_gr32 0xa5a5a55a er0      ; xor result:    a5 ^ ff
.endif
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8sx)
xor_b_imm8_rdind:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xor.b #xx:8,@eRd
        mov     #byte_dest, er0
        xor.b   #0xff:8, @er0   ; Immediate 8-bit src, reg indirect dst
;;;     .word   0x7d00
;;;     .word   0xd0ff
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 byte_dest, er0      ; er0 still contains address
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the xor to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x5a, r0l
        beq     .L1
        fail
.L1:
 
xor_b_imm8_postinc:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xor.b #xx:8,@eRd+
        mov     #byte_dest, er0
        xor.b   #0xff:8, @er0+  ; Immediate 8-bit src, reg indirect dst
;;;     .word   0x0174
;;;     .word   0x6c08
;;;     .word   0xd0ff
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 post_byte, er0      ; er0 contains address plus one
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the xor to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa5, r0l
        beq     .L2
        fail
.L2:
 
xor_b_imm8_rdpostdec:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xor.b #xx:8,@eRd-
        mov     #byte_dest, er0
        xor.b   #0xff:8, @er0-  ; Immediate 8-bit src, reg indirect dst
;;;     .word   0x0176
;;;     .word   0x6c08
;;;     .word   0xd0ff
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 pre_byte, er0       ; er0 contains address minus one
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the xor to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x5a, r0l
        beq     .L3
        fail
.L3:
 
 
.endif
 
xor_b_reg8_reg8:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  xor.b Rs,Rd
        mov.b   #0xff, r0h
        xor.b   r0h, r0l        ; Register operand
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr16 0xff5a r0   ; xor result:   a5 ^ ff
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
        test_h_gr32 0xa5a5ff5a er0      ; xor result:   a5 ^ ff
.endif
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8sx)
xor_b_reg8_rdind:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xor.b rs8,@eRd      ; xor reg8 to register indirect
        mov     #byte_dest, er0
        mov     #0xff, r1l
        xor.b   r1l, @er0       ; reg8 src, reg indirect dest
;;;     .word   0x7d00
;;;     .word   0x1590
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 byte_dest er0       ; er0 still contains address
        test_h_gr32 0xa5a5a5ff er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the or to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa5, r0l
        beq     .L4
        fail
.L4:
 
xor_b_reg8_rdpostinc:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xor.b rs8,@eRd+     ; xor reg8 to register post-increment
        mov     #byte_dest, er0
        mov     #0xff, r1l
        xor.b   r1l, @er0+      ; reg8 src, reg post-increment dest
;;;     .word   0x0179
;;;     .word   0x8059
 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_clear
 
        test_h_gr32 post_byte er0       ; er0 contains address plus one
        test_h_gr32 0xa5a5a5ff er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the or to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0x5a, r0l
        beq     .L5
        fail
.L5:
 
xor_b_reg8_rdpostdec:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xor.b rs8,@eRd-     ; xor reg8 to register post-decrement
        mov     #byte_dest, er0
        mov     #0xff, r1l
        xor.b   r1l, @er0-      ; reg8 src, reg indirect dest
;;;     .word   0x0179
;;;     .word   0xa059
 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
        test_ovf_clear
        test_zero_clear
        test_neg_set
 
        test_h_gr32 pre_byte er0        ; er0 contains address minus one
        test_h_gr32 0xa5a5a5ff er1      ; er1 has the test load
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        ;; Now check the result of the or to memory.
        sub.b   r0l, r0l
        mov.b   @byte_dest, r0l
        cmp.b   #0xa5, r0l
        beq     .L6
        fail
.L6:
 
.endif                          ; h8sx
 
xorc_imm8_ccr:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        set_ccr_zero
 
        ;;  xorc #xx:8,ccr
 
        test_neg_clear
        xorc    #0x8, ccr       ; Immediate 8-bit operand (neg flag)
        test_neg_set
        xorc    #0x8, ccr
        test_neg_clear
 
        test_zero_clear
        xorc    #0x4, ccr       ; Immediate 8-bit operand (zero flag)
        test_zero_set
        xorc    #0x4, ccr
        test_zero_clear
 
        test_ovf_clear
        xorc    #0x2, ccr       ; Immediate 8-bit operand (overflow flag)
        test_ovf_set
        xorc    #0x2, ccr
        test_ovf_clear
 
        test_carry_clear
        xorc    #0x1, ccr       ; Immediate 8-bit operand (carry flag)
        test_carry_set
        xorc    #0x1, ccr
        test_carry_clear
 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
xorc_imm8_exr:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ldc     #0, exr
        stc     exr, r0l
        test_h_gr8 0, r0l
 
        set_ccr_zero
        ;;  xorc #xx:8,exr
 
        xorc    #0x80, exr
        test_cc_clear
        stc     exr, r0l
        test_h_gr8 0x80, r0l
        xorc    #0x80, exr
        stc     exr, r0l
        test_h_gr8 0, r0l
 
        xorc    #0x4, exr
        stc     exr, r0l
        test_h_gr8 4, r0l
        xorc    #0x4, exr
        stc     exr, r0l
        test_h_gr8 0, r0l
 
        xorc    #0x2, exr       ; Immediate 8-bit operand (overflow flag)
        stc     exr, r0l
        test_h_gr8 2, r0l
        xorc    #0x2, exr
        stc     exr, r0l
        test_h_gr8 0, r0l
 
        xorc    #0x1, exr       ; Immediate 8-bit operand (carry flag)
        stc     exr, r0l
        test_h_gr8 1, r0l
        xorc    #0x1, exr
        stc     exr, r0l
        test_h_gr8 0, r0l
 
        test_h_gr32  0xa5a5a500 er0
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
.endif                          ; not h8300 or h8300h
 
        pass
 
        exit 0

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [xorb.s] - Blame information for rev 840

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Hitachi H8 testcase 'xor.b'`
2			`# mach(): all`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`# Instructions tested:`
14			`# xor.b #xx:8, rd ; d rd xxxxxxxx`
15			`# xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx`
16			`# xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx`
17			`# xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx`
18			`# xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx`
19			`# xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx`
20			`# xor.b rs, rd ; 1 5 rs rd`
21			`# xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ????`
22			`# xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs`
23			`# xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs`
24			`# xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs`
25			`# xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs`
26			`#`
27			`# xorc #xx:8, ccr ;`
28			`# xorc #xx:8, exr ;`
29
30			`# Coming soon:`
31			`# ...`
32
33			`.data`
34			`pre_byte: .byte 0`
35			`byte_dest: .byte 0xa5`
36			`post_byte: .byte 0`
37
38			`start`
39
40			`xor_b_imm8_reg:`
41			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
42			`;; fixme set ccr`
43
44			`;; xor.b #xx:8,Rd`
45			`xor.b #0xff, r0l ; Immediate 8-bit operand`
46
47			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
48			`test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff`
49			`.if (sim_cpu) ; non-zero means h8300h, s, or sx`
50			`test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff`
51			`.endif`
52			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
53			`test_gr_a5a5 2`
54			`test_gr_a5a5 3`
55			`test_gr_a5a5 4`
56			`test_gr_a5a5 5`
57			`test_gr_a5a5 6`
58			`test_gr_a5a5 7`
59
60			`.if (sim_cpu == h8sx)`
61			`xor_b_imm8_rdind:`
62			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
63			`set_ccr_zero`
64
65			`;; xor.b #xx:8,@eRd`
66			`mov #byte_dest, er0`
67			`xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst`
68			`;;; .word 0x7d00`
69			`;;; .word 0xd0ff`
70
71			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
72			`test_ovf_clear`
73			`test_zero_clear`
74			`test_neg_clear`
75
76			`test_h_gr32 byte_dest, er0 ; er0 still contains address`
77			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
78			`test_gr_a5a5 2`
79			`test_gr_a5a5 3`
80			`test_gr_a5a5 4`
81			`test_gr_a5a5 5`
82			`test_gr_a5a5 6`
83			`test_gr_a5a5 7`
84
85			`;; Now check the result of the xor to memory.`
86			`sub.b r0l, r0l`
87			`mov.b @byte_dest, r0l`
88			`cmp.b #0x5a, r0l`
89			`beq .L1`
90			`fail`
91			`.L1:`
92
93			`xor_b_imm8_postinc:`
94			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
95			`set_ccr_zero`
96
97			`;; xor.b #xx:8,@eRd+`
98			`mov #byte_dest, er0`
99			`xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst`
100			`;;; .word 0x0174`
101			`;;; .word 0x6c08`
102			`;;; .word 0xd0ff`
103
104			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
105			`test_ovf_clear`
106			`test_zero_clear`
107			`test_neg_set`
108
109			`test_h_gr32 post_byte, er0 ; er0 contains address plus one`
110			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
111			`test_gr_a5a5 2`
112			`test_gr_a5a5 3`
113			`test_gr_a5a5 4`
114			`test_gr_a5a5 5`
115			`test_gr_a5a5 6`
116			`test_gr_a5a5 7`
117
118			`;; Now check the result of the xor to memory.`
119			`sub.b r0l, r0l`
120			`mov.b @byte_dest, r0l`
121			`cmp.b #0xa5, r0l`
122			`beq .L2`
123			`fail`
124			`.L2:`
125
126			`xor_b_imm8_rdpostdec:`
127			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
128			`set_ccr_zero`
129
130			`;; xor.b #xx:8,@eRd-`
131			`mov #byte_dest, er0`
132			`xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst`
133			`;;; .word 0x0176`
134			`;;; .word 0x6c08`
135			`;;; .word 0xd0ff`
136
137			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
138			`test_ovf_clear`
139			`test_zero_clear`
140			`test_neg_clear`
141
142			`test_h_gr32 pre_byte, er0 ; er0 contains address minus one`
143			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
144			`test_gr_a5a5 2`
145			`test_gr_a5a5 3`
146			`test_gr_a5a5 4`
147			`test_gr_a5a5 5`
148			`test_gr_a5a5 6`
149			`test_gr_a5a5 7`
150
151			`;; Now check the result of the xor to memory.`
152			`sub.b r0l, r0l`
153			`mov.b @byte_dest, r0l`
154			`cmp.b #0x5a, r0l`
155			`beq .L3`
156			`fail`
157			`.L3:`
158
159
160			`.endif`
161
162			`xor_b_reg8_reg8:`
163			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
164			`;; fixme set ccr`
165
166			`;; xor.b Rs,Rd`
167			`mov.b #0xff, r0h`
168			`xor.b r0h, r0l ; Register operand`
169
170			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
171			`test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff`
172			`.if (sim_cpu) ; non-zero means h8300h, s, or sx`
173			`test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff`
174			`.endif`
175			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
176			`test_gr_a5a5 2`
177			`test_gr_a5a5 3`
178			`test_gr_a5a5 4`
179			`test_gr_a5a5 5`
180			`test_gr_a5a5 6`
181			`test_gr_a5a5 7`
182
183			`.if (sim_cpu == h8sx)`
184			`xor_b_reg8_rdind:`
185			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
186			`set_ccr_zero`
187
188			`;; xor.b rs8,@eRd ; xor reg8 to register indirect`
189			`mov #byte_dest, er0`
190			`mov #0xff, r1l`
191			`xor.b r1l, @er0 ; reg8 src, reg indirect dest`
192			`;;; .word 0x7d00`
193			`;;; .word 0x1590`
194
195			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
196			`test_ovf_clear`
197			`test_zero_clear`
198			`test_neg_set`
199
200			`test_h_gr32 byte_dest er0 ; er0 still contains address`
201			`test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load`
202
203			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
204			`test_gr_a5a5 3`
205			`test_gr_a5a5 4`
206			`test_gr_a5a5 5`
207			`test_gr_a5a5 6`
208			`test_gr_a5a5 7`
209
210			`;; Now check the result of the or to memory.`
211			`sub.b r0l, r0l`
212			`mov.b @byte_dest, r0l`
213			`cmp.b #0xa5, r0l`
214			`beq .L4`
215			`fail`
216			`.L4:`
217
218			`xor_b_reg8_rdpostinc:`
219			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
220			`set_ccr_zero`
221
222			`;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment`
223			`mov #byte_dest, er0`
224			`mov #0xff, r1l`
225			`xor.b r1l, @er0+ ; reg8 src, reg post-increment dest`
226			`;;; .word 0x0179`
227			`;;; .word 0x8059`
228
229			`test_carry_clear ; H=0 N=0 Z=0 V=0 C=0`
230			`test_ovf_clear`
231			`test_zero_clear`
232			`test_neg_clear`
233
234			`test_h_gr32 post_byte er0 ; er0 contains address plus one`
235			`test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load`
236
237			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
238			`test_gr_a5a5 3`
239			`test_gr_a5a5 4`
240			`test_gr_a5a5 5`
241			`test_gr_a5a5 6`
242			`test_gr_a5a5 7`
243
244			`;; Now check the result of the or to memory.`
245			`sub.b r0l, r0l`
246			`mov.b @byte_dest, r0l`
247			`cmp.b #0x5a, r0l`
248			`beq .L5`
249			`fail`
250			`.L5:`
251
252			`xor_b_reg8_rdpostdec:`
253			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
254			`set_ccr_zero`
255
256			`;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement`
257			`mov #byte_dest, er0`
258			`mov #0xff, r1l`
259			`xor.b r1l, @er0- ; reg8 src, reg indirect dest`
260			`;;; .word 0x0179`
261			`;;; .word 0xa059`
262
263			`test_carry_clear ; H=0 N=1 Z=0 V=0 C=0`
264			`test_ovf_clear`
265			`test_zero_clear`
266			`test_neg_set`
267
268			`test_h_gr32 pre_byte er0 ; er0 contains address minus one`
269			`test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load`
270
271			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
272			`test_gr_a5a5 3`
273			`test_gr_a5a5 4`
274			`test_gr_a5a5 5`
275			`test_gr_a5a5 6`
276			`test_gr_a5a5 7`
277
278			`;; Now check the result of the or to memory.`
279			`sub.b r0l, r0l`
280			`mov.b @byte_dest, r0l`
281			`cmp.b #0xa5, r0l`
282			`beq .L6`
283			`fail`
284			`.L6:`
285
286			`.endif ; h8sx`
287
288			`xorc_imm8_ccr:`
289			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
290			`set_ccr_zero`
291
292			`;; xorc #xx:8,ccr`
293
294			`test_neg_clear`
295			`xorc #0x8, ccr ; Immediate 8-bit operand (neg flag)`
296			`test_neg_set`
297			`xorc #0x8, ccr`
298			`test_neg_clear`
299
300			`test_zero_clear`
301			`xorc #0x4, ccr ; Immediate 8-bit operand (zero flag)`
302			`test_zero_set`
303			`xorc #0x4, ccr`
304			`test_zero_clear`
305
306			`test_ovf_clear`
307			`xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag)`
308			`test_ovf_set`
309			`xorc #0x2, ccr`
310			`test_ovf_clear`
311
312			`test_carry_clear`
313			`xorc #0x1, ccr ; Immediate 8-bit operand (carry flag)`
314			`test_carry_set`
315			`xorc #0x1, ccr`
316			`test_carry_clear`
317
318			`test_gr_a5a5 0 ; Make sure other general regs not disturbed`
319			`test_gr_a5a5 1`
320			`test_gr_a5a5 2`
321			`test_gr_a5a5 3`
322			`test_gr_a5a5 4`
323			`test_gr_a5a5 5`
324			`test_gr_a5a5 6`
325			`test_gr_a5a5 7`
326
327			`.if (sim_cpu == h8300s \|\| sim_cpu == h8sx) ; Earlier versions, no exr`
328			`xorc_imm8_exr:`
329			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
330			`ldc #0, exr`
331			`stc exr, r0l`
332			`test_h_gr8 0, r0l`
333
334			`set_ccr_zero`
335			`;; xorc #xx:8,exr`
336
337			`xorc #0x80, exr`
338			`test_cc_clear`
339			`stc exr, r0l`
340			`test_h_gr8 0x80, r0l`
341			`xorc #0x80, exr`
342			`stc exr, r0l`
343			`test_h_gr8 0, r0l`
344
345			`xorc #0x4, exr`
346			`stc exr, r0l`
347			`test_h_gr8 4, r0l`
348			`xorc #0x4, exr`
349			`stc exr, r0l`
350			`test_h_gr8 0, r0l`
351
352			`xorc #0x2, exr ; Immediate 8-bit operand (overflow flag)`
353			`stc exr, r0l`
354			`test_h_gr8 2, r0l`
355			`xorc #0x2, exr`
356			`stc exr, r0l`
357			`test_h_gr8 0, r0l`
358
359			`xorc #0x1, exr ; Immediate 8-bit operand (carry flag)`
360			`stc exr, r0l`
361			`test_h_gr8 1, r0l`
362			`xorc #0x1, exr`
363			`stc exr, r0l`
364			`test_h_gr8 0, r0l`
365
366			`test_h_gr32 0xa5a5a500 er0`
367			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
368			`test_gr_a5a5 2`
369			`test_gr_a5a5 3`
370			`test_gr_a5a5 4`
371			`test_gr_a5a5 5`
372			`test_gr_a5a5 6`
373			`test_gr_a5a5 7`
374			`.endif ; not h8300 or h8300h`
375
376			`pass`
377
378			`exit 0`