OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [hw-trap.ms] - Blame information for rev 840

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# mach(): m32r m32rx
2
# output(): pass\n
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
; construct bra trap2_handler in trap 2 slot
9
        ld24 r0,#bra_insn
10
        ld r0,@r0
11
        ld24 r1,#trap2_handler
12
        addi r1,#-0x48 ; pc relative address from trap 2 slot to handler
13
        srai r1,#2
14
        or r0,r1
15
        ld24 r2,#0x48 ; address of trap 2 slot
16
        st r0,@r2
17
 
18
; perform trap
19
        ldi r4,#0
20
        trap #2
21
        test_h_gr r4,42
22
 
23
        pass
24
 
25
; trap 2 handler
26
trap2_handler:
27
        ldi r4,#42
28
        rte
29
 
30
bra_insn:
31
        bra.l 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.