OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [misc.exp] - Blame information for rev 157

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# Miscellaneous M32R simulator testcases
2
 
3
if [istarget m32r*-*-*] {
4
    # load support procs
5
    # load_lib cgen.exp
6
 
7
    # all machines
8
    set all_machs "m32r"
9
 
10
 
11
    # The .ms suffix is for "miscellaneous .s".
12
    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] {
13
        # If we're only testing specific files and this isn't one of them,
14
        # skip it.
15
        if ![runtest_file_p $runtests $src] {
16
            continue
17
        }
18
 
19
        run_sim_test $src $all_machs
20
    }
21
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.