OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [sra3.cgs] - Blame information for rev 840

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# m32r testcase for sra3 $dr,$sr,#$simm16
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global sra3
9
sra3:
10
 
11
        mvi_h_gr  r4, 0
12
        mvi_h_gr  r5, 0xf0f0f0ff
13
        sra3      r4, r5, #4
14
        test_h_gr r4, 0xff0f0f0f
15
 
16
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.