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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [stb-d.cgs] - Blame information for rev 24

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# m32r testcase for stb $src1,@($slo16,$src2)
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global stb_d
stb_d:
        mvaddr_h_gr r4, data_loc
        mvi_h_gr    r5, 0x1234
 
        stb r5, @(#8,r4)
 
        mvaddr_h_gr r4, data_loc2
        ld r4, @r4
        test_h_gr r4, 0x34000000 ; big endian processor
 
        pass
 
data_loc:
        .word 0
        .word 0
data_loc2:
        .word 0

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for stb $src1,@($slo16,$src2)`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global stb_d`
9			`stb_d:`
10			`mvaddr_h_gr r4, data_loc`
11			`mvi_h_gr r5, 0x1234`
12
13			`stb r5, @(#8,r4)`
14
15			`mvaddr_h_gr r4, data_loc2`
16			`ld r4, @r4`
17			`test_h_gr r4, 0x34000000 ; big endian processor`
18
19			`pass`
20
21			`data_loc:`
22			`.word 0`
23			`.word 0`
24			`data_loc2:`
25			`.word 0`

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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [stb-d.cgs] - Blame information for rev 24