OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [add.cgs] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for add $rm, $rn -*- Asm -*-
2
# mach: all
3
# as: -isa=shcompact
4
# ld: -m shelf32
5
 
6
        .include "compact/testutils.inc"
7
 
8
        start
9
init:
10
        # Initialise some registers with values which help us to verify
11
        # that the correct source registers are used by the ADD instruction.
12
        mov #0, r0
13
        mov #1, r1
14
        mov #2, r2
15
        mov #3, r3
16
        mov #5, r5
17
        mov #15, r15
18
 
19
add:
20
        # 0 + 0 = 0.
21
        add r0, r0
22
        assert r0, #0
23
 
24
        # 0 + 1 = 1.
25
        add r0, r1
26
        assert r1, #1
27
 
28
        # 1 + 2 = 3.
29
        add r1, r2
30
        assert r2, #3
31
 
32
        # 3 + 5 = 8.
33
        add r3, r5
34
        assert r5, #8
35
 
36
        # 8 + 8 = 16.
37
        add r5, r5
38
        assert r5, #16
39
 
40
        # 15 + 1 = 16.
41
        add r15, r1
42
        assert r1, #16
43
 
44
neg:
45
        mov #1, r0
46
        neg r0, r0
47
        mov #2, r1
48
        add r0, r1
49
        assert r1, #1
50
 
51
okay:
52
        pass
53
 
54
wrong:
55
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.