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jeremybenn |
/* Target dependent code for CRIS, for GDB, the GNU debugger.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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Contributed by Axis Communications AB.
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Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "frame.h"
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#include "frame-unwind.h"
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#include "frame-base.h"
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#include "trad-frame.h"
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#include "dwarf2-frame.h"
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#include "symtab.h"
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#include "inferior.h"
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#include "gdbtypes.h"
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#include "gdbcore.h"
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#include "gdbcmd.h"
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#include "target.h"
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#include "value.h"
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#include "opcode/cris.h"
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#include "arch-utils.h"
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#include "regcache.h"
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#include "gdb_assert.h"
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#include "objfiles.h"
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#include "solib.h" /* Support for shared libraries. */
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#include "solib-svr4.h"
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#include "gdb_string.h"
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#include "dis-asm.h"
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enum cris_num_regs
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{
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/* There are no floating point registers. Used in gdbserver low-linux.c. */
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NUM_FREGS = 0,
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/* There are 16 general registers. */
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NUM_GENREGS = 16,
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/* There are 16 special registers. */
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NUM_SPECREGS = 16,
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/* CRISv32 has a pseudo PC register, not noted here. */
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/* CRISv32 has 16 support registers. */
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NUM_SUPPREGS = 16
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};
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/* Register numbers of various important registers.
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CRIS_FP_REGNUM Contains address of executing stack frame.
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STR_REGNUM Contains the address of structure return values.
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RET_REGNUM Contains the return value when shorter than or equal to 32 bits
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ARG1_REGNUM Contains the first parameter to a function.
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ARG2_REGNUM Contains the second parameter to a function.
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ARG3_REGNUM Contains the third parameter to a function.
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ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
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gdbarch_sp_regnum Contains address of top of stack.
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gdbarch_pc_regnum Contains address of next instruction.
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SRP_REGNUM Subroutine return pointer register.
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BRP_REGNUM Breakpoint return pointer register. */
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enum cris_regnums
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{
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/* Enums with respect to the general registers, valid for all
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CRIS versions. The frame pointer is always in R8. */
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CRIS_FP_REGNUM = 8,
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/* ABI related registers. */
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STR_REGNUM = 9,
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RET_REGNUM = 10,
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ARG1_REGNUM = 10,
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ARG2_REGNUM = 11,
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ARG3_REGNUM = 12,
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ARG4_REGNUM = 13,
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/* Registers which happen to be common. */
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VR_REGNUM = 17,
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MOF_REGNUM = 23,
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SRP_REGNUM = 27,
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/* CRISv10 et. al. specific registers. */
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P0_REGNUM = 16,
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P4_REGNUM = 20,
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CCR_REGNUM = 21,
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P8_REGNUM = 24,
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IBR_REGNUM = 25,
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IRP_REGNUM = 26,
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BAR_REGNUM = 28,
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DCCR_REGNUM = 29,
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BRP_REGNUM = 30,
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USP_REGNUM = 31,
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/* CRISv32 specific registers. */
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ACR_REGNUM = 15,
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BZ_REGNUM = 16,
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PID_REGNUM = 18,
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SRS_REGNUM = 19,
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WZ_REGNUM = 20,
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EXS_REGNUM = 21,
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EDA_REGNUM = 22,
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DZ_REGNUM = 24,
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EBP_REGNUM = 25,
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ERP_REGNUM = 26,
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NRP_REGNUM = 28,
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CCS_REGNUM = 29,
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CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
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SPC_REGNUM = 31,
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CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
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S0_REGNUM = 33,
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S1_REGNUM = 34,
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S2_REGNUM = 35,
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S3_REGNUM = 36,
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S4_REGNUM = 37,
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S5_REGNUM = 38,
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S6_REGNUM = 39,
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S7_REGNUM = 40,
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S8_REGNUM = 41,
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S9_REGNUM = 42,
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S10_REGNUM = 43,
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S11_REGNUM = 44,
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S12_REGNUM = 45,
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S13_REGNUM = 46,
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S14_REGNUM = 47,
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S15_REGNUM = 48,
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};
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extern const struct cris_spec_reg cris_spec_regs[];
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/* CRIS version, set via the user command 'set cris-version'. Affects
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register names and sizes. */
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static int usr_cmd_cris_version;
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/* Indicates whether to trust the above variable. */
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static int usr_cmd_cris_version_valid = 0;
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static const char cris_mode_normal[] = "normal";
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static const char cris_mode_guru[] = "guru";
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static const char *cris_modes[] = {
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cris_mode_normal,
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cris_mode_guru,
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};
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/* CRIS mode, set via the user command 'set cris-mode'. Affects
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type of break instruction among other things. */
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static const char *usr_cmd_cris_mode = cris_mode_normal;
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/* Whether to make use of Dwarf-2 CFI (default on). */
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static int usr_cmd_cris_dwarf2_cfi = 1;
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/* CRIS architecture specific information. */
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struct gdbarch_tdep
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{
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int cris_version;
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const char *cris_mode;
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int cris_dwarf2_cfi;
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};
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/* Sigtramp identification code copied from i386-linux-tdep.c. */
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#define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
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#define SIGTRAMP_OFFSET0 0
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#define SIGTRAMP_INSN1 0xe93d /* break 13 */
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#define SIGTRAMP_OFFSET1 4
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static const unsigned short sigtramp_code[] =
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{
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SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
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SIGTRAMP_INSN1 /* break 13 */
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};
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#define SIGTRAMP_LEN (sizeof sigtramp_code)
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/* Note: same length as normal sigtramp code. */
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static const unsigned short rt_sigtramp_code[] =
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{
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SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
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SIGTRAMP_INSN1 /* break 13 */
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};
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/* If PC is in a sigtramp routine, return the address of the start of
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the routine. Otherwise, return 0. */
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static CORE_ADDR
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cris_sigtramp_start (struct frame_info *this_frame)
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{
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CORE_ADDR pc = get_frame_pc (this_frame);
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gdb_byte buf[SIGTRAMP_LEN];
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if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
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return 0;
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if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
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{
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if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
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return 0;
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pc -= SIGTRAMP_OFFSET1;
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if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
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return 0;
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}
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if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
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return 0;
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return pc;
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}
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/* If PC is in a RT sigtramp routine, return the address of the start of
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the routine. Otherwise, return 0. */
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static CORE_ADDR
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cris_rt_sigtramp_start (struct frame_info *this_frame)
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{
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CORE_ADDR pc = get_frame_pc (this_frame);
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gdb_byte buf[SIGTRAMP_LEN];
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if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
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return 0;
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if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
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{
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if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
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return 0;
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pc -= SIGTRAMP_OFFSET1;
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if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
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return 0;
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}
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if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
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return 0;
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return pc;
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}
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/* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
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return the address of the associated sigcontext structure. */
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static CORE_ADDR
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cris_sigcontext_addr (struct frame_info *this_frame)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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CORE_ADDR pc;
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CORE_ADDR sp;
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char buf[4];
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get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
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sp = extract_unsigned_integer (buf, 4, byte_order);
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/* Look for normal sigtramp frame first. */
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pc = cris_sigtramp_start (this_frame);
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if (pc)
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{
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/* struct signal_frame (arch/cris/kernel/signal.c) contains
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struct sigcontext as its first member, meaning the SP points to
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it already. */
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return sp;
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}
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pc = cris_rt_sigtramp_start (this_frame);
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if (pc)
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{
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/* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
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a struct ucontext, which in turn contains a struct sigcontext.
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Magic digging:
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4 + 4 + 128 to struct ucontext, then
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4 + 4 + 12 to struct sigcontext. */
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return (sp + 156);
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}
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error (_("Couldn't recognize signal trampoline."));
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return 0;
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}
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struct cris_unwind_cache
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{
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/* The previous frame's inner most stack address. Used as this
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frame ID's stack_addr. */
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CORE_ADDR prev_sp;
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/* The frame's base, optionally used by the high-level debug info. */
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CORE_ADDR base;
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int size;
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/* How far the SP and r8 (FP) have been offset from the start of
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the stack frame (as defined by the previous frame's stack
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pointer). */
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LONGEST sp_offset;
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LONGEST r8_offset;
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int uses_frame;
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/* From old frame_extra_info struct. */
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CORE_ADDR return_pc;
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int leaf_function;
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/* Table indicating the location of each and every register. */
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struct trad_frame_saved_reg *saved_regs;
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};
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static struct cris_unwind_cache *
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cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
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void **this_cache)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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struct cris_unwind_cache *info;
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CORE_ADDR pc;
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CORE_ADDR sp;
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CORE_ADDR addr;
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char buf[4];
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int i;
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if ((*this_cache))
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return (*this_cache);
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info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
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(*this_cache) = info;
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info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
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/* Zero all fields. */
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info->prev_sp = 0;
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info->base = 0;
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info->size = 0;
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info->sp_offset = 0;
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info->r8_offset = 0;
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info->uses_frame = 0;
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info->return_pc = 0;
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info->leaf_function = 0;
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get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
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info->base = extract_unsigned_integer (buf, 4, byte_order);
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addr = cris_sigcontext_addr (this_frame);
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/* Layout of the sigcontext struct:
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struct sigcontext {
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struct pt_regs regs;
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unsigned long oldmask;
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358 |
|
|
unsigned long usp;
|
359 |
|
|
}; */
|
360 |
|
|
|
361 |
|
|
if (tdep->cris_version == 10)
|
362 |
|
|
{
|
363 |
|
|
/* R0 to R13 are stored in reverse order at offset (2 * 4) in
|
364 |
|
|
struct pt_regs. */
|
365 |
|
|
for (i = 0; i <= 13; i++)
|
366 |
|
|
info->saved_regs[i].addr = addr + ((15 - i) * 4);
|
367 |
|
|
|
368 |
|
|
info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
|
369 |
|
|
info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
|
370 |
|
|
info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
|
371 |
|
|
/* Note: IRP is off by 2 at this point. There's no point in correcting
|
372 |
|
|
it though since that will mean that the backtrace will show a PC
|
373 |
|
|
different from what is shown when stopped. */
|
374 |
|
|
info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
|
375 |
|
|
info->saved_regs[gdbarch_pc_regnum (gdbarch)]
|
376 |
|
|
= info->saved_regs[IRP_REGNUM];
|
377 |
|
|
info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
|
378 |
|
|
}
|
379 |
|
|
else
|
380 |
|
|
{
|
381 |
|
|
/* CRISv32. */
|
382 |
|
|
/* R0 to R13 are stored in order at offset (1 * 4) in
|
383 |
|
|
struct pt_regs. */
|
384 |
|
|
for (i = 0; i <= 13; i++)
|
385 |
|
|
info->saved_regs[i].addr = addr + ((i + 1) * 4);
|
386 |
|
|
|
387 |
|
|
info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
|
388 |
|
|
info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
|
389 |
|
|
info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
|
390 |
|
|
info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
|
391 |
|
|
info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
|
392 |
|
|
info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
|
393 |
|
|
info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
|
394 |
|
|
info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
|
395 |
|
|
info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
|
396 |
|
|
|
397 |
|
|
/* FIXME: If ERP is in a delay slot at this point then the PC will
|
398 |
|
|
be wrong at this point. This problem manifests itself in the
|
399 |
|
|
sigaltstack.exp test case, which occasionally generates FAILs when
|
400 |
|
|
the signal is received while in a delay slot.
|
401 |
|
|
|
402 |
|
|
This could be solved by a couple of read_memory_unsigned_integer and a
|
403 |
|
|
trad_frame_set_value. */
|
404 |
|
|
info->saved_regs[gdbarch_pc_regnum (gdbarch)]
|
405 |
|
|
= info->saved_regs[ERP_REGNUM];
|
406 |
|
|
|
407 |
|
|
info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
|
408 |
|
|
= addr + (25 * 4);
|
409 |
|
|
}
|
410 |
|
|
|
411 |
|
|
return info;
|
412 |
|
|
}
|
413 |
|
|
|
414 |
|
|
static void
|
415 |
|
|
cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
|
416 |
|
|
struct frame_id *this_id)
|
417 |
|
|
{
|
418 |
|
|
struct cris_unwind_cache *cache =
|
419 |
|
|
cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
|
420 |
|
|
(*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
|
421 |
|
|
}
|
422 |
|
|
|
423 |
|
|
/* Forward declaration. */
|
424 |
|
|
|
425 |
|
|
static struct value *cris_frame_prev_register (struct frame_info *this_frame,
|
426 |
|
|
void **this_cache, int regnum);
|
427 |
|
|
static struct value *
|
428 |
|
|
cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
|
429 |
|
|
void **this_cache, int regnum)
|
430 |
|
|
{
|
431 |
|
|
/* Make sure we've initialized the cache. */
|
432 |
|
|
cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
|
433 |
|
|
return cris_frame_prev_register (this_frame, this_cache, regnum);
|
434 |
|
|
}
|
435 |
|
|
|
436 |
|
|
static int
|
437 |
|
|
cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
|
438 |
|
|
struct frame_info *this_frame,
|
439 |
|
|
void **this_cache)
|
440 |
|
|
{
|
441 |
|
|
if (cris_sigtramp_start (this_frame)
|
442 |
|
|
|| cris_rt_sigtramp_start (this_frame))
|
443 |
|
|
return 1;
|
444 |
|
|
|
445 |
|
|
return 0;
|
446 |
|
|
}
|
447 |
|
|
|
448 |
|
|
static const struct frame_unwind cris_sigtramp_frame_unwind =
|
449 |
|
|
{
|
450 |
|
|
SIGTRAMP_FRAME,
|
451 |
|
|
cris_sigtramp_frame_this_id,
|
452 |
|
|
cris_sigtramp_frame_prev_register,
|
453 |
|
|
NULL,
|
454 |
|
|
cris_sigtramp_frame_sniffer
|
455 |
|
|
};
|
456 |
|
|
|
457 |
|
|
static int
|
458 |
|
|
crisv32_single_step_through_delay (struct gdbarch *gdbarch,
|
459 |
|
|
struct frame_info *this_frame)
|
460 |
|
|
{
|
461 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
462 |
|
|
ULONGEST erp;
|
463 |
|
|
int ret = 0;
|
464 |
|
|
|
465 |
|
|
if (tdep->cris_mode == cris_mode_guru)
|
466 |
|
|
erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
|
467 |
|
|
else
|
468 |
|
|
erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
|
469 |
|
|
|
470 |
|
|
if (erp & 0x1)
|
471 |
|
|
{
|
472 |
|
|
/* In delay slot - check if there's a breakpoint at the preceding
|
473 |
|
|
instruction. */
|
474 |
|
|
if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
|
475 |
|
|
ret = 1;
|
476 |
|
|
}
|
477 |
|
|
return ret;
|
478 |
|
|
}
|
479 |
|
|
|
480 |
|
|
/* Hardware watchpoint support. */
|
481 |
|
|
|
482 |
|
|
/* We support 6 hardware data watchpoints, but cannot trigger on execute
|
483 |
|
|
(any combination of read/write is fine). */
|
484 |
|
|
|
485 |
|
|
int
|
486 |
|
|
cris_can_use_hardware_watchpoint (int type, int count, int other)
|
487 |
|
|
{
|
488 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
|
489 |
|
|
|
490 |
|
|
/* No bookkeeping is done here; it is handled by the remote debug agent. */
|
491 |
|
|
|
492 |
|
|
if (tdep->cris_version != 32)
|
493 |
|
|
return 0;
|
494 |
|
|
else
|
495 |
|
|
/* CRISv32: Six data watchpoints, one for instructions. */
|
496 |
|
|
return (((type == bp_read_watchpoint || type == bp_access_watchpoint
|
497 |
|
|
|| type == bp_hardware_watchpoint) && count <= 6)
|
498 |
|
|
|| (type == bp_hardware_breakpoint && count <= 1));
|
499 |
|
|
}
|
500 |
|
|
|
501 |
|
|
/* The CRISv32 hardware data watchpoints work by specifying ranges,
|
502 |
|
|
which have no alignment or length restrictions. */
|
503 |
|
|
|
504 |
|
|
int
|
505 |
|
|
cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
|
506 |
|
|
{
|
507 |
|
|
return 1;
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
/* If the inferior has some watchpoint that triggered, return the
|
511 |
|
|
address associated with that watchpoint. Otherwise, return
|
512 |
|
|
zero. */
|
513 |
|
|
|
514 |
|
|
CORE_ADDR
|
515 |
|
|
cris_stopped_data_address (void)
|
516 |
|
|
{
|
517 |
|
|
CORE_ADDR eda;
|
518 |
|
|
eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
|
519 |
|
|
return eda;
|
520 |
|
|
}
|
521 |
|
|
|
522 |
|
|
/* The instruction environment needed to find single-step breakpoints. */
|
523 |
|
|
|
524 |
|
|
typedef
|
525 |
|
|
struct instruction_environment
|
526 |
|
|
{
|
527 |
|
|
unsigned long reg[NUM_GENREGS];
|
528 |
|
|
unsigned long preg[NUM_SPECREGS];
|
529 |
|
|
unsigned long branch_break_address;
|
530 |
|
|
unsigned long delay_slot_pc;
|
531 |
|
|
unsigned long prefix_value;
|
532 |
|
|
int branch_found;
|
533 |
|
|
int prefix_found;
|
534 |
|
|
int invalid;
|
535 |
|
|
int slot_needed;
|
536 |
|
|
int delay_slot_pc_active;
|
537 |
|
|
int xflag_found;
|
538 |
|
|
int disable_interrupt;
|
539 |
|
|
int byte_order;
|
540 |
|
|
} inst_env_type;
|
541 |
|
|
|
542 |
|
|
/* Machine-dependencies in CRIS for opcodes. */
|
543 |
|
|
|
544 |
|
|
/* Instruction sizes. */
|
545 |
|
|
enum cris_instruction_sizes
|
546 |
|
|
{
|
547 |
|
|
INST_BYTE_SIZE = 0,
|
548 |
|
|
INST_WORD_SIZE = 1,
|
549 |
|
|
INST_DWORD_SIZE = 2
|
550 |
|
|
};
|
551 |
|
|
|
552 |
|
|
/* Addressing modes. */
|
553 |
|
|
enum cris_addressing_modes
|
554 |
|
|
{
|
555 |
|
|
REGISTER_MODE = 1,
|
556 |
|
|
INDIRECT_MODE = 2,
|
557 |
|
|
AUTOINC_MODE = 3
|
558 |
|
|
};
|
559 |
|
|
|
560 |
|
|
/* Prefix addressing modes. */
|
561 |
|
|
enum cris_prefix_addressing_modes
|
562 |
|
|
{
|
563 |
|
|
PREFIX_INDEX_MODE = 2,
|
564 |
|
|
PREFIX_ASSIGN_MODE = 3,
|
565 |
|
|
|
566 |
|
|
/* Handle immediate byte offset addressing mode prefix format. */
|
567 |
|
|
PREFIX_OFFSET_MODE = 2
|
568 |
|
|
};
|
569 |
|
|
|
570 |
|
|
/* Masks for opcodes. */
|
571 |
|
|
enum cris_opcode_masks
|
572 |
|
|
{
|
573 |
|
|
BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
|
574 |
|
|
SIGNED_EXTEND_BIT_MASK = 0x2,
|
575 |
|
|
SIGNED_BYTE_MASK = 0x80,
|
576 |
|
|
SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
|
577 |
|
|
SIGNED_WORD_MASK = 0x8000,
|
578 |
|
|
SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
|
579 |
|
|
SIGNED_DWORD_MASK = 0x80000000,
|
580 |
|
|
SIGNED_QUICK_VALUE_MASK = 0x20,
|
581 |
|
|
SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
|
582 |
|
|
};
|
583 |
|
|
|
584 |
|
|
/* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
|
585 |
|
|
Bit 15 - 12 Operand2
|
586 |
|
|
11 - 10 Mode
|
587 |
|
|
9 - 6 Opcode
|
588 |
|
|
5 - 4 Size
|
589 |
|
|
3 - 0 Operand1 */
|
590 |
|
|
|
591 |
|
|
static int
|
592 |
|
|
cris_get_operand2 (unsigned short insn)
|
593 |
|
|
{
|
594 |
|
|
return ((insn & 0xF000) >> 12);
|
595 |
|
|
}
|
596 |
|
|
|
597 |
|
|
static int
|
598 |
|
|
cris_get_mode (unsigned short insn)
|
599 |
|
|
{
|
600 |
|
|
return ((insn & 0x0C00) >> 10);
|
601 |
|
|
}
|
602 |
|
|
|
603 |
|
|
static int
|
604 |
|
|
cris_get_opcode (unsigned short insn)
|
605 |
|
|
{
|
606 |
|
|
return ((insn & 0x03C0) >> 6);
|
607 |
|
|
}
|
608 |
|
|
|
609 |
|
|
static int
|
610 |
|
|
cris_get_size (unsigned short insn)
|
611 |
|
|
{
|
612 |
|
|
return ((insn & 0x0030) >> 4);
|
613 |
|
|
}
|
614 |
|
|
|
615 |
|
|
static int
|
616 |
|
|
cris_get_operand1 (unsigned short insn)
|
617 |
|
|
{
|
618 |
|
|
return (insn & 0x000F);
|
619 |
|
|
}
|
620 |
|
|
|
621 |
|
|
/* Additional functions in order to handle opcodes. */
|
622 |
|
|
|
623 |
|
|
static int
|
624 |
|
|
cris_get_quick_value (unsigned short insn)
|
625 |
|
|
{
|
626 |
|
|
return (insn & 0x003F);
|
627 |
|
|
}
|
628 |
|
|
|
629 |
|
|
static int
|
630 |
|
|
cris_get_bdap_quick_offset (unsigned short insn)
|
631 |
|
|
{
|
632 |
|
|
return (insn & 0x00FF);
|
633 |
|
|
}
|
634 |
|
|
|
635 |
|
|
static int
|
636 |
|
|
cris_get_branch_short_offset (unsigned short insn)
|
637 |
|
|
{
|
638 |
|
|
return (insn & 0x00FF);
|
639 |
|
|
}
|
640 |
|
|
|
641 |
|
|
static int
|
642 |
|
|
cris_get_asr_shift_steps (unsigned long value)
|
643 |
|
|
{
|
644 |
|
|
return (value & 0x3F);
|
645 |
|
|
}
|
646 |
|
|
|
647 |
|
|
static int
|
648 |
|
|
cris_get_clear_size (unsigned short insn)
|
649 |
|
|
{
|
650 |
|
|
return ((insn) & 0xC000);
|
651 |
|
|
}
|
652 |
|
|
|
653 |
|
|
static int
|
654 |
|
|
cris_is_signed_extend_bit_on (unsigned short insn)
|
655 |
|
|
{
|
656 |
|
|
return (((insn) & 0x20) == 0x20);
|
657 |
|
|
}
|
658 |
|
|
|
659 |
|
|
static int
|
660 |
|
|
cris_is_xflag_bit_on (unsigned short insn)
|
661 |
|
|
{
|
662 |
|
|
return (((insn) & 0x1000) == 0x1000);
|
663 |
|
|
}
|
664 |
|
|
|
665 |
|
|
static void
|
666 |
|
|
cris_set_size_to_dword (unsigned short *insn)
|
667 |
|
|
{
|
668 |
|
|
*insn &= 0xFFCF;
|
669 |
|
|
*insn |= 0x20;
|
670 |
|
|
}
|
671 |
|
|
|
672 |
|
|
static signed char
|
673 |
|
|
cris_get_signed_offset (unsigned short insn)
|
674 |
|
|
{
|
675 |
|
|
return ((signed char) (insn & 0x00FF));
|
676 |
|
|
}
|
677 |
|
|
|
678 |
|
|
/* Calls an op function given the op-type, working on the insn and the
|
679 |
|
|
inst_env. */
|
680 |
|
|
static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
|
681 |
|
|
inst_env_type *);
|
682 |
|
|
|
683 |
|
|
static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
|
684 |
|
|
struct gdbarch_list *);
|
685 |
|
|
|
686 |
|
|
static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
|
687 |
|
|
|
688 |
|
|
static void set_cris_version (char *ignore_args, int from_tty,
|
689 |
|
|
struct cmd_list_element *c);
|
690 |
|
|
|
691 |
|
|
static void set_cris_mode (char *ignore_args, int from_tty,
|
692 |
|
|
struct cmd_list_element *c);
|
693 |
|
|
|
694 |
|
|
static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
|
695 |
|
|
struct cmd_list_element *c);
|
696 |
|
|
|
697 |
|
|
static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
|
698 |
|
|
struct frame_info *this_frame,
|
699 |
|
|
struct cris_unwind_cache *info);
|
700 |
|
|
|
701 |
|
|
static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
|
702 |
|
|
struct frame_info *this_frame,
|
703 |
|
|
struct cris_unwind_cache *info);
|
704 |
|
|
|
705 |
|
|
static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
|
706 |
|
|
struct frame_info *next_frame);
|
707 |
|
|
|
708 |
|
|
static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
|
709 |
|
|
struct frame_info *next_frame);
|
710 |
|
|
|
711 |
|
|
/* When arguments must be pushed onto the stack, they go on in reverse
|
712 |
|
|
order. The below implements a FILO (stack) to do this.
|
713 |
|
|
Copied from d10v-tdep.c. */
|
714 |
|
|
|
715 |
|
|
struct stack_item
|
716 |
|
|
{
|
717 |
|
|
int len;
|
718 |
|
|
struct stack_item *prev;
|
719 |
|
|
void *data;
|
720 |
|
|
};
|
721 |
|
|
|
722 |
|
|
static struct stack_item *
|
723 |
|
|
push_stack_item (struct stack_item *prev, void *contents, int len)
|
724 |
|
|
{
|
725 |
|
|
struct stack_item *si;
|
726 |
|
|
si = xmalloc (sizeof (struct stack_item));
|
727 |
|
|
si->data = xmalloc (len);
|
728 |
|
|
si->len = len;
|
729 |
|
|
si->prev = prev;
|
730 |
|
|
memcpy (si->data, contents, len);
|
731 |
|
|
return si;
|
732 |
|
|
}
|
733 |
|
|
|
734 |
|
|
static struct stack_item *
|
735 |
|
|
pop_stack_item (struct stack_item *si)
|
736 |
|
|
{
|
737 |
|
|
struct stack_item *dead = si;
|
738 |
|
|
si = si->prev;
|
739 |
|
|
xfree (dead->data);
|
740 |
|
|
xfree (dead);
|
741 |
|
|
return si;
|
742 |
|
|
}
|
743 |
|
|
|
744 |
|
|
/* Put here the code to store, into fi->saved_regs, the addresses of
|
745 |
|
|
the saved registers of frame described by FRAME_INFO. This
|
746 |
|
|
includes special registers such as pc and fp saved in special ways
|
747 |
|
|
in the stack frame. sp is even more special: the address we return
|
748 |
|
|
for it IS the sp for the next frame. */
|
749 |
|
|
|
750 |
|
|
static struct cris_unwind_cache *
|
751 |
|
|
cris_frame_unwind_cache (struct frame_info *this_frame,
|
752 |
|
|
void **this_prologue_cache)
|
753 |
|
|
{
|
754 |
|
|
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
755 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
756 |
|
|
CORE_ADDR pc;
|
757 |
|
|
struct cris_unwind_cache *info;
|
758 |
|
|
int i;
|
759 |
|
|
|
760 |
|
|
if ((*this_prologue_cache))
|
761 |
|
|
return (*this_prologue_cache);
|
762 |
|
|
|
763 |
|
|
info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
|
764 |
|
|
(*this_prologue_cache) = info;
|
765 |
|
|
info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
766 |
|
|
|
767 |
|
|
/* Zero all fields. */
|
768 |
|
|
info->prev_sp = 0;
|
769 |
|
|
info->base = 0;
|
770 |
|
|
info->size = 0;
|
771 |
|
|
info->sp_offset = 0;
|
772 |
|
|
info->r8_offset = 0;
|
773 |
|
|
info->uses_frame = 0;
|
774 |
|
|
info->return_pc = 0;
|
775 |
|
|
info->leaf_function = 0;
|
776 |
|
|
|
777 |
|
|
/* Prologue analysis does the rest... */
|
778 |
|
|
if (tdep->cris_version == 32)
|
779 |
|
|
crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
|
780 |
|
|
else
|
781 |
|
|
cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
|
782 |
|
|
|
783 |
|
|
return info;
|
784 |
|
|
}
|
785 |
|
|
|
786 |
|
|
/* Given a GDB frame, determine the address of the calling function's
|
787 |
|
|
frame. This will be used to create a new GDB frame struct. */
|
788 |
|
|
|
789 |
|
|
static void
|
790 |
|
|
cris_frame_this_id (struct frame_info *this_frame,
|
791 |
|
|
void **this_prologue_cache,
|
792 |
|
|
struct frame_id *this_id)
|
793 |
|
|
{
|
794 |
|
|
struct cris_unwind_cache *info
|
795 |
|
|
= cris_frame_unwind_cache (this_frame, this_prologue_cache);
|
796 |
|
|
CORE_ADDR base;
|
797 |
|
|
CORE_ADDR func;
|
798 |
|
|
struct frame_id id;
|
799 |
|
|
|
800 |
|
|
/* The FUNC is easy. */
|
801 |
|
|
func = get_frame_func (this_frame);
|
802 |
|
|
|
803 |
|
|
/* Hopefully the prologue analysis either correctly determined the
|
804 |
|
|
frame's base (which is the SP from the previous frame), or set
|
805 |
|
|
that base to "NULL". */
|
806 |
|
|
base = info->prev_sp;
|
807 |
|
|
if (base == 0)
|
808 |
|
|
return;
|
809 |
|
|
|
810 |
|
|
id = frame_id_build (base, func);
|
811 |
|
|
|
812 |
|
|
(*this_id) = id;
|
813 |
|
|
}
|
814 |
|
|
|
815 |
|
|
static struct value *
|
816 |
|
|
cris_frame_prev_register (struct frame_info *this_frame,
|
817 |
|
|
void **this_prologue_cache, int regnum)
|
818 |
|
|
{
|
819 |
|
|
struct cris_unwind_cache *info
|
820 |
|
|
= cris_frame_unwind_cache (this_frame, this_prologue_cache);
|
821 |
|
|
return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
|
822 |
|
|
}
|
823 |
|
|
|
824 |
|
|
/* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
|
825 |
|
|
frame. The frame ID's base needs to match the TOS value saved by
|
826 |
|
|
save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
|
827 |
|
|
|
828 |
|
|
static struct frame_id
|
829 |
|
|
cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
|
830 |
|
|
{
|
831 |
|
|
CORE_ADDR sp;
|
832 |
|
|
sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
|
833 |
|
|
return frame_id_build (sp, get_frame_pc (this_frame));
|
834 |
|
|
}
|
835 |
|
|
|
836 |
|
|
static CORE_ADDR
|
837 |
|
|
cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
|
838 |
|
|
{
|
839 |
|
|
/* Align to the size of an instruction (so that they can safely be
|
840 |
|
|
pushed onto the stack). */
|
841 |
|
|
return sp & ~3;
|
842 |
|
|
}
|
843 |
|
|
|
844 |
|
|
static CORE_ADDR
|
845 |
|
|
cris_push_dummy_code (struct gdbarch *gdbarch,
|
846 |
|
|
CORE_ADDR sp, CORE_ADDR funaddr,
|
847 |
|
|
struct value **args, int nargs,
|
848 |
|
|
struct type *value_type,
|
849 |
|
|
CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
|
850 |
|
|
struct regcache *regcache)
|
851 |
|
|
{
|
852 |
|
|
/* Allocate space sufficient for a breakpoint. */
|
853 |
|
|
sp = (sp - 4) & ~3;
|
854 |
|
|
/* Store the address of that breakpoint */
|
855 |
|
|
*bp_addr = sp;
|
856 |
|
|
/* CRIS always starts the call at the callee's entry point. */
|
857 |
|
|
*real_pc = funaddr;
|
858 |
|
|
return sp;
|
859 |
|
|
}
|
860 |
|
|
|
861 |
|
|
static CORE_ADDR
|
862 |
|
|
cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
|
863 |
|
|
struct regcache *regcache, CORE_ADDR bp_addr,
|
864 |
|
|
int nargs, struct value **args, CORE_ADDR sp,
|
865 |
|
|
int struct_return, CORE_ADDR struct_addr)
|
866 |
|
|
{
|
867 |
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
868 |
|
|
int stack_alloc;
|
869 |
|
|
int stack_offset;
|
870 |
|
|
int argreg;
|
871 |
|
|
int argnum;
|
872 |
|
|
|
873 |
|
|
CORE_ADDR regval;
|
874 |
|
|
|
875 |
|
|
/* The function's arguments and memory allocated by gdb for the arguments to
|
876 |
|
|
point at reside in separate areas on the stack.
|
877 |
|
|
Both frame pointers grow toward higher addresses. */
|
878 |
|
|
CORE_ADDR fp_arg;
|
879 |
|
|
CORE_ADDR fp_mem;
|
880 |
|
|
|
881 |
|
|
struct stack_item *si = NULL;
|
882 |
|
|
|
883 |
|
|
/* Push the return address. */
|
884 |
|
|
regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
|
885 |
|
|
|
886 |
|
|
/* Are we returning a value using a structure return or a normal value
|
887 |
|
|
return? struct_addr is the address of the reserved space for the return
|
888 |
|
|
structure to be written on the stack. */
|
889 |
|
|
if (struct_return)
|
890 |
|
|
{
|
891 |
|
|
regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
|
892 |
|
|
}
|
893 |
|
|
|
894 |
|
|
/* Now load as many as possible of the first arguments into registers,
|
895 |
|
|
and push the rest onto the stack. */
|
896 |
|
|
argreg = ARG1_REGNUM;
|
897 |
|
|
stack_offset = 0;
|
898 |
|
|
|
899 |
|
|
for (argnum = 0; argnum < nargs; argnum++)
|
900 |
|
|
{
|
901 |
|
|
int len;
|
902 |
|
|
char *val;
|
903 |
|
|
int reg_demand;
|
904 |
|
|
int i;
|
905 |
|
|
|
906 |
|
|
len = TYPE_LENGTH (value_type (args[argnum]));
|
907 |
|
|
val = (char *) value_contents (args[argnum]);
|
908 |
|
|
|
909 |
|
|
/* How may registers worth of storage do we need for this argument? */
|
910 |
|
|
reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
|
911 |
|
|
|
912 |
|
|
if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
|
913 |
|
|
{
|
914 |
|
|
/* Data passed by value. Fits in available register(s). */
|
915 |
|
|
for (i = 0; i < reg_demand; i++)
|
916 |
|
|
{
|
917 |
|
|
regcache_cooked_write (regcache, argreg, val);
|
918 |
|
|
argreg++;
|
919 |
|
|
val += 4;
|
920 |
|
|
}
|
921 |
|
|
}
|
922 |
|
|
else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
|
923 |
|
|
{
|
924 |
|
|
/* Data passed by value. Does not fit in available register(s).
|
925 |
|
|
Use the register(s) first, then the stack. */
|
926 |
|
|
for (i = 0; i < reg_demand; i++)
|
927 |
|
|
{
|
928 |
|
|
if (argreg <= ARG4_REGNUM)
|
929 |
|
|
{
|
930 |
|
|
regcache_cooked_write (regcache, argreg, val);
|
931 |
|
|
argreg++;
|
932 |
|
|
val += 4;
|
933 |
|
|
}
|
934 |
|
|
else
|
935 |
|
|
{
|
936 |
|
|
/* Push item for later so that pushed arguments
|
937 |
|
|
come in the right order. */
|
938 |
|
|
si = push_stack_item (si, val, 4);
|
939 |
|
|
val += 4;
|
940 |
|
|
}
|
941 |
|
|
}
|
942 |
|
|
}
|
943 |
|
|
else if (len > (2 * 4))
|
944 |
|
|
{
|
945 |
|
|
/* Data passed by reference. Push copy of data onto stack
|
946 |
|
|
and pass pointer to this copy as argument. */
|
947 |
|
|
sp = (sp - len) & ~3;
|
948 |
|
|
write_memory (sp, val, len);
|
949 |
|
|
|
950 |
|
|
if (argreg <= ARG4_REGNUM)
|
951 |
|
|
{
|
952 |
|
|
regcache_cooked_write_unsigned (regcache, argreg, sp);
|
953 |
|
|
argreg++;
|
954 |
|
|
}
|
955 |
|
|
else
|
956 |
|
|
{
|
957 |
|
|
gdb_byte buf[4];
|
958 |
|
|
store_unsigned_integer (buf, 4, byte_order, sp);
|
959 |
|
|
si = push_stack_item (si, buf, 4);
|
960 |
|
|
}
|
961 |
|
|
}
|
962 |
|
|
else
|
963 |
|
|
{
|
964 |
|
|
/* Data passed by value. No available registers. Put it on
|
965 |
|
|
the stack. */
|
966 |
|
|
si = push_stack_item (si, val, len);
|
967 |
|
|
}
|
968 |
|
|
}
|
969 |
|
|
|
970 |
|
|
while (si)
|
971 |
|
|
{
|
972 |
|
|
/* fp_arg must be word-aligned (i.e., don't += len) to match
|
973 |
|
|
the function prologue. */
|
974 |
|
|
sp = (sp - si->len) & ~3;
|
975 |
|
|
write_memory (sp, si->data, si->len);
|
976 |
|
|
si = pop_stack_item (si);
|
977 |
|
|
}
|
978 |
|
|
|
979 |
|
|
/* Finally, update the SP register. */
|
980 |
|
|
regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
|
981 |
|
|
|
982 |
|
|
return sp;
|
983 |
|
|
}
|
984 |
|
|
|
985 |
|
|
static const struct frame_unwind cris_frame_unwind =
|
986 |
|
|
{
|
987 |
|
|
NORMAL_FRAME,
|
988 |
|
|
cris_frame_this_id,
|
989 |
|
|
cris_frame_prev_register,
|
990 |
|
|
NULL,
|
991 |
|
|
default_frame_sniffer
|
992 |
|
|
};
|
993 |
|
|
|
994 |
|
|
static CORE_ADDR
|
995 |
|
|
cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
|
996 |
|
|
{
|
997 |
|
|
struct cris_unwind_cache *info
|
998 |
|
|
= cris_frame_unwind_cache (this_frame, this_cache);
|
999 |
|
|
return info->base;
|
1000 |
|
|
}
|
1001 |
|
|
|
1002 |
|
|
static const struct frame_base cris_frame_base =
|
1003 |
|
|
{
|
1004 |
|
|
&cris_frame_unwind,
|
1005 |
|
|
cris_frame_base_address,
|
1006 |
|
|
cris_frame_base_address,
|
1007 |
|
|
cris_frame_base_address
|
1008 |
|
|
};
|
1009 |
|
|
|
1010 |
|
|
/* Frames information. The definition of the struct frame_info is
|
1011 |
|
|
|
1012 |
|
|
CORE_ADDR frame
|
1013 |
|
|
CORE_ADDR pc
|
1014 |
|
|
enum frame_type type;
|
1015 |
|
|
CORE_ADDR return_pc
|
1016 |
|
|
int leaf_function
|
1017 |
|
|
|
1018 |
|
|
If the compilation option -fno-omit-frame-pointer is present the
|
1019 |
|
|
variable frame will be set to the content of R8 which is the frame
|
1020 |
|
|
pointer register.
|
1021 |
|
|
|
1022 |
|
|
The variable pc contains the address where execution is performed
|
1023 |
|
|
in the present frame. The innermost frame contains the current content
|
1024 |
|
|
of the register PC. All other frames contain the content of the
|
1025 |
|
|
register PC in the next frame.
|
1026 |
|
|
|
1027 |
|
|
The variable `type' indicates the frame's type: normal, SIGTRAMP
|
1028 |
|
|
(associated with a signal handler), dummy (associated with a dummy
|
1029 |
|
|
frame).
|
1030 |
|
|
|
1031 |
|
|
The variable return_pc contains the address where execution should be
|
1032 |
|
|
resumed when the present frame has finished, the return address.
|
1033 |
|
|
|
1034 |
|
|
The variable leaf_function is 1 if the return address is in the register
|
1035 |
|
|
SRP, and 0 if it is on the stack.
|
1036 |
|
|
|
1037 |
|
|
Prologue instructions C-code.
|
1038 |
|
|
The prologue may consist of (-fno-omit-frame-pointer)
|
1039 |
|
|
1) 2)
|
1040 |
|
|
push srp
|
1041 |
|
|
push r8 push r8
|
1042 |
|
|
move.d sp,r8 move.d sp,r8
|
1043 |
|
|
subq X,sp subq X,sp
|
1044 |
|
|
movem rY,[sp] movem rY,[sp]
|
1045 |
|
|
move.S rZ,[r8-U] move.S rZ,[r8-U]
|
1046 |
|
|
|
1047 |
|
|
where 1 is a non-terminal function, and 2 is a leaf-function.
|
1048 |
|
|
|
1049 |
|
|
Note that this assumption is extremely brittle, and will break at the
|
1050 |
|
|
slightest change in GCC's prologue.
|
1051 |
|
|
|
1052 |
|
|
If local variables are declared or register contents are saved on stack
|
1053 |
|
|
the subq-instruction will be present with X as the number of bytes
|
1054 |
|
|
needed for storage. The reshuffle with respect to r8 may be performed
|
1055 |
|
|
with any size S (b, w, d) and any of the general registers Z={0..13}.
|
1056 |
|
|
The offset U should be representable by a signed 8-bit value in all cases.
|
1057 |
|
|
Thus, the prefix word is assumed to be immediate byte offset mode followed
|
1058 |
|
|
by another word containing the instruction.
|
1059 |
|
|
|
1060 |
|
|
Degenerate cases:
|
1061 |
|
|
3)
|
1062 |
|
|
push r8
|
1063 |
|
|
move.d sp,r8
|
1064 |
|
|
move.d r8,sp
|
1065 |
|
|
pop r8
|
1066 |
|
|
|
1067 |
|
|
Prologue instructions C++-code.
|
1068 |
|
|
Case 1) and 2) in the C-code may be followed by
|
1069 |
|
|
|
1070 |
|
|
move.d r10,rS ; this
|
1071 |
|
|
move.d r11,rT ; P1
|
1072 |
|
|
move.d r12,rU ; P2
|
1073 |
|
|
move.d r13,rV ; P3
|
1074 |
|
|
move.S [r8+U],rZ ; P4
|
1075 |
|
|
|
1076 |
|
|
if any of the call parameters are stored. The host expects these
|
1077 |
|
|
instructions to be executed in order to get the call parameters right. */
|
1078 |
|
|
|
1079 |
|
|
/* Examine the prologue of a function. The variable ip is the address of
|
1080 |
|
|
the first instruction of the prologue. The variable limit is the address
|
1081 |
|
|
of the first instruction after the prologue. The variable fi contains the
|
1082 |
|
|
information in struct frame_info. The variable frameless_p controls whether
|
1083 |
|
|
the entire prologue is examined (0) or just enough instructions to
|
1084 |
|
|
determine that it is a prologue (1). */
|
1085 |
|
|
|
1086 |
|
|
static CORE_ADDR
|
1087 |
|
|
cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
|
1088 |
|
|
struct cris_unwind_cache *info)
|
1089 |
|
|
{
|
1090 |
|
|
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
1091 |
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
1092 |
|
|
|
1093 |
|
|
/* Present instruction. */
|
1094 |
|
|
unsigned short insn;
|
1095 |
|
|
|
1096 |
|
|
/* Next instruction, lookahead. */
|
1097 |
|
|
unsigned short insn_next;
|
1098 |
|
|
int regno;
|
1099 |
|
|
|
1100 |
|
|
/* Is there a push fp? */
|
1101 |
|
|
int have_fp;
|
1102 |
|
|
|
1103 |
|
|
/* Number of byte on stack used for local variables and movem. */
|
1104 |
|
|
int val;
|
1105 |
|
|
|
1106 |
|
|
/* Highest register number in a movem. */
|
1107 |
|
|
int regsave;
|
1108 |
|
|
|
1109 |
|
|
/* move.d r<source_register>,rS */
|
1110 |
|
|
short source_register;
|
1111 |
|
|
|
1112 |
|
|
/* Scan limit. */
|
1113 |
|
|
int limit;
|
1114 |
|
|
|
1115 |
|
|
/* This frame is with respect to a leaf until a push srp is found. */
|
1116 |
|
|
if (info)
|
1117 |
|
|
{
|
1118 |
|
|
info->leaf_function = 1;
|
1119 |
|
|
}
|
1120 |
|
|
|
1121 |
|
|
/* Assume nothing on stack. */
|
1122 |
|
|
val = 0;
|
1123 |
|
|
regsave = -1;
|
1124 |
|
|
|
1125 |
|
|
/* If we were called without a this_frame, that means we were called
|
1126 |
|
|
from cris_skip_prologue which already tried to find the end of the
|
1127 |
|
|
prologue through the symbol information. 64 instructions past current
|
1128 |
|
|
pc is arbitrarily chosen, but at least it means we'll stop eventually. */
|
1129 |
|
|
limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
|
1130 |
|
|
|
1131 |
|
|
/* Find the prologue instructions. */
|
1132 |
|
|
while (pc > 0 && pc < limit)
|
1133 |
|
|
{
|
1134 |
|
|
insn = read_memory_unsigned_integer (pc, 2, byte_order);
|
1135 |
|
|
pc += 2;
|
1136 |
|
|
if (insn == 0xE1FC)
|
1137 |
|
|
{
|
1138 |
|
|
/* push <reg> 32 bit instruction */
|
1139 |
|
|
insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
|
1140 |
|
|
pc += 2;
|
1141 |
|
|
regno = cris_get_operand2 (insn_next);
|
1142 |
|
|
if (info)
|
1143 |
|
|
{
|
1144 |
|
|
info->sp_offset += 4;
|
1145 |
|
|
}
|
1146 |
|
|
/* This check, meant to recognize srp, used to be regno ==
|
1147 |
|
|
(SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
|
1148 |
|
|
if (insn_next == 0xBE7E)
|
1149 |
|
|
{
|
1150 |
|
|
if (info)
|
1151 |
|
|
{
|
1152 |
|
|
info->leaf_function = 0;
|
1153 |
|
|
}
|
1154 |
|
|
}
|
1155 |
|
|
else if (insn_next == 0x8FEE)
|
1156 |
|
|
{
|
1157 |
|
|
/* push $r8 */
|
1158 |
|
|
if (info)
|
1159 |
|
|
{
|
1160 |
|
|
info->r8_offset = info->sp_offset;
|
1161 |
|
|
}
|
1162 |
|
|
}
|
1163 |
|
|
}
|
1164 |
|
|
else if (insn == 0x866E)
|
1165 |
|
|
{
|
1166 |
|
|
/* move.d sp,r8 */
|
1167 |
|
|
if (info)
|
1168 |
|
|
{
|
1169 |
|
|
info->uses_frame = 1;
|
1170 |
|
|
}
|
1171 |
|
|
continue;
|
1172 |
|
|
}
|
1173 |
|
|
else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
|
1174 |
|
|
&& cris_get_mode (insn) == 0x0000
|
1175 |
|
|
&& cris_get_opcode (insn) == 0x000A)
|
1176 |
|
|
{
|
1177 |
|
|
/* subq <val>,sp */
|
1178 |
|
|
if (info)
|
1179 |
|
|
{
|
1180 |
|
|
info->sp_offset += cris_get_quick_value (insn);
|
1181 |
|
|
}
|
1182 |
|
|
}
|
1183 |
|
|
else if (cris_get_mode (insn) == 0x0002
|
1184 |
|
|
&& cris_get_opcode (insn) == 0x000F
|
1185 |
|
|
&& cris_get_size (insn) == 0x0003
|
1186 |
|
|
&& cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
|
1187 |
|
|
{
|
1188 |
|
|
/* movem r<regsave>,[sp] */
|
1189 |
|
|
regsave = cris_get_operand2 (insn);
|
1190 |
|
|
}
|
1191 |
|
|
else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
|
1192 |
|
|
&& ((insn & 0x0F00) >> 8) == 0x0001
|
1193 |
|
|
&& (cris_get_signed_offset (insn) < 0))
|
1194 |
|
|
{
|
1195 |
|
|
/* Immediate byte offset addressing prefix word with sp as base
|
1196 |
|
|
register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
|
1197 |
|
|
is between 64 and 128.
|
1198 |
|
|
movem r<regsave>,[sp=sp-<val>] */
|
1199 |
|
|
if (info)
|
1200 |
|
|
{
|
1201 |
|
|
info->sp_offset += -cris_get_signed_offset (insn);
|
1202 |
|
|
}
|
1203 |
|
|
insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
|
1204 |
|
|
pc += 2;
|
1205 |
|
|
if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
|
1206 |
|
|
&& cris_get_opcode (insn_next) == 0x000F
|
1207 |
|
|
&& cris_get_size (insn_next) == 0x0003
|
1208 |
|
|
&& cris_get_operand1 (insn_next) == gdbarch_sp_regnum
|
1209 |
|
|
(gdbarch))
|
1210 |
|
|
{
|
1211 |
|
|
regsave = cris_get_operand2 (insn_next);
|
1212 |
|
|
}
|
1213 |
|
|
else
|
1214 |
|
|
{
|
1215 |
|
|
/* The prologue ended before the limit was reached. */
|
1216 |
|
|
pc -= 4;
|
1217 |
|
|
break;
|
1218 |
|
|
}
|
1219 |
|
|
}
|
1220 |
|
|
else if (cris_get_mode (insn) == 0x0001
|
1221 |
|
|
&& cris_get_opcode (insn) == 0x0009
|
1222 |
|
|
&& cris_get_size (insn) == 0x0002)
|
1223 |
|
|
{
|
1224 |
|
|
/* move.d r<10..13>,r<0..15> */
|
1225 |
|
|
source_register = cris_get_operand1 (insn);
|
1226 |
|
|
|
1227 |
|
|
/* FIXME? In the glibc solibs, the prologue might contain something
|
1228 |
|
|
like (this example taken from relocate_doit):
|
1229 |
|
|
move.d $pc,$r0
|
1230 |
|
|
sub.d 0xfffef426,$r0
|
1231 |
|
|
which isn't covered by the source_register check below. Question
|
1232 |
|
|
is whether to add a check for this combo, or make better use of
|
1233 |
|
|
the limit variable instead. */
|
1234 |
|
|
if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
|
1235 |
|
|
{
|
1236 |
|
|
/* The prologue ended before the limit was reached. */
|
1237 |
|
|
pc -= 2;
|
1238 |
|
|
break;
|
1239 |
|
|
}
|
1240 |
|
|
}
|
1241 |
|
|
else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
|
1242 |
|
|
/* The size is a fixed-size. */
|
1243 |
|
|
&& ((insn & 0x0F00) >> 8) == 0x0001
|
1244 |
|
|
/* A negative offset. */
|
1245 |
|
|
&& (cris_get_signed_offset (insn) < 0))
|
1246 |
|
|
{
|
1247 |
|
|
/* move.S rZ,[r8-U] (?) */
|
1248 |
|
|
insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
|
1249 |
|
|
pc += 2;
|
1250 |
|
|
regno = cris_get_operand2 (insn_next);
|
1251 |
|
|
if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
|
1252 |
|
|
&& cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
|
1253 |
|
|
&& cris_get_opcode (insn_next) == 0x000F)
|
1254 |
|
|
{
|
1255 |
|
|
/* move.S rZ,[r8-U] */
|
1256 |
|
|
continue;
|
1257 |
|
|
}
|
1258 |
|
|
else
|
1259 |
|
|
{
|
1260 |
|
|
/* The prologue ended before the limit was reached. */
|
1261 |
|
|
pc -= 4;
|
1262 |
|
|
break;
|
1263 |
|
|
}
|
1264 |
|
|
}
|
1265 |
|
|
else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
|
1266 |
|
|
/* The size is a fixed-size. */
|
1267 |
|
|
&& ((insn & 0x0F00) >> 8) == 0x0001
|
1268 |
|
|
/* A positive offset. */
|
1269 |
|
|
&& (cris_get_signed_offset (insn) > 0))
|
1270 |
|
|
{
|
1271 |
|
|
/* move.S [r8+U],rZ (?) */
|
1272 |
|
|
insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
|
1273 |
|
|
pc += 2;
|
1274 |
|
|
regno = cris_get_operand2 (insn_next);
|
1275 |
|
|
if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
|
1276 |
|
|
&& cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
|
1277 |
|
|
&& cris_get_opcode (insn_next) == 0x0009
|
1278 |
|
|
&& cris_get_operand1 (insn_next) == regno)
|
1279 |
|
|
{
|
1280 |
|
|
/* move.S [r8+U],rZ */
|
1281 |
|
|
continue;
|
1282 |
|
|
}
|
1283 |
|
|
else
|
1284 |
|
|
{
|
1285 |
|
|
/* The prologue ended before the limit was reached. */
|
1286 |
|
|
pc -= 4;
|
1287 |
|
|
break;
|
1288 |
|
|
}
|
1289 |
|
|
}
|
1290 |
|
|
else
|
1291 |
|
|
{
|
1292 |
|
|
/* The prologue ended before the limit was reached. */
|
1293 |
|
|
pc -= 2;
|
1294 |
|
|
break;
|
1295 |
|
|
}
|
1296 |
|
|
}
|
1297 |
|
|
|
1298 |
|
|
/* We only want to know the end of the prologue when this_frame and info
|
1299 |
|
|
are NULL (called from cris_skip_prologue i.e.). */
|
1300 |
|
|
if (this_frame == NULL && info == NULL)
|
1301 |
|
|
{
|
1302 |
|
|
return pc;
|
1303 |
|
|
}
|
1304 |
|
|
|
1305 |
|
|
info->size = info->sp_offset;
|
1306 |
|
|
|
1307 |
|
|
/* Compute the previous frame's stack pointer (which is also the
|
1308 |
|
|
frame's ID's stack address), and this frame's base pointer. */
|
1309 |
|
|
if (info->uses_frame)
|
1310 |
|
|
{
|
1311 |
|
|
ULONGEST this_base;
|
1312 |
|
|
/* The SP was moved to the FP. This indicates that a new frame
|
1313 |
|
|
was created. Get THIS frame's FP value by unwinding it from
|
1314 |
|
|
the next frame. */
|
1315 |
|
|
this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
|
1316 |
|
|
info->base = this_base;
|
1317 |
|
|
info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
|
1318 |
|
|
|
1319 |
|
|
/* The FP points at the last saved register. Adjust the FP back
|
1320 |
|
|
to before the first saved register giving the SP. */
|
1321 |
|
|
info->prev_sp = info->base + info->r8_offset;
|
1322 |
|
|
}
|
1323 |
|
|
else
|
1324 |
|
|
{
|
1325 |
|
|
ULONGEST this_base;
|
1326 |
|
|
/* Assume that the FP is this frame's SP but with that pushed
|
1327 |
|
|
stack space added back. */
|
1328 |
|
|
this_base = get_frame_register_unsigned (this_frame,
|
1329 |
|
|
gdbarch_sp_regnum (gdbarch));
|
1330 |
|
|
info->base = this_base;
|
1331 |
|
|
info->prev_sp = info->base + info->size;
|
1332 |
|
|
}
|
1333 |
|
|
|
1334 |
|
|
/* Calculate the addresses for the saved registers on the stack. */
|
1335 |
|
|
/* FIXME: The address calculation should really be done on the fly while
|
1336 |
|
|
we're analyzing the prologue (we only hold one regsave value as it is
|
1337 |
|
|
now). */
|
1338 |
|
|
val = info->sp_offset;
|
1339 |
|
|
|
1340 |
|
|
for (regno = regsave; regno >= 0; regno--)
|
1341 |
|
|
{
|
1342 |
|
|
info->saved_regs[regno].addr = info->base + info->r8_offset - val;
|
1343 |
|
|
val -= 4;
|
1344 |
|
|
}
|
1345 |
|
|
|
1346 |
|
|
/* The previous frame's SP needed to be computed. Save the computed
|
1347 |
|
|
value. */
|
1348 |
|
|
trad_frame_set_value (info->saved_regs,
|
1349 |
|
|
gdbarch_sp_regnum (gdbarch), info->prev_sp);
|
1350 |
|
|
|
1351 |
|
|
if (!info->leaf_function)
|
1352 |
|
|
{
|
1353 |
|
|
/* SRP saved on the stack. But where? */
|
1354 |
|
|
if (info->r8_offset == 0)
|
1355 |
|
|
{
|
1356 |
|
|
/* R8 not pushed yet. */
|
1357 |
|
|
info->saved_regs[SRP_REGNUM].addr = info->base;
|
1358 |
|
|
}
|
1359 |
|
|
else
|
1360 |
|
|
{
|
1361 |
|
|
/* R8 pushed, but SP may or may not be moved to R8 yet. */
|
1362 |
|
|
info->saved_regs[SRP_REGNUM].addr = info->base + 4;
|
1363 |
|
|
}
|
1364 |
|
|
}
|
1365 |
|
|
|
1366 |
|
|
/* The PC is found in SRP (the actual register or located on the stack). */
|
1367 |
|
|
info->saved_regs[gdbarch_pc_regnum (gdbarch)]
|
1368 |
|
|
= info->saved_regs[SRP_REGNUM];
|
1369 |
|
|
|
1370 |
|
|
return pc;
|
1371 |
|
|
}
|
1372 |
|
|
|
1373 |
|
|
static CORE_ADDR
|
1374 |
|
|
crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
|
1375 |
|
|
struct cris_unwind_cache *info)
|
1376 |
|
|
{
|
1377 |
|
|
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
1378 |
|
|
ULONGEST this_base;
|
1379 |
|
|
|
1380 |
|
|
/* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
|
1381 |
|
|
meant to be a full-fledged prologue scanner. It is only needed for
|
1382 |
|
|
the cases where we end up in code always lacking DWARF-2 CFI, notably:
|
1383 |
|
|
|
1384 |
|
|
* PLT stubs (library calls)
|
1385 |
|
|
* call dummys
|
1386 |
|
|
* signal trampolines
|
1387 |
|
|
|
1388 |
|
|
For those cases, it is assumed that there is no actual prologue; that
|
1389 |
|
|
the stack pointer is not adjusted, and (as a consequence) the return
|
1390 |
|
|
address is not pushed onto the stack. */
|
1391 |
|
|
|
1392 |
|
|
/* We only want to know the end of the prologue when this_frame and info
|
1393 |
|
|
are NULL (called from cris_skip_prologue i.e.). */
|
1394 |
|
|
if (this_frame == NULL && info == NULL)
|
1395 |
|
|
{
|
1396 |
|
|
return pc;
|
1397 |
|
|
}
|
1398 |
|
|
|
1399 |
|
|
/* The SP is assumed to be unaltered. */
|
1400 |
|
|
this_base = get_frame_register_unsigned (this_frame,
|
1401 |
|
|
gdbarch_sp_regnum (gdbarch));
|
1402 |
|
|
info->base = this_base;
|
1403 |
|
|
info->prev_sp = this_base;
|
1404 |
|
|
|
1405 |
|
|
/* The PC is assumed to be found in SRP. */
|
1406 |
|
|
info->saved_regs[gdbarch_pc_regnum (gdbarch)]
|
1407 |
|
|
= info->saved_regs[SRP_REGNUM];
|
1408 |
|
|
|
1409 |
|
|
return pc;
|
1410 |
|
|
}
|
1411 |
|
|
|
1412 |
|
|
/* Advance pc beyond any function entry prologue instructions at pc
|
1413 |
|
|
to reach some "real" code. */
|
1414 |
|
|
|
1415 |
|
|
/* Given a PC value corresponding to the start of a function, return the PC
|
1416 |
|
|
of the first instruction after the function prologue. */
|
1417 |
|
|
|
1418 |
|
|
static CORE_ADDR
|
1419 |
|
|
cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
|
1420 |
|
|
{
|
1421 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
1422 |
|
|
CORE_ADDR func_addr, func_end;
|
1423 |
|
|
struct symtab_and_line sal;
|
1424 |
|
|
CORE_ADDR pc_after_prologue;
|
1425 |
|
|
|
1426 |
|
|
/* If we have line debugging information, then the end of the prologue
|
1427 |
|
|
should the first assembly instruction of the first source line. */
|
1428 |
|
|
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
|
1429 |
|
|
{
|
1430 |
|
|
sal = find_pc_line (func_addr, 0);
|
1431 |
|
|
if (sal.end > 0 && sal.end < func_end)
|
1432 |
|
|
return sal.end;
|
1433 |
|
|
}
|
1434 |
|
|
|
1435 |
|
|
if (tdep->cris_version == 32)
|
1436 |
|
|
pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
|
1437 |
|
|
else
|
1438 |
|
|
pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
|
1439 |
|
|
|
1440 |
|
|
return pc_after_prologue;
|
1441 |
|
|
}
|
1442 |
|
|
|
1443 |
|
|
static CORE_ADDR
|
1444 |
|
|
cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
1445 |
|
|
{
|
1446 |
|
|
ULONGEST pc;
|
1447 |
|
|
pc = frame_unwind_register_unsigned (next_frame,
|
1448 |
|
|
gdbarch_pc_regnum (gdbarch));
|
1449 |
|
|
return pc;
|
1450 |
|
|
}
|
1451 |
|
|
|
1452 |
|
|
static CORE_ADDR
|
1453 |
|
|
cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
1454 |
|
|
{
|
1455 |
|
|
ULONGEST sp;
|
1456 |
|
|
sp = frame_unwind_register_unsigned (next_frame,
|
1457 |
|
|
gdbarch_sp_regnum (gdbarch));
|
1458 |
|
|
return sp;
|
1459 |
|
|
}
|
1460 |
|
|
|
1461 |
|
|
/* Use the program counter to determine the contents and size of a breakpoint
|
1462 |
|
|
instruction. It returns a pointer to a string of bytes that encode a
|
1463 |
|
|
breakpoint instruction, stores the length of the string to *lenptr, and
|
1464 |
|
|
adjusts pcptr (if necessary) to point to the actual memory location where
|
1465 |
|
|
the breakpoint should be inserted. */
|
1466 |
|
|
|
1467 |
|
|
static const unsigned char *
|
1468 |
|
|
cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
|
1469 |
|
|
{
|
1470 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
1471 |
|
|
static unsigned char break8_insn[] = {0x38, 0xe9};
|
1472 |
|
|
static unsigned char break15_insn[] = {0x3f, 0xe9};
|
1473 |
|
|
*lenptr = 2;
|
1474 |
|
|
|
1475 |
|
|
if (tdep->cris_mode == cris_mode_guru)
|
1476 |
|
|
return break15_insn;
|
1477 |
|
|
else
|
1478 |
|
|
return break8_insn;
|
1479 |
|
|
}
|
1480 |
|
|
|
1481 |
|
|
/* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
|
1482 |
|
|
|
1483 |
|
|
|
1484 |
|
|
static int
|
1485 |
|
|
cris_spec_reg_applicable (struct gdbarch *gdbarch,
|
1486 |
|
|
struct cris_spec_reg spec_reg)
|
1487 |
|
|
{
|
1488 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
1489 |
|
|
int version = tdep->cris_version;
|
1490 |
|
|
|
1491 |
|
|
switch (spec_reg.applicable_version)
|
1492 |
|
|
{
|
1493 |
|
|
case cris_ver_version_all:
|
1494 |
|
|
return 1;
|
1495 |
|
|
case cris_ver_warning:
|
1496 |
|
|
/* Indeterminate/obsolete. */
|
1497 |
|
|
return 0;
|
1498 |
|
|
case cris_ver_v0_3:
|
1499 |
|
|
return (version >= 0 && version <= 3);
|
1500 |
|
|
case cris_ver_v3p:
|
1501 |
|
|
return (version >= 3);
|
1502 |
|
|
case cris_ver_v8:
|
1503 |
|
|
return (version == 8 || version == 9);
|
1504 |
|
|
case cris_ver_v8p:
|
1505 |
|
|
return (version >= 8);
|
1506 |
|
|
case cris_ver_v0_10:
|
1507 |
|
|
return (version >= 0 && version <= 10);
|
1508 |
|
|
case cris_ver_v3_10:
|
1509 |
|
|
return (version >= 3 && version <= 10);
|
1510 |
|
|
case cris_ver_v8_10:
|
1511 |
|
|
return (version >= 8 && version <= 10);
|
1512 |
|
|
case cris_ver_v10:
|
1513 |
|
|
return (version == 10);
|
1514 |
|
|
case cris_ver_v10p:
|
1515 |
|
|
return (version >= 10);
|
1516 |
|
|
case cris_ver_v32p:
|
1517 |
|
|
return (version >= 32);
|
1518 |
|
|
default:
|
1519 |
|
|
/* Invalid cris version. */
|
1520 |
|
|
return 0;
|
1521 |
|
|
}
|
1522 |
|
|
}
|
1523 |
|
|
|
1524 |
|
|
/* Returns the register size in unit byte. Returns 0 for an unimplemented
|
1525 |
|
|
register, -1 for an invalid register. */
|
1526 |
|
|
|
1527 |
|
|
static int
|
1528 |
|
|
cris_register_size (struct gdbarch *gdbarch, int regno)
|
1529 |
|
|
{
|
1530 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
1531 |
|
|
int i;
|
1532 |
|
|
int spec_regno;
|
1533 |
|
|
|
1534 |
|
|
if (regno >= 0 && regno < NUM_GENREGS)
|
1535 |
|
|
{
|
1536 |
|
|
/* General registers (R0 - R15) are 32 bits. */
|
1537 |
|
|
return 4;
|
1538 |
|
|
}
|
1539 |
|
|
else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
|
1540 |
|
|
{
|
1541 |
|
|
/* Special register (R16 - R31). cris_spec_regs is zero-based.
|
1542 |
|
|
Adjust regno accordingly. */
|
1543 |
|
|
spec_regno = regno - NUM_GENREGS;
|
1544 |
|
|
|
1545 |
|
|
for (i = 0; cris_spec_regs[i].name != NULL; i++)
|
1546 |
|
|
{
|
1547 |
|
|
if (cris_spec_regs[i].number == spec_regno
|
1548 |
|
|
&& cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
|
1549 |
|
|
/* Go with the first applicable register. */
|
1550 |
|
|
return cris_spec_regs[i].reg_size;
|
1551 |
|
|
}
|
1552 |
|
|
/* Special register not applicable to this CRIS version. */
|
1553 |
|
|
return 0;
|
1554 |
|
|
}
|
1555 |
|
|
else if (regno >= gdbarch_pc_regnum (gdbarch)
|
1556 |
|
|
&& regno < gdbarch_num_regs (gdbarch))
|
1557 |
|
|
{
|
1558 |
|
|
/* This will apply to CRISv32 only where there are additional registers
|
1559 |
|
|
after the special registers (pseudo PC and support registers). */
|
1560 |
|
|
return 4;
|
1561 |
|
|
}
|
1562 |
|
|
|
1563 |
|
|
|
1564 |
|
|
return -1;
|
1565 |
|
|
}
|
1566 |
|
|
|
1567 |
|
|
/* Nonzero if regno should not be fetched from the target. This is the case
|
1568 |
|
|
for unimplemented (size 0) and non-existant registers. */
|
1569 |
|
|
|
1570 |
|
|
static int
|
1571 |
|
|
cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
|
1572 |
|
|
{
|
1573 |
|
|
return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
|
1574 |
|
|
|| (cris_register_size (gdbarch, regno) == 0));
|
1575 |
|
|
}
|
1576 |
|
|
|
1577 |
|
|
/* Nonzero if regno should not be written to the target, for various
|
1578 |
|
|
reasons. */
|
1579 |
|
|
|
1580 |
|
|
static int
|
1581 |
|
|
cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
|
1582 |
|
|
{
|
1583 |
|
|
/* There are three kinds of registers we refuse to write to.
|
1584 |
|
|
1. Those that not implemented.
|
1585 |
|
|
2. Those that are read-only (depends on the processor mode).
|
1586 |
|
|
3. Those registers to which a write has no effect.
|
1587 |
|
|
*/
|
1588 |
|
|
|
1589 |
|
|
if (regno < 0
|
1590 |
|
|
|| regno >= gdbarch_num_regs (gdbarch)
|
1591 |
|
|
|| cris_register_size (gdbarch, regno) == 0)
|
1592 |
|
|
/* Not implemented. */
|
1593 |
|
|
return 1;
|
1594 |
|
|
|
1595 |
|
|
else if (regno == VR_REGNUM)
|
1596 |
|
|
/* Read-only. */
|
1597 |
|
|
return 1;
|
1598 |
|
|
|
1599 |
|
|
else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
|
1600 |
|
|
/* Writing has no effect. */
|
1601 |
|
|
return 1;
|
1602 |
|
|
|
1603 |
|
|
/* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
|
1604 |
|
|
agent decide whether they are writable. */
|
1605 |
|
|
|
1606 |
|
|
return 0;
|
1607 |
|
|
}
|
1608 |
|
|
|
1609 |
|
|
/* Nonzero if regno should not be fetched from the target. This is the case
|
1610 |
|
|
for unimplemented (size 0) and non-existant registers. */
|
1611 |
|
|
|
1612 |
|
|
static int
|
1613 |
|
|
crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
|
1614 |
|
|
{
|
1615 |
|
|
return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
|
1616 |
|
|
|| (cris_register_size (gdbarch, regno) == 0));
|
1617 |
|
|
}
|
1618 |
|
|
|
1619 |
|
|
/* Nonzero if regno should not be written to the target, for various
|
1620 |
|
|
reasons. */
|
1621 |
|
|
|
1622 |
|
|
static int
|
1623 |
|
|
crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
|
1624 |
|
|
{
|
1625 |
|
|
/* There are three kinds of registers we refuse to write to.
|
1626 |
|
|
1. Those that not implemented.
|
1627 |
|
|
2. Those that are read-only (depends on the processor mode).
|
1628 |
|
|
3. Those registers to which a write has no effect.
|
1629 |
|
|
*/
|
1630 |
|
|
|
1631 |
|
|
if (regno < 0
|
1632 |
|
|
|| regno >= gdbarch_num_regs (gdbarch)
|
1633 |
|
|
|| cris_register_size (gdbarch, regno) == 0)
|
1634 |
|
|
/* Not implemented. */
|
1635 |
|
|
return 1;
|
1636 |
|
|
|
1637 |
|
|
else if (regno == VR_REGNUM)
|
1638 |
|
|
/* Read-only. */
|
1639 |
|
|
return 1;
|
1640 |
|
|
|
1641 |
|
|
else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
|
1642 |
|
|
/* Writing has no effect. */
|
1643 |
|
|
return 1;
|
1644 |
|
|
|
1645 |
|
|
/* Many special registers are read-only in user mode. Let the debug
|
1646 |
|
|
agent decide whether they are writable. */
|
1647 |
|
|
|
1648 |
|
|
return 0;
|
1649 |
|
|
}
|
1650 |
|
|
|
1651 |
|
|
/* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
|
1652 |
|
|
of data in register regno. */
|
1653 |
|
|
|
1654 |
|
|
static struct type *
|
1655 |
|
|
cris_register_type (struct gdbarch *gdbarch, int regno)
|
1656 |
|
|
{
|
1657 |
|
|
if (regno == gdbarch_pc_regnum (gdbarch))
|
1658 |
|
|
return builtin_type (gdbarch)->builtin_func_ptr;
|
1659 |
|
|
else if (regno == gdbarch_sp_regnum (gdbarch)
|
1660 |
|
|
|| regno == CRIS_FP_REGNUM)
|
1661 |
|
|
return builtin_type (gdbarch)->builtin_data_ptr;
|
1662 |
|
|
else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
|
1663 |
|
|
|| (regno >= MOF_REGNUM && regno <= USP_REGNUM))
|
1664 |
|
|
/* Note: R8 taken care of previous clause. */
|
1665 |
|
|
return builtin_type (gdbarch)->builtin_uint32;
|
1666 |
|
|
else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
|
1667 |
|
|
return builtin_type (gdbarch)->builtin_uint16;
|
1668 |
|
|
else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
|
1669 |
|
|
return builtin_type (gdbarch)->builtin_uint8;
|
1670 |
|
|
else
|
1671 |
|
|
/* Invalid (unimplemented) register. */
|
1672 |
|
|
return builtin_type (gdbarch)->builtin_int0;
|
1673 |
|
|
}
|
1674 |
|
|
|
1675 |
|
|
static struct type *
|
1676 |
|
|
crisv32_register_type (struct gdbarch *gdbarch, int regno)
|
1677 |
|
|
{
|
1678 |
|
|
if (regno == gdbarch_pc_regnum (gdbarch))
|
1679 |
|
|
return builtin_type (gdbarch)->builtin_func_ptr;
|
1680 |
|
|
else if (regno == gdbarch_sp_regnum (gdbarch)
|
1681 |
|
|
|| regno == CRIS_FP_REGNUM)
|
1682 |
|
|
return builtin_type (gdbarch)->builtin_data_ptr;
|
1683 |
|
|
else if ((regno >= 0 && regno <= ACR_REGNUM)
|
1684 |
|
|
|| (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
|
1685 |
|
|
|| (regno == PID_REGNUM)
|
1686 |
|
|
|| (regno >= S0_REGNUM && regno <= S15_REGNUM))
|
1687 |
|
|
/* Note: R8 and SP taken care of by previous clause. */
|
1688 |
|
|
return builtin_type (gdbarch)->builtin_uint32;
|
1689 |
|
|
else if (regno == WZ_REGNUM)
|
1690 |
|
|
return builtin_type (gdbarch)->builtin_uint16;
|
1691 |
|
|
else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
|
1692 |
|
|
return builtin_type (gdbarch)->builtin_uint8;
|
1693 |
|
|
else
|
1694 |
|
|
{
|
1695 |
|
|
/* Invalid (unimplemented) register. Should not happen as there are
|
1696 |
|
|
no unimplemented CRISv32 registers. */
|
1697 |
|
|
warning (_("crisv32_register_type: unknown regno %d"), regno);
|
1698 |
|
|
return builtin_type (gdbarch)->builtin_int0;
|
1699 |
|
|
}
|
1700 |
|
|
}
|
1701 |
|
|
|
1702 |
|
|
/* Stores a function return value of type type, where valbuf is the address
|
1703 |
|
|
of the value to be stored. */
|
1704 |
|
|
|
1705 |
|
|
/* In the CRIS ABI, R10 and R11 are used to store return values. */
|
1706 |
|
|
|
1707 |
|
|
static void
|
1708 |
|
|
cris_store_return_value (struct type *type, struct regcache *regcache,
|
1709 |
|
|
const void *valbuf)
|
1710 |
|
|
{
|
1711 |
|
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
1712 |
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
1713 |
|
|
ULONGEST val;
|
1714 |
|
|
int len = TYPE_LENGTH (type);
|
1715 |
|
|
|
1716 |
|
|
if (len <= 4)
|
1717 |
|
|
{
|
1718 |
|
|
/* Put the return value in R10. */
|
1719 |
|
|
val = extract_unsigned_integer (valbuf, len, byte_order);
|
1720 |
|
|
regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
|
1721 |
|
|
}
|
1722 |
|
|
else if (len <= 8)
|
1723 |
|
|
{
|
1724 |
|
|
/* Put the return value in R10 and R11. */
|
1725 |
|
|
val = extract_unsigned_integer (valbuf, 4, byte_order);
|
1726 |
|
|
regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
|
1727 |
|
|
val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order);
|
1728 |
|
|
regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
|
1729 |
|
|
}
|
1730 |
|
|
else
|
1731 |
|
|
error (_("cris_store_return_value: type length too large."));
|
1732 |
|
|
}
|
1733 |
|
|
|
1734 |
|
|
/* Return the name of register regno as a string. Return NULL for an invalid or
|
1735 |
|
|
unimplemented register. */
|
1736 |
|
|
|
1737 |
|
|
static const char *
|
1738 |
|
|
cris_special_register_name (struct gdbarch *gdbarch, int regno)
|
1739 |
|
|
{
|
1740 |
|
|
int spec_regno;
|
1741 |
|
|
int i;
|
1742 |
|
|
|
1743 |
|
|
/* Special register (R16 - R31). cris_spec_regs is zero-based.
|
1744 |
|
|
Adjust regno accordingly. */
|
1745 |
|
|
spec_regno = regno - NUM_GENREGS;
|
1746 |
|
|
|
1747 |
|
|
/* Assume nothing about the layout of the cris_spec_regs struct
|
1748 |
|
|
when searching. */
|
1749 |
|
|
for (i = 0; cris_spec_regs[i].name != NULL; i++)
|
1750 |
|
|
{
|
1751 |
|
|
if (cris_spec_regs[i].number == spec_regno
|
1752 |
|
|
&& cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
|
1753 |
|
|
/* Go with the first applicable register. */
|
1754 |
|
|
return cris_spec_regs[i].name;
|
1755 |
|
|
}
|
1756 |
|
|
/* Special register not applicable to this CRIS version. */
|
1757 |
|
|
return NULL;
|
1758 |
|
|
}
|
1759 |
|
|
|
1760 |
|
|
static const char *
|
1761 |
|
|
cris_register_name (struct gdbarch *gdbarch, int regno)
|
1762 |
|
|
{
|
1763 |
|
|
static char *cris_genreg_names[] =
|
1764 |
|
|
{ "r0", "r1", "r2", "r3", \
|
1765 |
|
|
"r4", "r5", "r6", "r7", \
|
1766 |
|
|
"r8", "r9", "r10", "r11", \
|
1767 |
|
|
"r12", "r13", "sp", "pc" };
|
1768 |
|
|
|
1769 |
|
|
if (regno >= 0 && regno < NUM_GENREGS)
|
1770 |
|
|
{
|
1771 |
|
|
/* General register. */
|
1772 |
|
|
return cris_genreg_names[regno];
|
1773 |
|
|
}
|
1774 |
|
|
else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
|
1775 |
|
|
{
|
1776 |
|
|
return cris_special_register_name (gdbarch, regno);
|
1777 |
|
|
}
|
1778 |
|
|
else
|
1779 |
|
|
{
|
1780 |
|
|
/* Invalid register. */
|
1781 |
|
|
return NULL;
|
1782 |
|
|
}
|
1783 |
|
|
}
|
1784 |
|
|
|
1785 |
|
|
static const char *
|
1786 |
|
|
crisv32_register_name (struct gdbarch *gdbarch, int regno)
|
1787 |
|
|
{
|
1788 |
|
|
static char *crisv32_genreg_names[] =
|
1789 |
|
|
{ "r0", "r1", "r2", "r3", \
|
1790 |
|
|
"r4", "r5", "r6", "r7", \
|
1791 |
|
|
"r8", "r9", "r10", "r11", \
|
1792 |
|
|
"r12", "r13", "sp", "acr"
|
1793 |
|
|
};
|
1794 |
|
|
|
1795 |
|
|
static char *crisv32_sreg_names[] =
|
1796 |
|
|
{ "s0", "s1", "s2", "s3", \
|
1797 |
|
|
"s4", "s5", "s6", "s7", \
|
1798 |
|
|
"s8", "s9", "s10", "s11", \
|
1799 |
|
|
"s12", "s13", "s14", "s15"
|
1800 |
|
|
};
|
1801 |
|
|
|
1802 |
|
|
if (regno >= 0 && regno < NUM_GENREGS)
|
1803 |
|
|
{
|
1804 |
|
|
/* General register. */
|
1805 |
|
|
return crisv32_genreg_names[regno];
|
1806 |
|
|
}
|
1807 |
|
|
else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
|
1808 |
|
|
{
|
1809 |
|
|
return cris_special_register_name (gdbarch, regno);
|
1810 |
|
|
}
|
1811 |
|
|
else if (regno == gdbarch_pc_regnum (gdbarch))
|
1812 |
|
|
{
|
1813 |
|
|
return "pc";
|
1814 |
|
|
}
|
1815 |
|
|
else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
|
1816 |
|
|
{
|
1817 |
|
|
return crisv32_sreg_names[regno - S0_REGNUM];
|
1818 |
|
|
}
|
1819 |
|
|
else
|
1820 |
|
|
{
|
1821 |
|
|
/* Invalid register. */
|
1822 |
|
|
return NULL;
|
1823 |
|
|
}
|
1824 |
|
|
}
|
1825 |
|
|
|
1826 |
|
|
/* Convert DWARF register number REG to the appropriate register
|
1827 |
|
|
number used by GDB. */
|
1828 |
|
|
|
1829 |
|
|
static int
|
1830 |
|
|
cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
|
1831 |
|
|
{
|
1832 |
|
|
/* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
|
1833 |
|
|
numbering, MOF is 18).
|
1834 |
|
|
Adapted from gcc/config/cris/cris.h. */
|
1835 |
|
|
static int cris_dwarf_regmap[] = {
|
1836 |
|
|
0, 1, 2, 3,
|
1837 |
|
|
4, 5, 6, 7,
|
1838 |
|
|
8, 9, 10, 11,
|
1839 |
|
|
12, 13, 14, 15,
|
1840 |
|
|
27, -1, -1, -1,
|
1841 |
|
|
-1, -1, -1, 23,
|
1842 |
|
|
-1, -1, -1, 27,
|
1843 |
|
|
-1, -1, -1, -1
|
1844 |
|
|
};
|
1845 |
|
|
int regnum = -1;
|
1846 |
|
|
|
1847 |
|
|
if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
|
1848 |
|
|
regnum = cris_dwarf_regmap[reg];
|
1849 |
|
|
|
1850 |
|
|
if (regnum == -1)
|
1851 |
|
|
warning (_("Unmapped DWARF Register #%d encountered."), reg);
|
1852 |
|
|
|
1853 |
|
|
return regnum;
|
1854 |
|
|
}
|
1855 |
|
|
|
1856 |
|
|
/* DWARF-2 frame support. */
|
1857 |
|
|
|
1858 |
|
|
static void
|
1859 |
|
|
cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
|
1860 |
|
|
struct dwarf2_frame_state_reg *reg,
|
1861 |
|
|
struct frame_info *this_frame)
|
1862 |
|
|
{
|
1863 |
|
|
/* The return address column. */
|
1864 |
|
|
if (regnum == gdbarch_pc_regnum (gdbarch))
|
1865 |
|
|
reg->how = DWARF2_FRAME_REG_RA;
|
1866 |
|
|
|
1867 |
|
|
/* The call frame address. */
|
1868 |
|
|
else if (regnum == gdbarch_sp_regnum (gdbarch))
|
1869 |
|
|
reg->how = DWARF2_FRAME_REG_CFA;
|
1870 |
|
|
}
|
1871 |
|
|
|
1872 |
|
|
/* Extract from an array regbuf containing the raw register state a function
|
1873 |
|
|
return value of type type, and copy that, in virtual format, into
|
1874 |
|
|
valbuf. */
|
1875 |
|
|
|
1876 |
|
|
/* In the CRIS ABI, R10 and R11 are used to store return values. */
|
1877 |
|
|
|
1878 |
|
|
static void
|
1879 |
|
|
cris_extract_return_value (struct type *type, struct regcache *regcache,
|
1880 |
|
|
void *valbuf)
|
1881 |
|
|
{
|
1882 |
|
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
1883 |
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
1884 |
|
|
ULONGEST val;
|
1885 |
|
|
int len = TYPE_LENGTH (type);
|
1886 |
|
|
|
1887 |
|
|
if (len <= 4)
|
1888 |
|
|
{
|
1889 |
|
|
/* Get the return value from R10. */
|
1890 |
|
|
regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
|
1891 |
|
|
store_unsigned_integer (valbuf, len, byte_order, val);
|
1892 |
|
|
}
|
1893 |
|
|
else if (len <= 8)
|
1894 |
|
|
{
|
1895 |
|
|
/* Get the return value from R10 and R11. */
|
1896 |
|
|
regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
|
1897 |
|
|
store_unsigned_integer (valbuf, 4, byte_order, val);
|
1898 |
|
|
regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
|
1899 |
|
|
store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val);
|
1900 |
|
|
}
|
1901 |
|
|
else
|
1902 |
|
|
error (_("cris_extract_return_value: type length too large"));
|
1903 |
|
|
}
|
1904 |
|
|
|
1905 |
|
|
/* Handle the CRIS return value convention. */
|
1906 |
|
|
|
1907 |
|
|
static enum return_value_convention
|
1908 |
|
|
cris_return_value (struct gdbarch *gdbarch, struct type *func_type,
|
1909 |
|
|
struct type *type, struct regcache *regcache,
|
1910 |
|
|
gdb_byte *readbuf, const gdb_byte *writebuf)
|
1911 |
|
|
{
|
1912 |
|
|
if (TYPE_CODE (type) == TYPE_CODE_STRUCT
|
1913 |
|
|
|| TYPE_CODE (type) == TYPE_CODE_UNION
|
1914 |
|
|
|| TYPE_LENGTH (type) > 8)
|
1915 |
|
|
/* Structs, unions, and anything larger than 8 bytes (2 registers)
|
1916 |
|
|
goes on the stack. */
|
1917 |
|
|
return RETURN_VALUE_STRUCT_CONVENTION;
|
1918 |
|
|
|
1919 |
|
|
if (readbuf)
|
1920 |
|
|
cris_extract_return_value (type, regcache, readbuf);
|
1921 |
|
|
if (writebuf)
|
1922 |
|
|
cris_store_return_value (type, regcache, writebuf);
|
1923 |
|
|
|
1924 |
|
|
return RETURN_VALUE_REGISTER_CONVENTION;
|
1925 |
|
|
}
|
1926 |
|
|
|
1927 |
|
|
/* Calculates a value that measures how good inst_args constraints an
|
1928 |
|
|
instruction. It stems from cris_constraint, found in cris-dis.c. */
|
1929 |
|
|
|
1930 |
|
|
static int
|
1931 |
|
|
constraint (unsigned int insn, const signed char *inst_args,
|
1932 |
|
|
inst_env_type *inst_env)
|
1933 |
|
|
{
|
1934 |
|
|
int retval = 0;
|
1935 |
|
|
int tmp, i;
|
1936 |
|
|
|
1937 |
|
|
const char *s = inst_args;
|
1938 |
|
|
|
1939 |
|
|
for (; *s; s++)
|
1940 |
|
|
switch (*s)
|
1941 |
|
|
{
|
1942 |
|
|
case 'm':
|
1943 |
|
|
if ((insn & 0x30) == 0x30)
|
1944 |
|
|
return -1;
|
1945 |
|
|
break;
|
1946 |
|
|
|
1947 |
|
|
case 'S':
|
1948 |
|
|
/* A prefix operand. */
|
1949 |
|
|
if (inst_env->prefix_found)
|
1950 |
|
|
break;
|
1951 |
|
|
else
|
1952 |
|
|
return -1;
|
1953 |
|
|
|
1954 |
|
|
case 'B':
|
1955 |
|
|
/* A "push" prefix. (This check was REMOVED by san 970921.) Check for
|
1956 |
|
|
valid "push" size. In case of special register, it may be != 4. */
|
1957 |
|
|
if (inst_env->prefix_found)
|
1958 |
|
|
break;
|
1959 |
|
|
else
|
1960 |
|
|
return -1;
|
1961 |
|
|
|
1962 |
|
|
case 'D':
|
1963 |
|
|
retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
|
1964 |
|
|
if (!retval)
|
1965 |
|
|
return -1;
|
1966 |
|
|
else
|
1967 |
|
|
retval += 4;
|
1968 |
|
|
break;
|
1969 |
|
|
|
1970 |
|
|
case 'P':
|
1971 |
|
|
tmp = (insn >> 0xC) & 0xF;
|
1972 |
|
|
|
1973 |
|
|
for (i = 0; cris_spec_regs[i].name != NULL; i++)
|
1974 |
|
|
{
|
1975 |
|
|
/* Since we match four bits, we will give a value of
|
1976 |
|
|
4 - 1 = 3 in a match. If there is a corresponding
|
1977 |
|
|
exact match of a special register in another pattern, it
|
1978 |
|
|
will get a value of 4, which will be higher. This should
|
1979 |
|
|
be correct in that an exact pattern would match better that
|
1980 |
|
|
a general pattern.
|
1981 |
|
|
Note that there is a reason for not returning zero; the
|
1982 |
|
|
pattern for "clear" is partly matched in the bit-pattern
|
1983 |
|
|
(the two lower bits must be zero), while the bit-pattern
|
1984 |
|
|
for a move from a special register is matched in the
|
1985 |
|
|
register constraint.
|
1986 |
|
|
This also means we will will have a race condition if
|
1987 |
|
|
there is a partly match in three bits in the bit pattern. */
|
1988 |
|
|
if (tmp == cris_spec_regs[i].number)
|
1989 |
|
|
{
|
1990 |
|
|
retval += 3;
|
1991 |
|
|
break;
|
1992 |
|
|
}
|
1993 |
|
|
}
|
1994 |
|
|
|
1995 |
|
|
if (cris_spec_regs[i].name == NULL)
|
1996 |
|
|
return -1;
|
1997 |
|
|
break;
|
1998 |
|
|
}
|
1999 |
|
|
return retval;
|
2000 |
|
|
}
|
2001 |
|
|
|
2002 |
|
|
/* Returns the number of bits set in the variable value. */
|
2003 |
|
|
|
2004 |
|
|
static int
|
2005 |
|
|
number_of_bits (unsigned int value)
|
2006 |
|
|
{
|
2007 |
|
|
int number_of_bits = 0;
|
2008 |
|
|
|
2009 |
|
|
while (value != 0)
|
2010 |
|
|
{
|
2011 |
|
|
number_of_bits += 1;
|
2012 |
|
|
value &= (value - 1);
|
2013 |
|
|
}
|
2014 |
|
|
return number_of_bits;
|
2015 |
|
|
}
|
2016 |
|
|
|
2017 |
|
|
/* Finds the address that should contain the single step breakpoint(s).
|
2018 |
|
|
It stems from code in cris-dis.c. */
|
2019 |
|
|
|
2020 |
|
|
static int
|
2021 |
|
|
find_cris_op (unsigned short insn, inst_env_type *inst_env)
|
2022 |
|
|
{
|
2023 |
|
|
int i;
|
2024 |
|
|
int max_level_of_match = -1;
|
2025 |
|
|
int max_matched = -1;
|
2026 |
|
|
int level_of_match;
|
2027 |
|
|
|
2028 |
|
|
for (i = 0; cris_opcodes[i].name != NULL; i++)
|
2029 |
|
|
{
|
2030 |
|
|
if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
|
2031 |
|
|
&& ((cris_opcodes[i].lose & insn) == 0)
|
2032 |
|
|
/* Only CRISv10 instructions, please. */
|
2033 |
|
|
&& (cris_opcodes[i].applicable_version != cris_ver_v32p))
|
2034 |
|
|
{
|
2035 |
|
|
level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
|
2036 |
|
|
if (level_of_match >= 0)
|
2037 |
|
|
{
|
2038 |
|
|
level_of_match +=
|
2039 |
|
|
number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
|
2040 |
|
|
if (level_of_match > max_level_of_match)
|
2041 |
|
|
{
|
2042 |
|
|
max_matched = i;
|
2043 |
|
|
max_level_of_match = level_of_match;
|
2044 |
|
|
if (level_of_match == 16)
|
2045 |
|
|
{
|
2046 |
|
|
/* All bits matched, cannot find better. */
|
2047 |
|
|
break;
|
2048 |
|
|
}
|
2049 |
|
|
}
|
2050 |
|
|
}
|
2051 |
|
|
}
|
2052 |
|
|
}
|
2053 |
|
|
return max_matched;
|
2054 |
|
|
}
|
2055 |
|
|
|
2056 |
|
|
/* Attempts to find single-step breakpoints. Returns -1 on failure which is
|
2057 |
|
|
actually an internal error. */
|
2058 |
|
|
|
2059 |
|
|
static int
|
2060 |
|
|
find_step_target (struct frame_info *frame, inst_env_type *inst_env)
|
2061 |
|
|
{
|
2062 |
|
|
int i;
|
2063 |
|
|
int offset;
|
2064 |
|
|
unsigned short insn;
|
2065 |
|
|
struct gdbarch *gdbarch = get_frame_arch (frame);
|
2066 |
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
2067 |
|
|
|
2068 |
|
|
/* Create a local register image and set the initial state. */
|
2069 |
|
|
for (i = 0; i < NUM_GENREGS; i++)
|
2070 |
|
|
{
|
2071 |
|
|
inst_env->reg[i] =
|
2072 |
|
|
(unsigned long) get_frame_register_unsigned (frame, i);
|
2073 |
|
|
}
|
2074 |
|
|
offset = NUM_GENREGS;
|
2075 |
|
|
for (i = 0; i < NUM_SPECREGS; i++)
|
2076 |
|
|
{
|
2077 |
|
|
inst_env->preg[i] =
|
2078 |
|
|
(unsigned long) get_frame_register_unsigned (frame, offset + i);
|
2079 |
|
|
}
|
2080 |
|
|
inst_env->branch_found = 0;
|
2081 |
|
|
inst_env->slot_needed = 0;
|
2082 |
|
|
inst_env->delay_slot_pc_active = 0;
|
2083 |
|
|
inst_env->prefix_found = 0;
|
2084 |
|
|
inst_env->invalid = 0;
|
2085 |
|
|
inst_env->xflag_found = 0;
|
2086 |
|
|
inst_env->disable_interrupt = 0;
|
2087 |
|
|
inst_env->byte_order = byte_order;
|
2088 |
|
|
|
2089 |
|
|
/* Look for a step target. */
|
2090 |
|
|
do
|
2091 |
|
|
{
|
2092 |
|
|
/* Read an instruction from the client. */
|
2093 |
|
|
insn = read_memory_unsigned_integer
|
2094 |
|
|
(inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
|
2095 |
|
|
|
2096 |
|
|
/* If the instruction is not in a delay slot the new content of the
|
2097 |
|
|
PC is [PC] + 2. If the instruction is in a delay slot it is not
|
2098 |
|
|
that simple. Since a instruction in a delay slot cannot change
|
2099 |
|
|
the content of the PC, it does not matter what value PC will have.
|
2100 |
|
|
Just make sure it is a valid instruction. */
|
2101 |
|
|
if (!inst_env->delay_slot_pc_active)
|
2102 |
|
|
{
|
2103 |
|
|
inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
|
2104 |
|
|
}
|
2105 |
|
|
else
|
2106 |
|
|
{
|
2107 |
|
|
inst_env->delay_slot_pc_active = 0;
|
2108 |
|
|
inst_env->reg[gdbarch_pc_regnum (gdbarch)]
|
2109 |
|
|
= inst_env->delay_slot_pc;
|
2110 |
|
|
}
|
2111 |
|
|
/* Analyse the present instruction. */
|
2112 |
|
|
i = find_cris_op (insn, inst_env);
|
2113 |
|
|
if (i == -1)
|
2114 |
|
|
{
|
2115 |
|
|
inst_env->invalid = 1;
|
2116 |
|
|
}
|
2117 |
|
|
else
|
2118 |
|
|
{
|
2119 |
|
|
cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
|
2120 |
|
|
}
|
2121 |
|
|
} while (!inst_env->invalid
|
2122 |
|
|
&& (inst_env->prefix_found || inst_env->xflag_found
|
2123 |
|
|
|| inst_env->slot_needed));
|
2124 |
|
|
return i;
|
2125 |
|
|
}
|
2126 |
|
|
|
2127 |
|
|
/* There is no hardware single-step support. The function find_step_target
|
2128 |
|
|
digs through the opcodes in order to find all possible targets.
|
2129 |
|
|
Either one ordinary target or two targets for branches may be found. */
|
2130 |
|
|
|
2131 |
|
|
static int
|
2132 |
|
|
cris_software_single_step (struct frame_info *frame)
|
2133 |
|
|
{
|
2134 |
|
|
struct gdbarch *gdbarch = get_frame_arch (frame);
|
2135 |
|
|
struct address_space *aspace = get_frame_address_space (frame);
|
2136 |
|
|
inst_env_type inst_env;
|
2137 |
|
|
|
2138 |
|
|
/* Analyse the present instruction environment and insert
|
2139 |
|
|
breakpoints. */
|
2140 |
|
|
int status = find_step_target (frame, &inst_env);
|
2141 |
|
|
if (status == -1)
|
2142 |
|
|
{
|
2143 |
|
|
/* Could not find a target. Things are likely to go downhill
|
2144 |
|
|
from here. */
|
2145 |
|
|
warning (_("CRIS software single step could not find a step target."));
|
2146 |
|
|
}
|
2147 |
|
|
else
|
2148 |
|
|
{
|
2149 |
|
|
/* Insert at most two breakpoints. One for the next PC content
|
2150 |
|
|
and possibly another one for a branch, jump, etc. */
|
2151 |
|
|
CORE_ADDR next_pc
|
2152 |
|
|
= (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
|
2153 |
|
|
insert_single_step_breakpoint (gdbarch, aspace, next_pc);
|
2154 |
|
|
if (inst_env.branch_found
|
2155 |
|
|
&& (CORE_ADDR) inst_env.branch_break_address != next_pc)
|
2156 |
|
|
{
|
2157 |
|
|
CORE_ADDR branch_target_address
|
2158 |
|
|
= (CORE_ADDR) inst_env.branch_break_address;
|
2159 |
|
|
insert_single_step_breakpoint (gdbarch,
|
2160 |
|
|
aspace, branch_target_address);
|
2161 |
|
|
}
|
2162 |
|
|
}
|
2163 |
|
|
|
2164 |
|
|
return 1;
|
2165 |
|
|
}
|
2166 |
|
|
|
2167 |
|
|
/* Calculates the prefix value for quick offset addressing mode. */
|
2168 |
|
|
|
2169 |
|
|
static void
|
2170 |
|
|
quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
|
2171 |
|
|
{
|
2172 |
|
|
/* It's invalid to be in a delay slot. You can't have a prefix to this
|
2173 |
|
|
instruction (not 100% sure). */
|
2174 |
|
|
if (inst_env->slot_needed || inst_env->prefix_found)
|
2175 |
|
|
{
|
2176 |
|
|
inst_env->invalid = 1;
|
2177 |
|
|
return;
|
2178 |
|
|
}
|
2179 |
|
|
|
2180 |
|
|
inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
|
2181 |
|
|
inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
|
2182 |
|
|
|
2183 |
|
|
/* A prefix doesn't change the xflag_found. But the rest of the flags
|
2184 |
|
|
need updating. */
|
2185 |
|
|
inst_env->slot_needed = 0;
|
2186 |
|
|
inst_env->prefix_found = 1;
|
2187 |
|
|
}
|
2188 |
|
|
|
2189 |
|
|
/* Updates the autoincrement register. The size of the increment is derived
|
2190 |
|
|
from the size of the operation. The PC is always kept aligned on even
|
2191 |
|
|
word addresses. */
|
2192 |
|
|
|
2193 |
|
|
static void
|
2194 |
|
|
process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
|
2195 |
|
|
{
|
2196 |
|
|
if (size == INST_BYTE_SIZE)
|
2197 |
|
|
{
|
2198 |
|
|
inst_env->reg[cris_get_operand1 (inst)] += 1;
|
2199 |
|
|
|
2200 |
|
|
/* The PC must be word aligned, so increase the PC with one
|
2201 |
|
|
word even if the size is byte. */
|
2202 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
2203 |
|
|
{
|
2204 |
|
|
inst_env->reg[REG_PC] += 1;
|
2205 |
|
|
}
|
2206 |
|
|
}
|
2207 |
|
|
else if (size == INST_WORD_SIZE)
|
2208 |
|
|
{
|
2209 |
|
|
inst_env->reg[cris_get_operand1 (inst)] += 2;
|
2210 |
|
|
}
|
2211 |
|
|
else if (size == INST_DWORD_SIZE)
|
2212 |
|
|
{
|
2213 |
|
|
inst_env->reg[cris_get_operand1 (inst)] += 4;
|
2214 |
|
|
}
|
2215 |
|
|
else
|
2216 |
|
|
{
|
2217 |
|
|
/* Invalid size. */
|
2218 |
|
|
inst_env->invalid = 1;
|
2219 |
|
|
}
|
2220 |
|
|
}
|
2221 |
|
|
|
2222 |
|
|
/* Just a forward declaration. */
|
2223 |
|
|
|
2224 |
|
|
static unsigned long get_data_from_address (unsigned short *inst,
|
2225 |
|
|
CORE_ADDR address,
|
2226 |
|
|
enum bfd_endian byte_order);
|
2227 |
|
|
|
2228 |
|
|
/* Calculates the prefix value for the general case of offset addressing
|
2229 |
|
|
mode. */
|
2230 |
|
|
|
2231 |
|
|
static void
|
2232 |
|
|
bdap_prefix (unsigned short inst, inst_env_type *inst_env)
|
2233 |
|
|
{
|
2234 |
|
|
|
2235 |
|
|
long offset;
|
2236 |
|
|
|
2237 |
|
|
/* It's invalid to be in a delay slot. */
|
2238 |
|
|
if (inst_env->slot_needed || inst_env->prefix_found)
|
2239 |
|
|
{
|
2240 |
|
|
inst_env->invalid = 1;
|
2241 |
|
|
return;
|
2242 |
|
|
}
|
2243 |
|
|
|
2244 |
|
|
/* The calculation of prefix_value used to be after process_autoincrement,
|
2245 |
|
|
but that fails for an instruction such as jsr [$r0+12] which is encoded
|
2246 |
|
|
as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
|
2247 |
|
|
mustn't be incremented until we have read it and what it points at. */
|
2248 |
|
|
inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
|
2249 |
|
|
|
2250 |
|
|
/* The offset is an indirection of the contents of the operand1 register. */
|
2251 |
|
|
inst_env->prefix_value +=
|
2252 |
|
|
get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
|
2253 |
|
|
inst_env->byte_order);
|
2254 |
|
|
|
2255 |
|
|
if (cris_get_mode (inst) == AUTOINC_MODE)
|
2256 |
|
|
{
|
2257 |
|
|
process_autoincrement (cris_get_size (inst), inst, inst_env);
|
2258 |
|
|
}
|
2259 |
|
|
|
2260 |
|
|
/* A prefix doesn't change the xflag_found. But the rest of the flags
|
2261 |
|
|
need updating. */
|
2262 |
|
|
inst_env->slot_needed = 0;
|
2263 |
|
|
inst_env->prefix_found = 1;
|
2264 |
|
|
}
|
2265 |
|
|
|
2266 |
|
|
/* Calculates the prefix value for the index addressing mode. */
|
2267 |
|
|
|
2268 |
|
|
static void
|
2269 |
|
|
biap_prefix (unsigned short inst, inst_env_type *inst_env)
|
2270 |
|
|
{
|
2271 |
|
|
/* It's invalid to be in a delay slot. I can't see that it's possible to
|
2272 |
|
|
have a prefix to this instruction. So I will treat this as invalid. */
|
2273 |
|
|
if (inst_env->slot_needed || inst_env->prefix_found)
|
2274 |
|
|
{
|
2275 |
|
|
inst_env->invalid = 1;
|
2276 |
|
|
return;
|
2277 |
|
|
}
|
2278 |
|
|
|
2279 |
|
|
inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
|
2280 |
|
|
|
2281 |
|
|
/* The offset is the operand2 value shifted the size of the instruction
|
2282 |
|
|
to the left. */
|
2283 |
|
|
inst_env->prefix_value +=
|
2284 |
|
|
inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
|
2285 |
|
|
|
2286 |
|
|
/* If the PC is operand1 (base) the address used is the address after
|
2287 |
|
|
the main instruction, i.e. address + 2 (the PC is already compensated
|
2288 |
|
|
for the prefix operation). */
|
2289 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
2290 |
|
|
{
|
2291 |
|
|
inst_env->prefix_value += 2;
|
2292 |
|
|
}
|
2293 |
|
|
|
2294 |
|
|
/* A prefix doesn't change the xflag_found. But the rest of the flags
|
2295 |
|
|
need updating. */
|
2296 |
|
|
inst_env->slot_needed = 0;
|
2297 |
|
|
inst_env->xflag_found = 0;
|
2298 |
|
|
inst_env->prefix_found = 1;
|
2299 |
|
|
}
|
2300 |
|
|
|
2301 |
|
|
/* Calculates the prefix value for the double indirect addressing mode. */
|
2302 |
|
|
|
2303 |
|
|
static void
|
2304 |
|
|
dip_prefix (unsigned short inst, inst_env_type *inst_env)
|
2305 |
|
|
{
|
2306 |
|
|
|
2307 |
|
|
CORE_ADDR address;
|
2308 |
|
|
|
2309 |
|
|
/* It's invalid to be in a delay slot. */
|
2310 |
|
|
if (inst_env->slot_needed || inst_env->prefix_found)
|
2311 |
|
|
{
|
2312 |
|
|
inst_env->invalid = 1;
|
2313 |
|
|
return;
|
2314 |
|
|
}
|
2315 |
|
|
|
2316 |
|
|
/* The prefix value is one dereference of the contents of the operand1
|
2317 |
|
|
register. */
|
2318 |
|
|
address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
|
2319 |
|
|
inst_env->prefix_value
|
2320 |
|
|
= read_memory_unsigned_integer (address, 4, inst_env->byte_order);
|
2321 |
|
|
|
2322 |
|
|
/* Check if the mode is autoincrement. */
|
2323 |
|
|
if (cris_get_mode (inst) == AUTOINC_MODE)
|
2324 |
|
|
{
|
2325 |
|
|
inst_env->reg[cris_get_operand1 (inst)] += 4;
|
2326 |
|
|
}
|
2327 |
|
|
|
2328 |
|
|
/* A prefix doesn't change the xflag_found. But the rest of the flags
|
2329 |
|
|
need updating. */
|
2330 |
|
|
inst_env->slot_needed = 0;
|
2331 |
|
|
inst_env->xflag_found = 0;
|
2332 |
|
|
inst_env->prefix_found = 1;
|
2333 |
|
|
}
|
2334 |
|
|
|
2335 |
|
|
/* Finds the destination for a branch with 8-bits offset. */
|
2336 |
|
|
|
2337 |
|
|
static void
|
2338 |
|
|
eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
|
2339 |
|
|
{
|
2340 |
|
|
|
2341 |
|
|
short offset;
|
2342 |
|
|
|
2343 |
|
|
/* If we have a prefix or are in a delay slot it's bad. */
|
2344 |
|
|
if (inst_env->slot_needed || inst_env->prefix_found)
|
2345 |
|
|
{
|
2346 |
|
|
inst_env->invalid = 1;
|
2347 |
|
|
return;
|
2348 |
|
|
}
|
2349 |
|
|
|
2350 |
|
|
/* We have a branch, find out where the branch will land. */
|
2351 |
|
|
offset = cris_get_branch_short_offset (inst);
|
2352 |
|
|
|
2353 |
|
|
/* Check if the offset is signed. */
|
2354 |
|
|
if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
|
2355 |
|
|
{
|
2356 |
|
|
offset |= 0xFF00;
|
2357 |
|
|
}
|
2358 |
|
|
|
2359 |
|
|
/* The offset ends with the sign bit, set it to zero. The address
|
2360 |
|
|
should always be word aligned. */
|
2361 |
|
|
offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
|
2362 |
|
|
|
2363 |
|
|
inst_env->branch_found = 1;
|
2364 |
|
|
inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
|
2365 |
|
|
|
2366 |
|
|
inst_env->slot_needed = 1;
|
2367 |
|
|
inst_env->prefix_found = 0;
|
2368 |
|
|
inst_env->xflag_found = 0;
|
2369 |
|
|
inst_env->disable_interrupt = 1;
|
2370 |
|
|
}
|
2371 |
|
|
|
2372 |
|
|
/* Finds the destination for a branch with 16-bits offset. */
|
2373 |
|
|
|
2374 |
|
|
static void
|
2375 |
|
|
sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
|
2376 |
|
|
{
|
2377 |
|
|
short offset;
|
2378 |
|
|
|
2379 |
|
|
/* If we have a prefix or is in a delay slot it's bad. */
|
2380 |
|
|
if (inst_env->slot_needed || inst_env->prefix_found)
|
2381 |
|
|
{
|
2382 |
|
|
inst_env->invalid = 1;
|
2383 |
|
|
return;
|
2384 |
|
|
}
|
2385 |
|
|
|
2386 |
|
|
/* We have a branch, find out the offset for the branch. */
|
2387 |
|
|
offset = read_memory_integer (inst_env->reg[REG_PC], 2, inst_env->byte_order);
|
2388 |
|
|
|
2389 |
|
|
/* The instruction is one word longer than normal, so add one word
|
2390 |
|
|
to the PC. */
|
2391 |
|
|
inst_env->reg[REG_PC] += 2;
|
2392 |
|
|
|
2393 |
|
|
inst_env->branch_found = 1;
|
2394 |
|
|
inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
|
2395 |
|
|
|
2396 |
|
|
|
2397 |
|
|
inst_env->slot_needed = 1;
|
2398 |
|
|
inst_env->prefix_found = 0;
|
2399 |
|
|
inst_env->xflag_found = 0;
|
2400 |
|
|
inst_env->disable_interrupt = 1;
|
2401 |
|
|
}
|
2402 |
|
|
|
2403 |
|
|
/* Handles the ABS instruction. */
|
2404 |
|
|
|
2405 |
|
|
static void
|
2406 |
|
|
abs_op (unsigned short inst, inst_env_type *inst_env)
|
2407 |
|
|
{
|
2408 |
|
|
|
2409 |
|
|
long value;
|
2410 |
|
|
|
2411 |
|
|
/* ABS can't have a prefix, so it's bad if it does. */
|
2412 |
|
|
if (inst_env->prefix_found)
|
2413 |
|
|
{
|
2414 |
|
|
inst_env->invalid = 1;
|
2415 |
|
|
return;
|
2416 |
|
|
}
|
2417 |
|
|
|
2418 |
|
|
/* Check if the operation affects the PC. */
|
2419 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
2420 |
|
|
{
|
2421 |
|
|
|
2422 |
|
|
/* It's invalid to change to the PC if we are in a delay slot. */
|
2423 |
|
|
if (inst_env->slot_needed)
|
2424 |
|
|
{
|
2425 |
|
|
inst_env->invalid = 1;
|
2426 |
|
|
return;
|
2427 |
|
|
}
|
2428 |
|
|
|
2429 |
|
|
value = (long) inst_env->reg[REG_PC];
|
2430 |
|
|
|
2431 |
|
|
/* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
|
2432 |
|
|
if (value != SIGNED_DWORD_MASK)
|
2433 |
|
|
{
|
2434 |
|
|
value = -value;
|
2435 |
|
|
inst_env->reg[REG_PC] = (long) value;
|
2436 |
|
|
}
|
2437 |
|
|
}
|
2438 |
|
|
|
2439 |
|
|
inst_env->slot_needed = 0;
|
2440 |
|
|
inst_env->prefix_found = 0;
|
2441 |
|
|
inst_env->xflag_found = 0;
|
2442 |
|
|
inst_env->disable_interrupt = 0;
|
2443 |
|
|
}
|
2444 |
|
|
|
2445 |
|
|
/* Handles the ADDI instruction. */
|
2446 |
|
|
|
2447 |
|
|
static void
|
2448 |
|
|
addi_op (unsigned short inst, inst_env_type *inst_env)
|
2449 |
|
|
{
|
2450 |
|
|
/* It's invalid to have the PC as base register. And ADDI can't have
|
2451 |
|
|
a prefix. */
|
2452 |
|
|
if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
|
2453 |
|
|
{
|
2454 |
|
|
inst_env->invalid = 1;
|
2455 |
|
|
return;
|
2456 |
|
|
}
|
2457 |
|
|
|
2458 |
|
|
inst_env->slot_needed = 0;
|
2459 |
|
|
inst_env->prefix_found = 0;
|
2460 |
|
|
inst_env->xflag_found = 0;
|
2461 |
|
|
inst_env->disable_interrupt = 0;
|
2462 |
|
|
}
|
2463 |
|
|
|
2464 |
|
|
/* Handles the ASR instruction. */
|
2465 |
|
|
|
2466 |
|
|
static void
|
2467 |
|
|
asr_op (unsigned short inst, inst_env_type *inst_env)
|
2468 |
|
|
{
|
2469 |
|
|
int shift_steps;
|
2470 |
|
|
unsigned long value;
|
2471 |
|
|
unsigned long signed_extend_mask = 0;
|
2472 |
|
|
|
2473 |
|
|
/* ASR can't have a prefix, so check that it doesn't. */
|
2474 |
|
|
if (inst_env->prefix_found)
|
2475 |
|
|
{
|
2476 |
|
|
inst_env->invalid = 1;
|
2477 |
|
|
return;
|
2478 |
|
|
}
|
2479 |
|
|
|
2480 |
|
|
/* Check if the PC is the target register. */
|
2481 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
2482 |
|
|
{
|
2483 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
2484 |
|
|
if (inst_env->slot_needed)
|
2485 |
|
|
{
|
2486 |
|
|
inst_env->invalid = 1;
|
2487 |
|
|
return;
|
2488 |
|
|
}
|
2489 |
|
|
/* Get the number of bits to shift. */
|
2490 |
|
|
shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
|
2491 |
|
|
value = inst_env->reg[REG_PC];
|
2492 |
|
|
|
2493 |
|
|
/* Find out how many bits the operation should apply to. */
|
2494 |
|
|
if (cris_get_size (inst) == INST_BYTE_SIZE)
|
2495 |
|
|
{
|
2496 |
|
|
if (value & SIGNED_BYTE_MASK)
|
2497 |
|
|
{
|
2498 |
|
|
signed_extend_mask = 0xFF;
|
2499 |
|
|
signed_extend_mask = signed_extend_mask >> shift_steps;
|
2500 |
|
|
signed_extend_mask = ~signed_extend_mask;
|
2501 |
|
|
}
|
2502 |
|
|
value = value >> shift_steps;
|
2503 |
|
|
value |= signed_extend_mask;
|
2504 |
|
|
value &= 0xFF;
|
2505 |
|
|
inst_env->reg[REG_PC] &= 0xFFFFFF00;
|
2506 |
|
|
inst_env->reg[REG_PC] |= value;
|
2507 |
|
|
}
|
2508 |
|
|
else if (cris_get_size (inst) == INST_WORD_SIZE)
|
2509 |
|
|
{
|
2510 |
|
|
if (value & SIGNED_WORD_MASK)
|
2511 |
|
|
{
|
2512 |
|
|
signed_extend_mask = 0xFFFF;
|
2513 |
|
|
signed_extend_mask = signed_extend_mask >> shift_steps;
|
2514 |
|
|
signed_extend_mask = ~signed_extend_mask;
|
2515 |
|
|
}
|
2516 |
|
|
value = value >> shift_steps;
|
2517 |
|
|
value |= signed_extend_mask;
|
2518 |
|
|
value &= 0xFFFF;
|
2519 |
|
|
inst_env->reg[REG_PC] &= 0xFFFF0000;
|
2520 |
|
|
inst_env->reg[REG_PC] |= value;
|
2521 |
|
|
}
|
2522 |
|
|
else if (cris_get_size (inst) == INST_DWORD_SIZE)
|
2523 |
|
|
{
|
2524 |
|
|
if (value & SIGNED_DWORD_MASK)
|
2525 |
|
|
{
|
2526 |
|
|
signed_extend_mask = 0xFFFFFFFF;
|
2527 |
|
|
signed_extend_mask = signed_extend_mask >> shift_steps;
|
2528 |
|
|
signed_extend_mask = ~signed_extend_mask;
|
2529 |
|
|
}
|
2530 |
|
|
value = value >> shift_steps;
|
2531 |
|
|
value |= signed_extend_mask;
|
2532 |
|
|
inst_env->reg[REG_PC] = value;
|
2533 |
|
|
}
|
2534 |
|
|
}
|
2535 |
|
|
inst_env->slot_needed = 0;
|
2536 |
|
|
inst_env->prefix_found = 0;
|
2537 |
|
|
inst_env->xflag_found = 0;
|
2538 |
|
|
inst_env->disable_interrupt = 0;
|
2539 |
|
|
}
|
2540 |
|
|
|
2541 |
|
|
/* Handles the ASRQ instruction. */
|
2542 |
|
|
|
2543 |
|
|
static void
|
2544 |
|
|
asrq_op (unsigned short inst, inst_env_type *inst_env)
|
2545 |
|
|
{
|
2546 |
|
|
|
2547 |
|
|
int shift_steps;
|
2548 |
|
|
unsigned long value;
|
2549 |
|
|
unsigned long signed_extend_mask = 0;
|
2550 |
|
|
|
2551 |
|
|
/* ASRQ can't have a prefix, so check that it doesn't. */
|
2552 |
|
|
if (inst_env->prefix_found)
|
2553 |
|
|
{
|
2554 |
|
|
inst_env->invalid = 1;
|
2555 |
|
|
return;
|
2556 |
|
|
}
|
2557 |
|
|
|
2558 |
|
|
/* Check if the PC is the target register. */
|
2559 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
2560 |
|
|
{
|
2561 |
|
|
|
2562 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
2563 |
|
|
if (inst_env->slot_needed)
|
2564 |
|
|
{
|
2565 |
|
|
inst_env->invalid = 1;
|
2566 |
|
|
return;
|
2567 |
|
|
}
|
2568 |
|
|
/* The shift size is given as a 5 bit quick value, i.e. we don't
|
2569 |
|
|
want the the sign bit of the quick value. */
|
2570 |
|
|
shift_steps = cris_get_asr_shift_steps (inst);
|
2571 |
|
|
value = inst_env->reg[REG_PC];
|
2572 |
|
|
if (value & SIGNED_DWORD_MASK)
|
2573 |
|
|
{
|
2574 |
|
|
signed_extend_mask = 0xFFFFFFFF;
|
2575 |
|
|
signed_extend_mask = signed_extend_mask >> shift_steps;
|
2576 |
|
|
signed_extend_mask = ~signed_extend_mask;
|
2577 |
|
|
}
|
2578 |
|
|
value = value >> shift_steps;
|
2579 |
|
|
value |= signed_extend_mask;
|
2580 |
|
|
inst_env->reg[REG_PC] = value;
|
2581 |
|
|
}
|
2582 |
|
|
inst_env->slot_needed = 0;
|
2583 |
|
|
inst_env->prefix_found = 0;
|
2584 |
|
|
inst_env->xflag_found = 0;
|
2585 |
|
|
inst_env->disable_interrupt = 0;
|
2586 |
|
|
}
|
2587 |
|
|
|
2588 |
|
|
/* Handles the AX, EI and SETF instruction. */
|
2589 |
|
|
|
2590 |
|
|
static void
|
2591 |
|
|
ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
|
2592 |
|
|
{
|
2593 |
|
|
if (inst_env->prefix_found)
|
2594 |
|
|
{
|
2595 |
|
|
inst_env->invalid = 1;
|
2596 |
|
|
return;
|
2597 |
|
|
}
|
2598 |
|
|
/* Check if the instruction is setting the X flag. */
|
2599 |
|
|
if (cris_is_xflag_bit_on (inst))
|
2600 |
|
|
{
|
2601 |
|
|
inst_env->xflag_found = 1;
|
2602 |
|
|
}
|
2603 |
|
|
else
|
2604 |
|
|
{
|
2605 |
|
|
inst_env->xflag_found = 0;
|
2606 |
|
|
}
|
2607 |
|
|
inst_env->slot_needed = 0;
|
2608 |
|
|
inst_env->prefix_found = 0;
|
2609 |
|
|
inst_env->disable_interrupt = 1;
|
2610 |
|
|
}
|
2611 |
|
|
|
2612 |
|
|
/* Checks if the instruction is in assign mode. If so, it updates the assign
|
2613 |
|
|
register. Note that check_assign assumes that the caller has checked that
|
2614 |
|
|
there is a prefix to this instruction. The mode check depends on this. */
|
2615 |
|
|
|
2616 |
|
|
static void
|
2617 |
|
|
check_assign (unsigned short inst, inst_env_type *inst_env)
|
2618 |
|
|
{
|
2619 |
|
|
/* Check if it's an assign addressing mode. */
|
2620 |
|
|
if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
|
2621 |
|
|
{
|
2622 |
|
|
/* Assign the prefix value to operand 1. */
|
2623 |
|
|
inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
|
2624 |
|
|
}
|
2625 |
|
|
}
|
2626 |
|
|
|
2627 |
|
|
/* Handles the 2-operand BOUND instruction. */
|
2628 |
|
|
|
2629 |
|
|
static void
|
2630 |
|
|
two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
|
2631 |
|
|
{
|
2632 |
|
|
/* It's invalid to have the PC as the index operand. */
|
2633 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
2634 |
|
|
{
|
2635 |
|
|
inst_env->invalid = 1;
|
2636 |
|
|
return;
|
2637 |
|
|
}
|
2638 |
|
|
/* Check if we have a prefix. */
|
2639 |
|
|
if (inst_env->prefix_found)
|
2640 |
|
|
{
|
2641 |
|
|
check_assign (inst, inst_env);
|
2642 |
|
|
}
|
2643 |
|
|
/* Check if this is an autoincrement mode. */
|
2644 |
|
|
else if (cris_get_mode (inst) == AUTOINC_MODE)
|
2645 |
|
|
{
|
2646 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
2647 |
|
|
if (inst_env->slot_needed)
|
2648 |
|
|
{
|
2649 |
|
|
inst_env->invalid = 1;
|
2650 |
|
|
return;
|
2651 |
|
|
}
|
2652 |
|
|
process_autoincrement (cris_get_size (inst), inst, inst_env);
|
2653 |
|
|
}
|
2654 |
|
|
inst_env->slot_needed = 0;
|
2655 |
|
|
inst_env->prefix_found = 0;
|
2656 |
|
|
inst_env->xflag_found = 0;
|
2657 |
|
|
inst_env->disable_interrupt = 0;
|
2658 |
|
|
}
|
2659 |
|
|
|
2660 |
|
|
/* Handles the 3-operand BOUND instruction. */
|
2661 |
|
|
|
2662 |
|
|
static void
|
2663 |
|
|
three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
|
2664 |
|
|
{
|
2665 |
|
|
/* It's an error if we haven't got a prefix. And it's also an error
|
2666 |
|
|
if the PC is the destination register. */
|
2667 |
|
|
if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
|
2668 |
|
|
{
|
2669 |
|
|
inst_env->invalid = 1;
|
2670 |
|
|
return;
|
2671 |
|
|
}
|
2672 |
|
|
inst_env->slot_needed = 0;
|
2673 |
|
|
inst_env->prefix_found = 0;
|
2674 |
|
|
inst_env->xflag_found = 0;
|
2675 |
|
|
inst_env->disable_interrupt = 0;
|
2676 |
|
|
}
|
2677 |
|
|
|
2678 |
|
|
/* Clears the status flags in inst_env. */
|
2679 |
|
|
|
2680 |
|
|
static void
|
2681 |
|
|
btst_nop_op (unsigned short inst, inst_env_type *inst_env)
|
2682 |
|
|
{
|
2683 |
|
|
/* It's an error if we have got a prefix. */
|
2684 |
|
|
if (inst_env->prefix_found)
|
2685 |
|
|
{
|
2686 |
|
|
inst_env->invalid = 1;
|
2687 |
|
|
return;
|
2688 |
|
|
}
|
2689 |
|
|
|
2690 |
|
|
inst_env->slot_needed = 0;
|
2691 |
|
|
inst_env->prefix_found = 0;
|
2692 |
|
|
inst_env->xflag_found = 0;
|
2693 |
|
|
inst_env->disable_interrupt = 0;
|
2694 |
|
|
}
|
2695 |
|
|
|
2696 |
|
|
/* Clears the status flags in inst_env. */
|
2697 |
|
|
|
2698 |
|
|
static void
|
2699 |
|
|
clearf_di_op (unsigned short inst, inst_env_type *inst_env)
|
2700 |
|
|
{
|
2701 |
|
|
/* It's an error if we have got a prefix. */
|
2702 |
|
|
if (inst_env->prefix_found)
|
2703 |
|
|
{
|
2704 |
|
|
inst_env->invalid = 1;
|
2705 |
|
|
return;
|
2706 |
|
|
}
|
2707 |
|
|
|
2708 |
|
|
inst_env->slot_needed = 0;
|
2709 |
|
|
inst_env->prefix_found = 0;
|
2710 |
|
|
inst_env->xflag_found = 0;
|
2711 |
|
|
inst_env->disable_interrupt = 1;
|
2712 |
|
|
}
|
2713 |
|
|
|
2714 |
|
|
/* Handles the CLEAR instruction if it's in register mode. */
|
2715 |
|
|
|
2716 |
|
|
static void
|
2717 |
|
|
reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
|
2718 |
|
|
{
|
2719 |
|
|
/* Check if the target is the PC. */
|
2720 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
2721 |
|
|
{
|
2722 |
|
|
/* The instruction will clear the instruction's size bits. */
|
2723 |
|
|
int clear_size = cris_get_clear_size (inst);
|
2724 |
|
|
if (clear_size == INST_BYTE_SIZE)
|
2725 |
|
|
{
|
2726 |
|
|
inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
|
2727 |
|
|
}
|
2728 |
|
|
if (clear_size == INST_WORD_SIZE)
|
2729 |
|
|
{
|
2730 |
|
|
inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
|
2731 |
|
|
}
|
2732 |
|
|
if (clear_size == INST_DWORD_SIZE)
|
2733 |
|
|
{
|
2734 |
|
|
inst_env->delay_slot_pc = 0x0;
|
2735 |
|
|
}
|
2736 |
|
|
/* The jump will be delayed with one delay slot. So we need a delay
|
2737 |
|
|
slot. */
|
2738 |
|
|
inst_env->slot_needed = 1;
|
2739 |
|
|
inst_env->delay_slot_pc_active = 1;
|
2740 |
|
|
}
|
2741 |
|
|
else
|
2742 |
|
|
{
|
2743 |
|
|
/* The PC will not change => no delay slot. */
|
2744 |
|
|
inst_env->slot_needed = 0;
|
2745 |
|
|
}
|
2746 |
|
|
inst_env->prefix_found = 0;
|
2747 |
|
|
inst_env->xflag_found = 0;
|
2748 |
|
|
inst_env->disable_interrupt = 0;
|
2749 |
|
|
}
|
2750 |
|
|
|
2751 |
|
|
/* Handles the TEST instruction if it's in register mode. */
|
2752 |
|
|
|
2753 |
|
|
static void
|
2754 |
|
|
reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
|
2755 |
|
|
{
|
2756 |
|
|
/* It's an error if we have got a prefix. */
|
2757 |
|
|
if (inst_env->prefix_found)
|
2758 |
|
|
{
|
2759 |
|
|
inst_env->invalid = 1;
|
2760 |
|
|
return;
|
2761 |
|
|
}
|
2762 |
|
|
inst_env->slot_needed = 0;
|
2763 |
|
|
inst_env->prefix_found = 0;
|
2764 |
|
|
inst_env->xflag_found = 0;
|
2765 |
|
|
inst_env->disable_interrupt = 0;
|
2766 |
|
|
|
2767 |
|
|
}
|
2768 |
|
|
|
2769 |
|
|
/* Handles the CLEAR and TEST instruction if the instruction isn't
|
2770 |
|
|
in register mode. */
|
2771 |
|
|
|
2772 |
|
|
static void
|
2773 |
|
|
none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
|
2774 |
|
|
{
|
2775 |
|
|
/* Check if we are in a prefix mode. */
|
2776 |
|
|
if (inst_env->prefix_found)
|
2777 |
|
|
{
|
2778 |
|
|
/* The only way the PC can change is if this instruction is in
|
2779 |
|
|
assign addressing mode. */
|
2780 |
|
|
check_assign (inst, inst_env);
|
2781 |
|
|
}
|
2782 |
|
|
/* Indirect mode can't change the PC so just check if the mode is
|
2783 |
|
|
autoincrement. */
|
2784 |
|
|
else if (cris_get_mode (inst) == AUTOINC_MODE)
|
2785 |
|
|
{
|
2786 |
|
|
process_autoincrement (cris_get_size (inst), inst, inst_env);
|
2787 |
|
|
}
|
2788 |
|
|
inst_env->slot_needed = 0;
|
2789 |
|
|
inst_env->prefix_found = 0;
|
2790 |
|
|
inst_env->xflag_found = 0;
|
2791 |
|
|
inst_env->disable_interrupt = 0;
|
2792 |
|
|
}
|
2793 |
|
|
|
2794 |
|
|
/* Checks that the PC isn't the destination register or the instructions has
|
2795 |
|
|
a prefix. */
|
2796 |
|
|
|
2797 |
|
|
static void
|
2798 |
|
|
dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
|
2799 |
|
|
{
|
2800 |
|
|
/* It's invalid to have the PC as the destination. The instruction can't
|
2801 |
|
|
have a prefix. */
|
2802 |
|
|
if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
|
2803 |
|
|
{
|
2804 |
|
|
inst_env->invalid = 1;
|
2805 |
|
|
return;
|
2806 |
|
|
}
|
2807 |
|
|
|
2808 |
|
|
inst_env->slot_needed = 0;
|
2809 |
|
|
inst_env->prefix_found = 0;
|
2810 |
|
|
inst_env->xflag_found = 0;
|
2811 |
|
|
inst_env->disable_interrupt = 0;
|
2812 |
|
|
}
|
2813 |
|
|
|
2814 |
|
|
/* Checks that the instruction doesn't have a prefix. */
|
2815 |
|
|
|
2816 |
|
|
static void
|
2817 |
|
|
break_op (unsigned short inst, inst_env_type *inst_env)
|
2818 |
|
|
{
|
2819 |
|
|
/* The instruction can't have a prefix. */
|
2820 |
|
|
if (inst_env->prefix_found)
|
2821 |
|
|
{
|
2822 |
|
|
inst_env->invalid = 1;
|
2823 |
|
|
return;
|
2824 |
|
|
}
|
2825 |
|
|
|
2826 |
|
|
inst_env->slot_needed = 0;
|
2827 |
|
|
inst_env->prefix_found = 0;
|
2828 |
|
|
inst_env->xflag_found = 0;
|
2829 |
|
|
inst_env->disable_interrupt = 1;
|
2830 |
|
|
}
|
2831 |
|
|
|
2832 |
|
|
/* Checks that the PC isn't the destination register and that the instruction
|
2833 |
|
|
doesn't have a prefix. */
|
2834 |
|
|
|
2835 |
|
|
static void
|
2836 |
|
|
scc_op (unsigned short inst, inst_env_type *inst_env)
|
2837 |
|
|
{
|
2838 |
|
|
/* It's invalid to have the PC as the destination. The instruction can't
|
2839 |
|
|
have a prefix. */
|
2840 |
|
|
if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
|
2841 |
|
|
{
|
2842 |
|
|
inst_env->invalid = 1;
|
2843 |
|
|
return;
|
2844 |
|
|
}
|
2845 |
|
|
|
2846 |
|
|
inst_env->slot_needed = 0;
|
2847 |
|
|
inst_env->prefix_found = 0;
|
2848 |
|
|
inst_env->xflag_found = 0;
|
2849 |
|
|
inst_env->disable_interrupt = 1;
|
2850 |
|
|
}
|
2851 |
|
|
|
2852 |
|
|
/* Handles the register mode JUMP instruction. */
|
2853 |
|
|
|
2854 |
|
|
static void
|
2855 |
|
|
reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
|
2856 |
|
|
{
|
2857 |
|
|
/* It's invalid to do a JUMP in a delay slot. The mode is register, so
|
2858 |
|
|
you can't have a prefix. */
|
2859 |
|
|
if ((inst_env->slot_needed) || (inst_env->prefix_found))
|
2860 |
|
|
{
|
2861 |
|
|
inst_env->invalid = 1;
|
2862 |
|
|
return;
|
2863 |
|
|
}
|
2864 |
|
|
|
2865 |
|
|
/* Just change the PC. */
|
2866 |
|
|
inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
|
2867 |
|
|
inst_env->slot_needed = 0;
|
2868 |
|
|
inst_env->prefix_found = 0;
|
2869 |
|
|
inst_env->xflag_found = 0;
|
2870 |
|
|
inst_env->disable_interrupt = 1;
|
2871 |
|
|
}
|
2872 |
|
|
|
2873 |
|
|
/* Handles the JUMP instruction for all modes except register. */
|
2874 |
|
|
|
2875 |
|
|
static void
|
2876 |
|
|
none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
|
2877 |
|
|
{
|
2878 |
|
|
unsigned long newpc;
|
2879 |
|
|
CORE_ADDR address;
|
2880 |
|
|
|
2881 |
|
|
/* It's invalid to do a JUMP in a delay slot. */
|
2882 |
|
|
if (inst_env->slot_needed)
|
2883 |
|
|
{
|
2884 |
|
|
inst_env->invalid = 1;
|
2885 |
|
|
}
|
2886 |
|
|
else
|
2887 |
|
|
{
|
2888 |
|
|
/* Check if we have a prefix. */
|
2889 |
|
|
if (inst_env->prefix_found)
|
2890 |
|
|
{
|
2891 |
|
|
check_assign (inst, inst_env);
|
2892 |
|
|
|
2893 |
|
|
/* Get the new value for the the PC. */
|
2894 |
|
|
newpc =
|
2895 |
|
|
read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
|
2896 |
|
|
4, inst_env->byte_order);
|
2897 |
|
|
}
|
2898 |
|
|
else
|
2899 |
|
|
{
|
2900 |
|
|
/* Get the new value for the PC. */
|
2901 |
|
|
address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
|
2902 |
|
|
newpc = read_memory_unsigned_integer (address,
|
2903 |
|
|
4, inst_env->byte_order);
|
2904 |
|
|
|
2905 |
|
|
/* Check if we should increment a register. */
|
2906 |
|
|
if (cris_get_mode (inst) == AUTOINC_MODE)
|
2907 |
|
|
{
|
2908 |
|
|
inst_env->reg[cris_get_operand1 (inst)] += 4;
|
2909 |
|
|
}
|
2910 |
|
|
}
|
2911 |
|
|
inst_env->reg[REG_PC] = newpc;
|
2912 |
|
|
}
|
2913 |
|
|
inst_env->slot_needed = 0;
|
2914 |
|
|
inst_env->prefix_found = 0;
|
2915 |
|
|
inst_env->xflag_found = 0;
|
2916 |
|
|
inst_env->disable_interrupt = 1;
|
2917 |
|
|
}
|
2918 |
|
|
|
2919 |
|
|
/* Handles moves to special registers (aka P-register) for all modes. */
|
2920 |
|
|
|
2921 |
|
|
static void
|
2922 |
|
|
move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
|
2923 |
|
|
inst_env_type *inst_env)
|
2924 |
|
|
{
|
2925 |
|
|
if (inst_env->prefix_found)
|
2926 |
|
|
{
|
2927 |
|
|
/* The instruction has a prefix that means we are only interested if
|
2928 |
|
|
the instruction is in assign mode. */
|
2929 |
|
|
if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
|
2930 |
|
|
{
|
2931 |
|
|
/* The prefix handles the problem if we are in a delay slot. */
|
2932 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
2933 |
|
|
{
|
2934 |
|
|
/* Just take care of the assign. */
|
2935 |
|
|
check_assign (inst, inst_env);
|
2936 |
|
|
}
|
2937 |
|
|
}
|
2938 |
|
|
}
|
2939 |
|
|
else if (cris_get_mode (inst) == AUTOINC_MODE)
|
2940 |
|
|
{
|
2941 |
|
|
/* The instruction doesn't have a prefix, the only case left that we
|
2942 |
|
|
are interested in is the autoincrement mode. */
|
2943 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
2944 |
|
|
{
|
2945 |
|
|
/* If the PC is to be incremented it's invalid to be in a
|
2946 |
|
|
delay slot. */
|
2947 |
|
|
if (inst_env->slot_needed)
|
2948 |
|
|
{
|
2949 |
|
|
inst_env->invalid = 1;
|
2950 |
|
|
return;
|
2951 |
|
|
}
|
2952 |
|
|
|
2953 |
|
|
/* The increment depends on the size of the special register. */
|
2954 |
|
|
if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
|
2955 |
|
|
{
|
2956 |
|
|
process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
|
2957 |
|
|
}
|
2958 |
|
|
else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
|
2959 |
|
|
{
|
2960 |
|
|
process_autoincrement (INST_WORD_SIZE, inst, inst_env);
|
2961 |
|
|
}
|
2962 |
|
|
else
|
2963 |
|
|
{
|
2964 |
|
|
process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
|
2965 |
|
|
}
|
2966 |
|
|
}
|
2967 |
|
|
}
|
2968 |
|
|
inst_env->slot_needed = 0;
|
2969 |
|
|
inst_env->prefix_found = 0;
|
2970 |
|
|
inst_env->xflag_found = 0;
|
2971 |
|
|
inst_env->disable_interrupt = 1;
|
2972 |
|
|
}
|
2973 |
|
|
|
2974 |
|
|
/* Handles moves from special registers (aka P-register) for all modes
|
2975 |
|
|
except register. */
|
2976 |
|
|
|
2977 |
|
|
static void
|
2978 |
|
|
none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
|
2979 |
|
|
inst_env_type *inst_env)
|
2980 |
|
|
{
|
2981 |
|
|
if (inst_env->prefix_found)
|
2982 |
|
|
{
|
2983 |
|
|
/* The instruction has a prefix that means we are only interested if
|
2984 |
|
|
the instruction is in assign mode. */
|
2985 |
|
|
if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
|
2986 |
|
|
{
|
2987 |
|
|
/* The prefix handles the problem if we are in a delay slot. */
|
2988 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
2989 |
|
|
{
|
2990 |
|
|
/* Just take care of the assign. */
|
2991 |
|
|
check_assign (inst, inst_env);
|
2992 |
|
|
}
|
2993 |
|
|
}
|
2994 |
|
|
}
|
2995 |
|
|
/* The instruction doesn't have a prefix, the only case left that we
|
2996 |
|
|
are interested in is the autoincrement mode. */
|
2997 |
|
|
else if (cris_get_mode (inst) == AUTOINC_MODE)
|
2998 |
|
|
{
|
2999 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
3000 |
|
|
{
|
3001 |
|
|
/* If the PC is to be incremented it's invalid to be in a
|
3002 |
|
|
delay slot. */
|
3003 |
|
|
if (inst_env->slot_needed)
|
3004 |
|
|
{
|
3005 |
|
|
inst_env->invalid = 1;
|
3006 |
|
|
return;
|
3007 |
|
|
}
|
3008 |
|
|
|
3009 |
|
|
/* The increment depends on the size of the special register. */
|
3010 |
|
|
if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
|
3011 |
|
|
{
|
3012 |
|
|
process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
|
3013 |
|
|
}
|
3014 |
|
|
else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
|
3015 |
|
|
{
|
3016 |
|
|
process_autoincrement (INST_WORD_SIZE, inst, inst_env);
|
3017 |
|
|
}
|
3018 |
|
|
else
|
3019 |
|
|
{
|
3020 |
|
|
process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
|
3021 |
|
|
}
|
3022 |
|
|
}
|
3023 |
|
|
}
|
3024 |
|
|
inst_env->slot_needed = 0;
|
3025 |
|
|
inst_env->prefix_found = 0;
|
3026 |
|
|
inst_env->xflag_found = 0;
|
3027 |
|
|
inst_env->disable_interrupt = 1;
|
3028 |
|
|
}
|
3029 |
|
|
|
3030 |
|
|
/* Handles moves from special registers (aka P-register) when the mode
|
3031 |
|
|
is register. */
|
3032 |
|
|
|
3033 |
|
|
static void
|
3034 |
|
|
reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
|
3035 |
|
|
{
|
3036 |
|
|
/* Register mode move from special register can't have a prefix. */
|
3037 |
|
|
if (inst_env->prefix_found)
|
3038 |
|
|
{
|
3039 |
|
|
inst_env->invalid = 1;
|
3040 |
|
|
return;
|
3041 |
|
|
}
|
3042 |
|
|
|
3043 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
3044 |
|
|
{
|
3045 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
3046 |
|
|
if (inst_env->slot_needed)
|
3047 |
|
|
{
|
3048 |
|
|
inst_env->invalid = 1;
|
3049 |
|
|
return;
|
3050 |
|
|
}
|
3051 |
|
|
/* The destination is the PC, the jump will have a delay slot. */
|
3052 |
|
|
inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
|
3053 |
|
|
inst_env->slot_needed = 1;
|
3054 |
|
|
inst_env->delay_slot_pc_active = 1;
|
3055 |
|
|
}
|
3056 |
|
|
else
|
3057 |
|
|
{
|
3058 |
|
|
/* If the destination isn't PC, there will be no jump. */
|
3059 |
|
|
inst_env->slot_needed = 0;
|
3060 |
|
|
}
|
3061 |
|
|
inst_env->prefix_found = 0;
|
3062 |
|
|
inst_env->xflag_found = 0;
|
3063 |
|
|
inst_env->disable_interrupt = 1;
|
3064 |
|
|
}
|
3065 |
|
|
|
3066 |
|
|
/* Handles the MOVEM from memory to general register instruction. */
|
3067 |
|
|
|
3068 |
|
|
static void
|
3069 |
|
|
move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
|
3070 |
|
|
{
|
3071 |
|
|
if (inst_env->prefix_found)
|
3072 |
|
|
{
|
3073 |
|
|
/* The prefix handles the problem if we are in a delay slot. Is the
|
3074 |
|
|
MOVEM instruction going to change the PC? */
|
3075 |
|
|
if (cris_get_operand2 (inst) >= REG_PC)
|
3076 |
|
|
{
|
3077 |
|
|
inst_env->reg[REG_PC] =
|
3078 |
|
|
read_memory_unsigned_integer (inst_env->prefix_value,
|
3079 |
|
|
4, inst_env->byte_order);
|
3080 |
|
|
}
|
3081 |
|
|
/* The assign value is the value after the increment. Normally, the
|
3082 |
|
|
assign value is the value before the increment. */
|
3083 |
|
|
if ((cris_get_operand1 (inst) == REG_PC)
|
3084 |
|
|
&& (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
|
3085 |
|
|
{
|
3086 |
|
|
inst_env->reg[REG_PC] = inst_env->prefix_value;
|
3087 |
|
|
inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
|
3088 |
|
|
}
|
3089 |
|
|
}
|
3090 |
|
|
else
|
3091 |
|
|
{
|
3092 |
|
|
/* Is the MOVEM instruction going to change the PC? */
|
3093 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3094 |
|
|
{
|
3095 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
3096 |
|
|
if (inst_env->slot_needed)
|
3097 |
|
|
{
|
3098 |
|
|
inst_env->invalid = 1;
|
3099 |
|
|
return;
|
3100 |
|
|
}
|
3101 |
|
|
inst_env->reg[REG_PC] =
|
3102 |
|
|
read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
|
3103 |
|
|
4, inst_env->byte_order);
|
3104 |
|
|
}
|
3105 |
|
|
/* The increment is not depending on the size, instead it's depending
|
3106 |
|
|
on the number of registers loaded from memory. */
|
3107 |
|
|
if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
|
3108 |
|
|
{
|
3109 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
3110 |
|
|
if (inst_env->slot_needed)
|
3111 |
|
|
{
|
3112 |
|
|
inst_env->invalid = 1;
|
3113 |
|
|
return;
|
3114 |
|
|
}
|
3115 |
|
|
inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
|
3116 |
|
|
}
|
3117 |
|
|
}
|
3118 |
|
|
inst_env->slot_needed = 0;
|
3119 |
|
|
inst_env->prefix_found = 0;
|
3120 |
|
|
inst_env->xflag_found = 0;
|
3121 |
|
|
inst_env->disable_interrupt = 0;
|
3122 |
|
|
}
|
3123 |
|
|
|
3124 |
|
|
/* Handles the MOVEM to memory from general register instruction. */
|
3125 |
|
|
|
3126 |
|
|
static void
|
3127 |
|
|
move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
|
3128 |
|
|
{
|
3129 |
|
|
if (inst_env->prefix_found)
|
3130 |
|
|
{
|
3131 |
|
|
/* The assign value is the value after the increment. Normally, the
|
3132 |
|
|
assign value is the value before the increment. */
|
3133 |
|
|
if ((cris_get_operand1 (inst) == REG_PC)
|
3134 |
|
|
&& (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
|
3135 |
|
|
{
|
3136 |
|
|
/* The prefix handles the problem if we are in a delay slot. */
|
3137 |
|
|
inst_env->reg[REG_PC] = inst_env->prefix_value;
|
3138 |
|
|
inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
|
3139 |
|
|
}
|
3140 |
|
|
}
|
3141 |
|
|
else
|
3142 |
|
|
{
|
3143 |
|
|
/* The increment is not depending on the size, instead it's depending
|
3144 |
|
|
on the number of registers loaded to memory. */
|
3145 |
|
|
if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
|
3146 |
|
|
{
|
3147 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
3148 |
|
|
if (inst_env->slot_needed)
|
3149 |
|
|
{
|
3150 |
|
|
inst_env->invalid = 1;
|
3151 |
|
|
return;
|
3152 |
|
|
}
|
3153 |
|
|
inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
|
3154 |
|
|
}
|
3155 |
|
|
}
|
3156 |
|
|
inst_env->slot_needed = 0;
|
3157 |
|
|
inst_env->prefix_found = 0;
|
3158 |
|
|
inst_env->xflag_found = 0;
|
3159 |
|
|
inst_env->disable_interrupt = 0;
|
3160 |
|
|
}
|
3161 |
|
|
|
3162 |
|
|
/* Handles the intructions that's not yet implemented, by setting
|
3163 |
|
|
inst_env->invalid to true. */
|
3164 |
|
|
|
3165 |
|
|
static void
|
3166 |
|
|
not_implemented_op (unsigned short inst, inst_env_type *inst_env)
|
3167 |
|
|
{
|
3168 |
|
|
inst_env->invalid = 1;
|
3169 |
|
|
}
|
3170 |
|
|
|
3171 |
|
|
/* Handles the XOR instruction. */
|
3172 |
|
|
|
3173 |
|
|
static void
|
3174 |
|
|
xor_op (unsigned short inst, inst_env_type *inst_env)
|
3175 |
|
|
{
|
3176 |
|
|
/* XOR can't have a prefix. */
|
3177 |
|
|
if (inst_env->prefix_found)
|
3178 |
|
|
{
|
3179 |
|
|
inst_env->invalid = 1;
|
3180 |
|
|
return;
|
3181 |
|
|
}
|
3182 |
|
|
|
3183 |
|
|
/* Check if the PC is the target. */
|
3184 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3185 |
|
|
{
|
3186 |
|
|
/* It's invalid to change the PC in a delay slot. */
|
3187 |
|
|
if (inst_env->slot_needed)
|
3188 |
|
|
{
|
3189 |
|
|
inst_env->invalid = 1;
|
3190 |
|
|
return;
|
3191 |
|
|
}
|
3192 |
|
|
inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
|
3193 |
|
|
}
|
3194 |
|
|
inst_env->slot_needed = 0;
|
3195 |
|
|
inst_env->prefix_found = 0;
|
3196 |
|
|
inst_env->xflag_found = 0;
|
3197 |
|
|
inst_env->disable_interrupt = 0;
|
3198 |
|
|
}
|
3199 |
|
|
|
3200 |
|
|
/* Handles the MULS instruction. */
|
3201 |
|
|
|
3202 |
|
|
static void
|
3203 |
|
|
muls_op (unsigned short inst, inst_env_type *inst_env)
|
3204 |
|
|
{
|
3205 |
|
|
/* MULS/U can't have a prefix. */
|
3206 |
|
|
if (inst_env->prefix_found)
|
3207 |
|
|
{
|
3208 |
|
|
inst_env->invalid = 1;
|
3209 |
|
|
return;
|
3210 |
|
|
}
|
3211 |
|
|
|
3212 |
|
|
/* Consider it invalid if the PC is the target. */
|
3213 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3214 |
|
|
{
|
3215 |
|
|
inst_env->invalid = 1;
|
3216 |
|
|
return;
|
3217 |
|
|
}
|
3218 |
|
|
inst_env->slot_needed = 0;
|
3219 |
|
|
inst_env->prefix_found = 0;
|
3220 |
|
|
inst_env->xflag_found = 0;
|
3221 |
|
|
inst_env->disable_interrupt = 0;
|
3222 |
|
|
}
|
3223 |
|
|
|
3224 |
|
|
/* Handles the MULU instruction. */
|
3225 |
|
|
|
3226 |
|
|
static void
|
3227 |
|
|
mulu_op (unsigned short inst, inst_env_type *inst_env)
|
3228 |
|
|
{
|
3229 |
|
|
/* MULS/U can't have a prefix. */
|
3230 |
|
|
if (inst_env->prefix_found)
|
3231 |
|
|
{
|
3232 |
|
|
inst_env->invalid = 1;
|
3233 |
|
|
return;
|
3234 |
|
|
}
|
3235 |
|
|
|
3236 |
|
|
/* Consider it invalid if the PC is the target. */
|
3237 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3238 |
|
|
{
|
3239 |
|
|
inst_env->invalid = 1;
|
3240 |
|
|
return;
|
3241 |
|
|
}
|
3242 |
|
|
inst_env->slot_needed = 0;
|
3243 |
|
|
inst_env->prefix_found = 0;
|
3244 |
|
|
inst_env->xflag_found = 0;
|
3245 |
|
|
inst_env->disable_interrupt = 0;
|
3246 |
|
|
}
|
3247 |
|
|
|
3248 |
|
|
/* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
|
3249 |
|
|
The MOVE instruction is the move from source to register. */
|
3250 |
|
|
|
3251 |
|
|
static void
|
3252 |
|
|
add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
|
3253 |
|
|
unsigned long source1, unsigned long source2)
|
3254 |
|
|
{
|
3255 |
|
|
unsigned long pc_mask;
|
3256 |
|
|
unsigned long operation_mask;
|
3257 |
|
|
|
3258 |
|
|
/* Find out how many bits the operation should apply to. */
|
3259 |
|
|
if (cris_get_size (inst) == INST_BYTE_SIZE)
|
3260 |
|
|
{
|
3261 |
|
|
pc_mask = 0xFFFFFF00;
|
3262 |
|
|
operation_mask = 0xFF;
|
3263 |
|
|
}
|
3264 |
|
|
else if (cris_get_size (inst) == INST_WORD_SIZE)
|
3265 |
|
|
{
|
3266 |
|
|
pc_mask = 0xFFFF0000;
|
3267 |
|
|
operation_mask = 0xFFFF;
|
3268 |
|
|
}
|
3269 |
|
|
else if (cris_get_size (inst) == INST_DWORD_SIZE)
|
3270 |
|
|
{
|
3271 |
|
|
pc_mask = 0x0;
|
3272 |
|
|
operation_mask = 0xFFFFFFFF;
|
3273 |
|
|
}
|
3274 |
|
|
else
|
3275 |
|
|
{
|
3276 |
|
|
/* The size is out of range. */
|
3277 |
|
|
inst_env->invalid = 1;
|
3278 |
|
|
return;
|
3279 |
|
|
}
|
3280 |
|
|
|
3281 |
|
|
/* The instruction just works on uw_operation_mask bits. */
|
3282 |
|
|
source2 &= operation_mask;
|
3283 |
|
|
source1 &= operation_mask;
|
3284 |
|
|
|
3285 |
|
|
/* Now calculate the result. The opcode's 3 first bits separates
|
3286 |
|
|
the different actions. */
|
3287 |
|
|
switch (cris_get_opcode (inst) & 7)
|
3288 |
|
|
{
|
3289 |
|
|
case 0: /* add */
|
3290 |
|
|
source1 += source2;
|
3291 |
|
|
break;
|
3292 |
|
|
|
3293 |
|
|
case 1: /* move */
|
3294 |
|
|
source1 = source2;
|
3295 |
|
|
break;
|
3296 |
|
|
|
3297 |
|
|
case 2: /* subtract */
|
3298 |
|
|
source1 -= source2;
|
3299 |
|
|
break;
|
3300 |
|
|
|
3301 |
|
|
case 3: /* compare */
|
3302 |
|
|
break;
|
3303 |
|
|
|
3304 |
|
|
case 4: /* and */
|
3305 |
|
|
source1 &= source2;
|
3306 |
|
|
break;
|
3307 |
|
|
|
3308 |
|
|
case 5: /* or */
|
3309 |
|
|
source1 |= source2;
|
3310 |
|
|
break;
|
3311 |
|
|
|
3312 |
|
|
default:
|
3313 |
|
|
inst_env->invalid = 1;
|
3314 |
|
|
return;
|
3315 |
|
|
|
3316 |
|
|
break;
|
3317 |
|
|
}
|
3318 |
|
|
|
3319 |
|
|
/* Make sure that the result doesn't contain more than the instruction
|
3320 |
|
|
size bits. */
|
3321 |
|
|
source2 &= operation_mask;
|
3322 |
|
|
|
3323 |
|
|
/* Calculate the new breakpoint address. */
|
3324 |
|
|
inst_env->reg[REG_PC] &= pc_mask;
|
3325 |
|
|
inst_env->reg[REG_PC] |= source1;
|
3326 |
|
|
|
3327 |
|
|
}
|
3328 |
|
|
|
3329 |
|
|
/* Extends the value from either byte or word size to a dword. If the mode
|
3330 |
|
|
is zero extend then the value is extended with zero. If instead the mode
|
3331 |
|
|
is signed extend the sign bit of the value is taken into consideration. */
|
3332 |
|
|
|
3333 |
|
|
static unsigned long
|
3334 |
|
|
do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
|
3335 |
|
|
{
|
3336 |
|
|
/* The size can be either byte or word, check which one it is.
|
3337 |
|
|
Don't check the highest bit, it's indicating if it's a zero
|
3338 |
|
|
or sign extend. */
|
3339 |
|
|
if (cris_get_size (*inst) & INST_WORD_SIZE)
|
3340 |
|
|
{
|
3341 |
|
|
/* Word size. */
|
3342 |
|
|
value &= 0xFFFF;
|
3343 |
|
|
|
3344 |
|
|
/* Check if the instruction is signed extend. If so, check if value has
|
3345 |
|
|
the sign bit on. */
|
3346 |
|
|
if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
|
3347 |
|
|
{
|
3348 |
|
|
value |= SIGNED_WORD_EXTEND_MASK;
|
3349 |
|
|
}
|
3350 |
|
|
}
|
3351 |
|
|
else
|
3352 |
|
|
{
|
3353 |
|
|
/* Byte size. */
|
3354 |
|
|
value &= 0xFF;
|
3355 |
|
|
|
3356 |
|
|
/* Check if the instruction is signed extend. If so, check if value has
|
3357 |
|
|
the sign bit on. */
|
3358 |
|
|
if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
|
3359 |
|
|
{
|
3360 |
|
|
value |= SIGNED_BYTE_EXTEND_MASK;
|
3361 |
|
|
}
|
3362 |
|
|
}
|
3363 |
|
|
/* The size should now be dword. */
|
3364 |
|
|
cris_set_size_to_dword (inst);
|
3365 |
|
|
return value;
|
3366 |
|
|
}
|
3367 |
|
|
|
3368 |
|
|
/* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
|
3369 |
|
|
instruction. The MOVE instruction is the move from source to register. */
|
3370 |
|
|
|
3371 |
|
|
static void
|
3372 |
|
|
reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
|
3373 |
|
|
inst_env_type *inst_env)
|
3374 |
|
|
{
|
3375 |
|
|
unsigned long operand1;
|
3376 |
|
|
unsigned long operand2;
|
3377 |
|
|
|
3378 |
|
|
/* It's invalid to have a prefix to the instruction. This is a register
|
3379 |
|
|
mode instruction and can't have a prefix. */
|
3380 |
|
|
if (inst_env->prefix_found)
|
3381 |
|
|
{
|
3382 |
|
|
inst_env->invalid = 1;
|
3383 |
|
|
return;
|
3384 |
|
|
}
|
3385 |
|
|
/* Check if the instruction has PC as its target. */
|
3386 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3387 |
|
|
{
|
3388 |
|
|
if (inst_env->slot_needed)
|
3389 |
|
|
{
|
3390 |
|
|
inst_env->invalid = 1;
|
3391 |
|
|
return;
|
3392 |
|
|
}
|
3393 |
|
|
/* The instruction has the PC as its target register. */
|
3394 |
|
|
operand1 = inst_env->reg[cris_get_operand1 (inst)];
|
3395 |
|
|
operand2 = inst_env->reg[REG_PC];
|
3396 |
|
|
|
3397 |
|
|
/* Check if it's a extend, signed or zero instruction. */
|
3398 |
|
|
if (cris_get_opcode (inst) < 4)
|
3399 |
|
|
{
|
3400 |
|
|
operand1 = do_sign_or_zero_extend (operand1, &inst);
|
3401 |
|
|
}
|
3402 |
|
|
/* Calculate the PC value after the instruction, i.e. where the
|
3403 |
|
|
breakpoint should be. The order of the udw_operands is vital. */
|
3404 |
|
|
add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
|
3405 |
|
|
}
|
3406 |
|
|
inst_env->slot_needed = 0;
|
3407 |
|
|
inst_env->prefix_found = 0;
|
3408 |
|
|
inst_env->xflag_found = 0;
|
3409 |
|
|
inst_env->disable_interrupt = 0;
|
3410 |
|
|
}
|
3411 |
|
|
|
3412 |
|
|
/* Returns the data contained at address. The size of the data is derived from
|
3413 |
|
|
the size of the operation. If the instruction is a zero or signed
|
3414 |
|
|
extend instruction, the size field is changed in instruction. */
|
3415 |
|
|
|
3416 |
|
|
static unsigned long
|
3417 |
|
|
get_data_from_address (unsigned short *inst, CORE_ADDR address, enum bfd_endian byte_order)
|
3418 |
|
|
{
|
3419 |
|
|
int size = cris_get_size (*inst);
|
3420 |
|
|
unsigned long value;
|
3421 |
|
|
|
3422 |
|
|
/* If it's an extend instruction we don't want the signed extend bit,
|
3423 |
|
|
because it influences the size. */
|
3424 |
|
|
if (cris_get_opcode (*inst) < 4)
|
3425 |
|
|
{
|
3426 |
|
|
size &= ~SIGNED_EXTEND_BIT_MASK;
|
3427 |
|
|
}
|
3428 |
|
|
/* Is there a need for checking the size? Size should contain the number of
|
3429 |
|
|
bytes to read. */
|
3430 |
|
|
size = 1 << size;
|
3431 |
|
|
value = read_memory_unsigned_integer (address, size, byte_order);
|
3432 |
|
|
|
3433 |
|
|
/* Check if it's an extend, signed or zero instruction. */
|
3434 |
|
|
if (cris_get_opcode (*inst) < 4)
|
3435 |
|
|
{
|
3436 |
|
|
value = do_sign_or_zero_extend (value, inst);
|
3437 |
|
|
}
|
3438 |
|
|
return value;
|
3439 |
|
|
}
|
3440 |
|
|
|
3441 |
|
|
/* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
|
3442 |
|
|
instructions. The MOVE instruction is the move from source to register. */
|
3443 |
|
|
|
3444 |
|
|
static void
|
3445 |
|
|
handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
|
3446 |
|
|
inst_env_type *inst_env)
|
3447 |
|
|
{
|
3448 |
|
|
unsigned long operand2;
|
3449 |
|
|
unsigned long operand3;
|
3450 |
|
|
|
3451 |
|
|
check_assign (inst, inst_env);
|
3452 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3453 |
|
|
{
|
3454 |
|
|
operand2 = inst_env->reg[REG_PC];
|
3455 |
|
|
|
3456 |
|
|
/* Get the value of the third operand. */
|
3457 |
|
|
operand3 = get_data_from_address (&inst, inst_env->prefix_value,
|
3458 |
|
|
inst_env->byte_order);
|
3459 |
|
|
|
3460 |
|
|
/* Calculate the PC value after the instruction, i.e. where the
|
3461 |
|
|
breakpoint should be. The order of the udw_operands is vital. */
|
3462 |
|
|
add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
|
3463 |
|
|
}
|
3464 |
|
|
inst_env->slot_needed = 0;
|
3465 |
|
|
inst_env->prefix_found = 0;
|
3466 |
|
|
inst_env->xflag_found = 0;
|
3467 |
|
|
inst_env->disable_interrupt = 0;
|
3468 |
|
|
}
|
3469 |
|
|
|
3470 |
|
|
/* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
|
3471 |
|
|
OR instructions. Note that for this to work as expected, the calling
|
3472 |
|
|
function must have made sure that there is a prefix to this instruction. */
|
3473 |
|
|
|
3474 |
|
|
static void
|
3475 |
|
|
three_operand_add_sub_cmp_and_or_op (unsigned short inst,
|
3476 |
|
|
inst_env_type *inst_env)
|
3477 |
|
|
{
|
3478 |
|
|
unsigned long operand2;
|
3479 |
|
|
unsigned long operand3;
|
3480 |
|
|
|
3481 |
|
|
if (cris_get_operand1 (inst) == REG_PC)
|
3482 |
|
|
{
|
3483 |
|
|
/* The PC will be changed by the instruction. */
|
3484 |
|
|
operand2 = inst_env->reg[cris_get_operand2 (inst)];
|
3485 |
|
|
|
3486 |
|
|
/* Get the value of the third operand. */
|
3487 |
|
|
operand3 = get_data_from_address (&inst, inst_env->prefix_value,
|
3488 |
|
|
inst_env->byte_order);
|
3489 |
|
|
|
3490 |
|
|
/* Calculate the PC value after the instruction, i.e. where the
|
3491 |
|
|
breakpoint should be. */
|
3492 |
|
|
add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
|
3493 |
|
|
}
|
3494 |
|
|
inst_env->slot_needed = 0;
|
3495 |
|
|
inst_env->prefix_found = 0;
|
3496 |
|
|
inst_env->xflag_found = 0;
|
3497 |
|
|
inst_env->disable_interrupt = 0;
|
3498 |
|
|
}
|
3499 |
|
|
|
3500 |
|
|
/* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
|
3501 |
|
|
instructions. The MOVE instruction is the move from source to register. */
|
3502 |
|
|
|
3503 |
|
|
static void
|
3504 |
|
|
handle_prefix_index_mode_for_aritm_op (unsigned short inst,
|
3505 |
|
|
inst_env_type *inst_env)
|
3506 |
|
|
{
|
3507 |
|
|
if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
|
3508 |
|
|
{
|
3509 |
|
|
/* If the instruction is MOVE it's invalid. If the instruction is ADD,
|
3510 |
|
|
SUB, AND or OR something weird is going on (if everything works these
|
3511 |
|
|
instructions should end up in the three operand version). */
|
3512 |
|
|
inst_env->invalid = 1;
|
3513 |
|
|
return;
|
3514 |
|
|
}
|
3515 |
|
|
else
|
3516 |
|
|
{
|
3517 |
|
|
/* three_operand_add_sub_cmp_and_or does the same as we should do here
|
3518 |
|
|
so use it. */
|
3519 |
|
|
three_operand_add_sub_cmp_and_or_op (inst, inst_env);
|
3520 |
|
|
}
|
3521 |
|
|
inst_env->slot_needed = 0;
|
3522 |
|
|
inst_env->prefix_found = 0;
|
3523 |
|
|
inst_env->xflag_found = 0;
|
3524 |
|
|
inst_env->disable_interrupt = 0;
|
3525 |
|
|
}
|
3526 |
|
|
|
3527 |
|
|
/* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
|
3528 |
|
|
CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
|
3529 |
|
|
source to register. */
|
3530 |
|
|
|
3531 |
|
|
static void
|
3532 |
|
|
handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
|
3533 |
|
|
inst_env_type *inst_env)
|
3534 |
|
|
{
|
3535 |
|
|
unsigned long operand1;
|
3536 |
|
|
unsigned long operand2;
|
3537 |
|
|
unsigned long operand3;
|
3538 |
|
|
int size;
|
3539 |
|
|
|
3540 |
|
|
/* The instruction is either an indirect or autoincrement addressing mode.
|
3541 |
|
|
Check if the destination register is the PC. */
|
3542 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3543 |
|
|
{
|
3544 |
|
|
/* Must be done here, get_data_from_address may change the size
|
3545 |
|
|
field. */
|
3546 |
|
|
size = cris_get_size (inst);
|
3547 |
|
|
operand2 = inst_env->reg[REG_PC];
|
3548 |
|
|
|
3549 |
|
|
/* Get the value of the third operand, i.e. the indirect operand. */
|
3550 |
|
|
operand1 = inst_env->reg[cris_get_operand1 (inst)];
|
3551 |
|
|
operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
|
3552 |
|
|
|
3553 |
|
|
/* Calculate the PC value after the instruction, i.e. where the
|
3554 |
|
|
breakpoint should be. The order of the udw_operands is vital. */
|
3555 |
|
|
add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
|
3556 |
|
|
}
|
3557 |
|
|
/* If this is an autoincrement addressing mode, check if the increment
|
3558 |
|
|
changes the PC. */
|
3559 |
|
|
if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
|
3560 |
|
|
{
|
3561 |
|
|
/* Get the size field. */
|
3562 |
|
|
size = cris_get_size (inst);
|
3563 |
|
|
|
3564 |
|
|
/* If it's an extend instruction we don't want the signed extend bit,
|
3565 |
|
|
because it influences the size. */
|
3566 |
|
|
if (cris_get_opcode (inst) < 4)
|
3567 |
|
|
{
|
3568 |
|
|
size &= ~SIGNED_EXTEND_BIT_MASK;
|
3569 |
|
|
}
|
3570 |
|
|
process_autoincrement (size, inst, inst_env);
|
3571 |
|
|
}
|
3572 |
|
|
inst_env->slot_needed = 0;
|
3573 |
|
|
inst_env->prefix_found = 0;
|
3574 |
|
|
inst_env->xflag_found = 0;
|
3575 |
|
|
inst_env->disable_interrupt = 0;
|
3576 |
|
|
}
|
3577 |
|
|
|
3578 |
|
|
/* Handles the two-operand addressing mode, all modes except register, for
|
3579 |
|
|
the ADD, SUB CMP, AND and OR instruction. */
|
3580 |
|
|
|
3581 |
|
|
static void
|
3582 |
|
|
none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
|
3583 |
|
|
inst_env_type *inst_env)
|
3584 |
|
|
{
|
3585 |
|
|
if (inst_env->prefix_found)
|
3586 |
|
|
{
|
3587 |
|
|
if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
|
3588 |
|
|
{
|
3589 |
|
|
handle_prefix_index_mode_for_aritm_op (inst, inst_env);
|
3590 |
|
|
}
|
3591 |
|
|
else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
|
3592 |
|
|
{
|
3593 |
|
|
handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
|
3594 |
|
|
}
|
3595 |
|
|
else
|
3596 |
|
|
{
|
3597 |
|
|
/* The mode is invalid for a prefixed base instruction. */
|
3598 |
|
|
inst_env->invalid = 1;
|
3599 |
|
|
return;
|
3600 |
|
|
}
|
3601 |
|
|
}
|
3602 |
|
|
else
|
3603 |
|
|
{
|
3604 |
|
|
handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
|
3605 |
|
|
}
|
3606 |
|
|
}
|
3607 |
|
|
|
3608 |
|
|
/* Handles the quick addressing mode for the ADD and SUB instruction. */
|
3609 |
|
|
|
3610 |
|
|
static void
|
3611 |
|
|
quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
|
3612 |
|
|
{
|
3613 |
|
|
unsigned long operand1;
|
3614 |
|
|
unsigned long operand2;
|
3615 |
|
|
|
3616 |
|
|
/* It's a bad idea to be in a prefix instruction now. This is a quick mode
|
3617 |
|
|
instruction and can't have a prefix. */
|
3618 |
|
|
if (inst_env->prefix_found)
|
3619 |
|
|
{
|
3620 |
|
|
inst_env->invalid = 1;
|
3621 |
|
|
return;
|
3622 |
|
|
}
|
3623 |
|
|
|
3624 |
|
|
/* Check if the instruction has PC as its target. */
|
3625 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3626 |
|
|
{
|
3627 |
|
|
if (inst_env->slot_needed)
|
3628 |
|
|
{
|
3629 |
|
|
inst_env->invalid = 1;
|
3630 |
|
|
return;
|
3631 |
|
|
}
|
3632 |
|
|
operand1 = cris_get_quick_value (inst);
|
3633 |
|
|
operand2 = inst_env->reg[REG_PC];
|
3634 |
|
|
|
3635 |
|
|
/* The size should now be dword. */
|
3636 |
|
|
cris_set_size_to_dword (&inst);
|
3637 |
|
|
|
3638 |
|
|
/* Calculate the PC value after the instruction, i.e. where the
|
3639 |
|
|
breakpoint should be. */
|
3640 |
|
|
add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
|
3641 |
|
|
}
|
3642 |
|
|
inst_env->slot_needed = 0;
|
3643 |
|
|
inst_env->prefix_found = 0;
|
3644 |
|
|
inst_env->xflag_found = 0;
|
3645 |
|
|
inst_env->disable_interrupt = 0;
|
3646 |
|
|
}
|
3647 |
|
|
|
3648 |
|
|
/* Handles the quick addressing mode for the CMP, AND and OR instruction. */
|
3649 |
|
|
|
3650 |
|
|
static void
|
3651 |
|
|
quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
|
3652 |
|
|
{
|
3653 |
|
|
unsigned long operand1;
|
3654 |
|
|
unsigned long operand2;
|
3655 |
|
|
|
3656 |
|
|
/* It's a bad idea to be in a prefix instruction now. This is a quick mode
|
3657 |
|
|
instruction and can't have a prefix. */
|
3658 |
|
|
if (inst_env->prefix_found)
|
3659 |
|
|
{
|
3660 |
|
|
inst_env->invalid = 1;
|
3661 |
|
|
return;
|
3662 |
|
|
}
|
3663 |
|
|
/* Check if the instruction has PC as its target. */
|
3664 |
|
|
if (cris_get_operand2 (inst) == REG_PC)
|
3665 |
|
|
{
|
3666 |
|
|
if (inst_env->slot_needed)
|
3667 |
|
|
{
|
3668 |
|
|
inst_env->invalid = 1;
|
3669 |
|
|
return;
|
3670 |
|
|
}
|
3671 |
|
|
/* The instruction has the PC as its target register. */
|
3672 |
|
|
operand1 = cris_get_quick_value (inst);
|
3673 |
|
|
operand2 = inst_env->reg[REG_PC];
|
3674 |
|
|
|
3675 |
|
|
/* The quick value is signed, so check if we must do a signed extend. */
|
3676 |
|
|
if (operand1 & SIGNED_QUICK_VALUE_MASK)
|
3677 |
|
|
{
|
3678 |
|
|
/* sign extend */
|
3679 |
|
|
operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
|
3680 |
|
|
}
|
3681 |
|
|
/* The size should now be dword. */
|
3682 |
|
|
cris_set_size_to_dword (&inst);
|
3683 |
|
|
|
3684 |
|
|
/* Calculate the PC value after the instruction, i.e. where the
|
3685 |
|
|
breakpoint should be. */
|
3686 |
|
|
add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
|
3687 |
|
|
}
|
3688 |
|
|
inst_env->slot_needed = 0;
|
3689 |
|
|
inst_env->prefix_found = 0;
|
3690 |
|
|
inst_env->xflag_found = 0;
|
3691 |
|
|
inst_env->disable_interrupt = 0;
|
3692 |
|
|
}
|
3693 |
|
|
|
3694 |
|
|
/* Translate op_type to a function and call it. */
|
3695 |
|
|
|
3696 |
|
|
static void
|
3697 |
|
|
cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
|
3698 |
|
|
unsigned short inst, inst_env_type *inst_env)
|
3699 |
|
|
{
|
3700 |
|
|
switch (op_type)
|
3701 |
|
|
{
|
3702 |
|
|
case cris_not_implemented_op:
|
3703 |
|
|
not_implemented_op (inst, inst_env);
|
3704 |
|
|
break;
|
3705 |
|
|
|
3706 |
|
|
case cris_abs_op:
|
3707 |
|
|
abs_op (inst, inst_env);
|
3708 |
|
|
break;
|
3709 |
|
|
|
3710 |
|
|
case cris_addi_op:
|
3711 |
|
|
addi_op (inst, inst_env);
|
3712 |
|
|
break;
|
3713 |
|
|
|
3714 |
|
|
case cris_asr_op:
|
3715 |
|
|
asr_op (inst, inst_env);
|
3716 |
|
|
break;
|
3717 |
|
|
|
3718 |
|
|
case cris_asrq_op:
|
3719 |
|
|
asrq_op (inst, inst_env);
|
3720 |
|
|
break;
|
3721 |
|
|
|
3722 |
|
|
case cris_ax_ei_setf_op:
|
3723 |
|
|
ax_ei_setf_op (inst, inst_env);
|
3724 |
|
|
break;
|
3725 |
|
|
|
3726 |
|
|
case cris_bdap_prefix:
|
3727 |
|
|
bdap_prefix (inst, inst_env);
|
3728 |
|
|
break;
|
3729 |
|
|
|
3730 |
|
|
case cris_biap_prefix:
|
3731 |
|
|
biap_prefix (inst, inst_env);
|
3732 |
|
|
break;
|
3733 |
|
|
|
3734 |
|
|
case cris_break_op:
|
3735 |
|
|
break_op (inst, inst_env);
|
3736 |
|
|
break;
|
3737 |
|
|
|
3738 |
|
|
case cris_btst_nop_op:
|
3739 |
|
|
btst_nop_op (inst, inst_env);
|
3740 |
|
|
break;
|
3741 |
|
|
|
3742 |
|
|
case cris_clearf_di_op:
|
3743 |
|
|
clearf_di_op (inst, inst_env);
|
3744 |
|
|
break;
|
3745 |
|
|
|
3746 |
|
|
case cris_dip_prefix:
|
3747 |
|
|
dip_prefix (inst, inst_env);
|
3748 |
|
|
break;
|
3749 |
|
|
|
3750 |
|
|
case cris_dstep_logshift_mstep_neg_not_op:
|
3751 |
|
|
dstep_logshift_mstep_neg_not_op (inst, inst_env);
|
3752 |
|
|
break;
|
3753 |
|
|
|
3754 |
|
|
case cris_eight_bit_offset_branch_op:
|
3755 |
|
|
eight_bit_offset_branch_op (inst, inst_env);
|
3756 |
|
|
break;
|
3757 |
|
|
|
3758 |
|
|
case cris_move_mem_to_reg_movem_op:
|
3759 |
|
|
move_mem_to_reg_movem_op (inst, inst_env);
|
3760 |
|
|
break;
|
3761 |
|
|
|
3762 |
|
|
case cris_move_reg_to_mem_movem_op:
|
3763 |
|
|
move_reg_to_mem_movem_op (inst, inst_env);
|
3764 |
|
|
break;
|
3765 |
|
|
|
3766 |
|
|
case cris_move_to_preg_op:
|
3767 |
|
|
move_to_preg_op (gdbarch, inst, inst_env);
|
3768 |
|
|
break;
|
3769 |
|
|
|
3770 |
|
|
case cris_muls_op:
|
3771 |
|
|
muls_op (inst, inst_env);
|
3772 |
|
|
break;
|
3773 |
|
|
|
3774 |
|
|
case cris_mulu_op:
|
3775 |
|
|
mulu_op (inst, inst_env);
|
3776 |
|
|
break;
|
3777 |
|
|
|
3778 |
|
|
case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
|
3779 |
|
|
none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
|
3780 |
|
|
break;
|
3781 |
|
|
|
3782 |
|
|
case cris_none_reg_mode_clear_test_op:
|
3783 |
|
|
none_reg_mode_clear_test_op (inst, inst_env);
|
3784 |
|
|
break;
|
3785 |
|
|
|
3786 |
|
|
case cris_none_reg_mode_jump_op:
|
3787 |
|
|
none_reg_mode_jump_op (inst, inst_env);
|
3788 |
|
|
break;
|
3789 |
|
|
|
3790 |
|
|
case cris_none_reg_mode_move_from_preg_op:
|
3791 |
|
|
none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
|
3792 |
|
|
break;
|
3793 |
|
|
|
3794 |
|
|
case cris_quick_mode_add_sub_op:
|
3795 |
|
|
quick_mode_add_sub_op (inst, inst_env);
|
3796 |
|
|
break;
|
3797 |
|
|
|
3798 |
|
|
case cris_quick_mode_and_cmp_move_or_op:
|
3799 |
|
|
quick_mode_and_cmp_move_or_op (inst, inst_env);
|
3800 |
|
|
break;
|
3801 |
|
|
|
3802 |
|
|
case cris_quick_mode_bdap_prefix:
|
3803 |
|
|
quick_mode_bdap_prefix (inst, inst_env);
|
3804 |
|
|
break;
|
3805 |
|
|
|
3806 |
|
|
case cris_reg_mode_add_sub_cmp_and_or_move_op:
|
3807 |
|
|
reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
|
3808 |
|
|
break;
|
3809 |
|
|
|
3810 |
|
|
case cris_reg_mode_clear_op:
|
3811 |
|
|
reg_mode_clear_op (inst, inst_env);
|
3812 |
|
|
break;
|
3813 |
|
|
|
3814 |
|
|
case cris_reg_mode_jump_op:
|
3815 |
|
|
reg_mode_jump_op (inst, inst_env);
|
3816 |
|
|
break;
|
3817 |
|
|
|
3818 |
|
|
case cris_reg_mode_move_from_preg_op:
|
3819 |
|
|
reg_mode_move_from_preg_op (inst, inst_env);
|
3820 |
|
|
break;
|
3821 |
|
|
|
3822 |
|
|
case cris_reg_mode_test_op:
|
3823 |
|
|
reg_mode_test_op (inst, inst_env);
|
3824 |
|
|
break;
|
3825 |
|
|
|
3826 |
|
|
case cris_scc_op:
|
3827 |
|
|
scc_op (inst, inst_env);
|
3828 |
|
|
break;
|
3829 |
|
|
|
3830 |
|
|
case cris_sixteen_bit_offset_branch_op:
|
3831 |
|
|
sixteen_bit_offset_branch_op (inst, inst_env);
|
3832 |
|
|
break;
|
3833 |
|
|
|
3834 |
|
|
case cris_three_operand_add_sub_cmp_and_or_op:
|
3835 |
|
|
three_operand_add_sub_cmp_and_or_op (inst, inst_env);
|
3836 |
|
|
break;
|
3837 |
|
|
|
3838 |
|
|
case cris_three_operand_bound_op:
|
3839 |
|
|
three_operand_bound_op (inst, inst_env);
|
3840 |
|
|
break;
|
3841 |
|
|
|
3842 |
|
|
case cris_two_operand_bound_op:
|
3843 |
|
|
two_operand_bound_op (inst, inst_env);
|
3844 |
|
|
break;
|
3845 |
|
|
|
3846 |
|
|
case cris_xor_op:
|
3847 |
|
|
xor_op (inst, inst_env);
|
3848 |
|
|
break;
|
3849 |
|
|
}
|
3850 |
|
|
}
|
3851 |
|
|
|
3852 |
|
|
/* This wrapper is to avoid cris_get_assembler being called before
|
3853 |
|
|
exec_bfd has been set. */
|
3854 |
|
|
|
3855 |
|
|
static int
|
3856 |
|
|
cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
|
3857 |
|
|
{
|
3858 |
|
|
int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
|
3859 |
|
|
/* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
|
3860 |
|
|
disassembler, even when there is no BFD. Does something like
|
3861 |
|
|
"gdb; target remote; disassmeble *0x123" work? */
|
3862 |
|
|
gdb_assert (exec_bfd != NULL);
|
3863 |
|
|
print_insn = cris_get_disassembler (exec_bfd);
|
3864 |
|
|
gdb_assert (print_insn != NULL);
|
3865 |
|
|
return print_insn (addr, info);
|
3866 |
|
|
}
|
3867 |
|
|
|
3868 |
|
|
/* Copied from <asm/elf.h>. */
|
3869 |
|
|
typedef unsigned long elf_greg_t;
|
3870 |
|
|
|
3871 |
|
|
/* Same as user_regs_struct struct in <asm/user.h>. */
|
3872 |
|
|
#define CRISV10_ELF_NGREG 35
|
3873 |
|
|
typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
|
3874 |
|
|
|
3875 |
|
|
#define CRISV32_ELF_NGREG 32
|
3876 |
|
|
typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
|
3877 |
|
|
|
3878 |
|
|
/* Unpack an elf_gregset_t into GDB's register cache. */
|
3879 |
|
|
|
3880 |
|
|
static void
|
3881 |
|
|
cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
|
3882 |
|
|
{
|
3883 |
|
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
3884 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
3885 |
|
|
int i;
|
3886 |
|
|
elf_greg_t *regp = *gregsetp;
|
3887 |
|
|
static char zerobuf[4] = {0};
|
3888 |
|
|
|
3889 |
|
|
/* The kernel dumps all 32 registers as unsigned longs, but supply_register
|
3890 |
|
|
knows about the actual size of each register so that's no problem. */
|
3891 |
|
|
for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
|
3892 |
|
|
{
|
3893 |
|
|
regcache_raw_supply (regcache, i, (char *)®p[i]);
|
3894 |
|
|
}
|
3895 |
|
|
|
3896 |
|
|
if (tdep->cris_version == 32)
|
3897 |
|
|
{
|
3898 |
|
|
/* Needed to set pseudo-register PC for CRISv32. */
|
3899 |
|
|
/* FIXME: If ERP is in a delay slot at this point then the PC will
|
3900 |
|
|
be wrong. Issue a warning to alert the user. */
|
3901 |
|
|
regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
|
3902 |
|
|
(char *)®p[ERP_REGNUM]);
|
3903 |
|
|
|
3904 |
|
|
if (*(char *)®p[ERP_REGNUM] & 0x1)
|
3905 |
|
|
fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
|
3906 |
|
|
}
|
3907 |
|
|
}
|
3908 |
|
|
|
3909 |
|
|
/* Use a local version of this function to get the correct types for
|
3910 |
|
|
regsets, until multi-arch core support is ready. */
|
3911 |
|
|
|
3912 |
|
|
static void
|
3913 |
|
|
fetch_core_registers (struct regcache *regcache,
|
3914 |
|
|
char *core_reg_sect, unsigned core_reg_size,
|
3915 |
|
|
int which, CORE_ADDR reg_addr)
|
3916 |
|
|
{
|
3917 |
|
|
elf_gregset_t gregset;
|
3918 |
|
|
|
3919 |
|
|
switch (which)
|
3920 |
|
|
{
|
3921 |
|
|
case 0:
|
3922 |
|
|
if (core_reg_size != sizeof (elf_gregset_t)
|
3923 |
|
|
&& core_reg_size != sizeof (crisv32_elf_gregset_t))
|
3924 |
|
|
{
|
3925 |
|
|
warning (_("wrong size gregset struct in core file"));
|
3926 |
|
|
}
|
3927 |
|
|
else
|
3928 |
|
|
{
|
3929 |
|
|
memcpy (&gregset, core_reg_sect, sizeof (gregset));
|
3930 |
|
|
cris_supply_gregset (regcache, &gregset);
|
3931 |
|
|
}
|
3932 |
|
|
|
3933 |
|
|
default:
|
3934 |
|
|
/* We've covered all the kinds of registers we know about here,
|
3935 |
|
|
so this must be something we wouldn't know what to do with
|
3936 |
|
|
anyway. Just ignore it. */
|
3937 |
|
|
break;
|
3938 |
|
|
}
|
3939 |
|
|
}
|
3940 |
|
|
|
3941 |
|
|
static struct core_fns cris_elf_core_fns =
|
3942 |
|
|
{
|
3943 |
|
|
bfd_target_elf_flavour, /* core_flavour */
|
3944 |
|
|
default_check_format, /* check_format */
|
3945 |
|
|
default_core_sniffer, /* core_sniffer */
|
3946 |
|
|
fetch_core_registers, /* core_read_registers */
|
3947 |
|
|
NULL /* next */
|
3948 |
|
|
};
|
3949 |
|
|
|
3950 |
|
|
extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
|
3951 |
|
|
|
3952 |
|
|
void
|
3953 |
|
|
_initialize_cris_tdep (void)
|
3954 |
|
|
{
|
3955 |
|
|
static struct cmd_list_element *cris_set_cmdlist;
|
3956 |
|
|
static struct cmd_list_element *cris_show_cmdlist;
|
3957 |
|
|
|
3958 |
|
|
struct cmd_list_element *c;
|
3959 |
|
|
|
3960 |
|
|
gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
|
3961 |
|
|
|
3962 |
|
|
/* CRIS-specific user-commands. */
|
3963 |
|
|
add_setshow_uinteger_cmd ("cris-version", class_support,
|
3964 |
|
|
&usr_cmd_cris_version,
|
3965 |
|
|
_("Set the current CRIS version."),
|
3966 |
|
|
_("Show the current CRIS version."),
|
3967 |
|
|
_("\
|
3968 |
|
|
Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
|
3969 |
|
|
Defaults to 10. "),
|
3970 |
|
|
set_cris_version,
|
3971 |
|
|
NULL, /* FIXME: i18n: Current CRIS version is %s. */
|
3972 |
|
|
&setlist, &showlist);
|
3973 |
|
|
|
3974 |
|
|
add_setshow_enum_cmd ("cris-mode", class_support,
|
3975 |
|
|
cris_modes, &usr_cmd_cris_mode,
|
3976 |
|
|
_("Set the current CRIS mode."),
|
3977 |
|
|
_("Show the current CRIS mode."),
|
3978 |
|
|
_("\
|
3979 |
|
|
Set to CRIS_MODE_GURU when debugging in guru mode.\n\
|
3980 |
|
|
Makes GDB use the NRP register instead of the ERP register in certain cases."),
|
3981 |
|
|
set_cris_mode,
|
3982 |
|
|
NULL, /* FIXME: i18n: Current CRIS version is %s. */
|
3983 |
|
|
&setlist, &showlist);
|
3984 |
|
|
|
3985 |
|
|
add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
|
3986 |
|
|
&usr_cmd_cris_dwarf2_cfi,
|
3987 |
|
|
_("Set the usage of Dwarf-2 CFI for CRIS."),
|
3988 |
|
|
_("Show the usage of Dwarf-2 CFI for CRIS."),
|
3989 |
|
|
_("Set this to \"off\" if using gcc-cris < R59."),
|
3990 |
|
|
set_cris_dwarf2_cfi,
|
3991 |
|
|
NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
|
3992 |
|
|
&setlist, &showlist);
|
3993 |
|
|
|
3994 |
|
|
deprecated_add_core_fns (&cris_elf_core_fns);
|
3995 |
|
|
}
|
3996 |
|
|
|
3997 |
|
|
/* Prints out all target specific values. */
|
3998 |
|
|
|
3999 |
|
|
static void
|
4000 |
|
|
cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
|
4001 |
|
|
{
|
4002 |
|
|
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
4003 |
|
|
if (tdep != NULL)
|
4004 |
|
|
{
|
4005 |
|
|
fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
|
4006 |
|
|
tdep->cris_version);
|
4007 |
|
|
fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
|
4008 |
|
|
tdep->cris_mode);
|
4009 |
|
|
fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
|
4010 |
|
|
tdep->cris_dwarf2_cfi);
|
4011 |
|
|
}
|
4012 |
|
|
}
|
4013 |
|
|
|
4014 |
|
|
static void
|
4015 |
|
|
set_cris_version (char *ignore_args, int from_tty,
|
4016 |
|
|
struct cmd_list_element *c)
|
4017 |
|
|
{
|
4018 |
|
|
struct gdbarch_info info;
|
4019 |
|
|
|
4020 |
|
|
usr_cmd_cris_version_valid = 1;
|
4021 |
|
|
|
4022 |
|
|
/* Update the current architecture, if needed. */
|
4023 |
|
|
gdbarch_info_init (&info);
|
4024 |
|
|
if (!gdbarch_update_p (info))
|
4025 |
|
|
internal_error (__FILE__, __LINE__,
|
4026 |
|
|
_("cris_gdbarch_update: failed to update architecture."));
|
4027 |
|
|
}
|
4028 |
|
|
|
4029 |
|
|
static void
|
4030 |
|
|
set_cris_mode (char *ignore_args, int from_tty,
|
4031 |
|
|
struct cmd_list_element *c)
|
4032 |
|
|
{
|
4033 |
|
|
struct gdbarch_info info;
|
4034 |
|
|
|
4035 |
|
|
/* Update the current architecture, if needed. */
|
4036 |
|
|
gdbarch_info_init (&info);
|
4037 |
|
|
if (!gdbarch_update_p (info))
|
4038 |
|
|
internal_error (__FILE__, __LINE__,
|
4039 |
|
|
"cris_gdbarch_update: failed to update architecture.");
|
4040 |
|
|
}
|
4041 |
|
|
|
4042 |
|
|
static void
|
4043 |
|
|
set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
|
4044 |
|
|
struct cmd_list_element *c)
|
4045 |
|
|
{
|
4046 |
|
|
struct gdbarch_info info;
|
4047 |
|
|
|
4048 |
|
|
/* Update the current architecture, if needed. */
|
4049 |
|
|
gdbarch_info_init (&info);
|
4050 |
|
|
if (!gdbarch_update_p (info))
|
4051 |
|
|
internal_error (__FILE__, __LINE__,
|
4052 |
|
|
_("cris_gdbarch_update: failed to update architecture."));
|
4053 |
|
|
}
|
4054 |
|
|
|
4055 |
|
|
static struct gdbarch *
|
4056 |
|
|
cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
4057 |
|
|
{
|
4058 |
|
|
struct gdbarch *gdbarch;
|
4059 |
|
|
struct gdbarch_tdep *tdep;
|
4060 |
|
|
int cris_version;
|
4061 |
|
|
|
4062 |
|
|
if (usr_cmd_cris_version_valid)
|
4063 |
|
|
{
|
4064 |
|
|
/* Trust the user's CRIS version setting. */
|
4065 |
|
|
cris_version = usr_cmd_cris_version;
|
4066 |
|
|
}
|
4067 |
|
|
else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
|
4068 |
|
|
{
|
4069 |
|
|
cris_version = 32;
|
4070 |
|
|
}
|
4071 |
|
|
else
|
4072 |
|
|
{
|
4073 |
|
|
/* Assume it's CRIS version 10. */
|
4074 |
|
|
cris_version = 10;
|
4075 |
|
|
}
|
4076 |
|
|
|
4077 |
|
|
/* Make the current settings visible to the user. */
|
4078 |
|
|
usr_cmd_cris_version = cris_version;
|
4079 |
|
|
|
4080 |
|
|
/* Find a candidate among the list of pre-declared architectures. */
|
4081 |
|
|
for (arches = gdbarch_list_lookup_by_info (arches, &info);
|
4082 |
|
|
arches != NULL;
|
4083 |
|
|
arches = gdbarch_list_lookup_by_info (arches->next, &info))
|
4084 |
|
|
{
|
4085 |
|
|
if ((gdbarch_tdep (arches->gdbarch)->cris_version
|
4086 |
|
|
== usr_cmd_cris_version)
|
4087 |
|
|
&& (gdbarch_tdep (arches->gdbarch)->cris_mode
|
4088 |
|
|
== usr_cmd_cris_mode)
|
4089 |
|
|
&& (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
|
4090 |
|
|
== usr_cmd_cris_dwarf2_cfi))
|
4091 |
|
|
return arches->gdbarch;
|
4092 |
|
|
}
|
4093 |
|
|
|
4094 |
|
|
/* No matching architecture was found. Create a new one. */
|
4095 |
|
|
tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
|
4096 |
|
|
gdbarch = gdbarch_alloc (&info, tdep);
|
4097 |
|
|
|
4098 |
|
|
tdep->cris_version = usr_cmd_cris_version;
|
4099 |
|
|
tdep->cris_mode = usr_cmd_cris_mode;
|
4100 |
|
|
tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
|
4101 |
|
|
|
4102 |
|
|
/* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
|
4103 |
|
|
switch (info.byte_order)
|
4104 |
|
|
{
|
4105 |
|
|
case BFD_ENDIAN_LITTLE:
|
4106 |
|
|
/* Ok. */
|
4107 |
|
|
break;
|
4108 |
|
|
|
4109 |
|
|
case BFD_ENDIAN_BIG:
|
4110 |
|
|
internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
|
4111 |
|
|
break;
|
4112 |
|
|
|
4113 |
|
|
default:
|
4114 |
|
|
internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
|
4115 |
|
|
}
|
4116 |
|
|
|
4117 |
|
|
set_gdbarch_return_value (gdbarch, cris_return_value);
|
4118 |
|
|
|
4119 |
|
|
set_gdbarch_sp_regnum (gdbarch, 14);
|
4120 |
|
|
|
4121 |
|
|
/* Length of ordinary registers used in push_word and a few other
|
4122 |
|
|
places. register_size() is the real way to know how big a
|
4123 |
|
|
register is. */
|
4124 |
|
|
|
4125 |
|
|
set_gdbarch_double_bit (gdbarch, 64);
|
4126 |
|
|
/* The default definition of a long double is 2 * gdbarch_double_bit,
|
4127 |
|
|
which means we have to set this explicitly. */
|
4128 |
|
|
set_gdbarch_long_double_bit (gdbarch, 64);
|
4129 |
|
|
|
4130 |
|
|
/* The total amount of space needed to store (in an array called registers)
|
4131 |
|
|
GDB's copy of the machine's register state. Note: We can not use
|
4132 |
|
|
cris_register_size at this point, since it relies on gdbarch
|
4133 |
|
|
being set. */
|
4134 |
|
|
switch (tdep->cris_version)
|
4135 |
|
|
{
|
4136 |
|
|
case 0:
|
4137 |
|
|
case 1:
|
4138 |
|
|
case 2:
|
4139 |
|
|
case 3:
|
4140 |
|
|
case 8:
|
4141 |
|
|
case 9:
|
4142 |
|
|
/* Old versions; not supported. */
|
4143 |
|
|
internal_error (__FILE__, __LINE__,
|
4144 |
|
|
_("cris_gdbarch_init: unsupported CRIS version"));
|
4145 |
|
|
break;
|
4146 |
|
|
|
4147 |
|
|
case 10:
|
4148 |
|
|
case 11:
|
4149 |
|
|
/* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
|
4150 |
|
|
P7 (32 bits), and P15 (32 bits) have been implemented. */
|
4151 |
|
|
set_gdbarch_pc_regnum (gdbarch, 15);
|
4152 |
|
|
set_gdbarch_register_type (gdbarch, cris_register_type);
|
4153 |
|
|
/* There are 32 registers (some of which may not be implemented). */
|
4154 |
|
|
set_gdbarch_num_regs (gdbarch, 32);
|
4155 |
|
|
set_gdbarch_register_name (gdbarch, cris_register_name);
|
4156 |
|
|
set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
|
4157 |
|
|
set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
|
4158 |
|
|
|
4159 |
|
|
set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
|
4160 |
|
|
break;
|
4161 |
|
|
|
4162 |
|
|
case 32:
|
4163 |
|
|
/* CRIS v32. General registers R0 - R15 (32 bits), special registers
|
4164 |
|
|
P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
|
4165 |
|
|
and pseudo-register PC (32 bits). */
|
4166 |
|
|
set_gdbarch_pc_regnum (gdbarch, 32);
|
4167 |
|
|
set_gdbarch_register_type (gdbarch, crisv32_register_type);
|
4168 |
|
|
/* 32 registers + pseudo-register PC + 16 support registers. */
|
4169 |
|
|
set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
|
4170 |
|
|
set_gdbarch_register_name (gdbarch, crisv32_register_name);
|
4171 |
|
|
|
4172 |
|
|
set_gdbarch_cannot_store_register
|
4173 |
|
|
(gdbarch, crisv32_cannot_store_register);
|
4174 |
|
|
set_gdbarch_cannot_fetch_register
|
4175 |
|
|
(gdbarch, crisv32_cannot_fetch_register);
|
4176 |
|
|
|
4177 |
|
|
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
|
4178 |
|
|
|
4179 |
|
|
set_gdbarch_single_step_through_delay
|
4180 |
|
|
(gdbarch, crisv32_single_step_through_delay);
|
4181 |
|
|
|
4182 |
|
|
break;
|
4183 |
|
|
|
4184 |
|
|
default:
|
4185 |
|
|
internal_error (__FILE__, __LINE__,
|
4186 |
|
|
_("cris_gdbarch_init: unknown CRIS version"));
|
4187 |
|
|
}
|
4188 |
|
|
|
4189 |
|
|
/* Dummy frame functions (shared between CRISv10 and CRISv32 since they
|
4190 |
|
|
have the same ABI). */
|
4191 |
|
|
set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
|
4192 |
|
|
set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
|
4193 |
|
|
set_gdbarch_frame_align (gdbarch, cris_frame_align);
|
4194 |
|
|
set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
|
4195 |
|
|
|
4196 |
|
|
/* The stack grows downward. */
|
4197 |
|
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
4198 |
|
|
|
4199 |
|
|
set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
|
4200 |
|
|
|
4201 |
|
|
set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
|
4202 |
|
|
set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
|
4203 |
|
|
set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
|
4204 |
|
|
|
4205 |
|
|
if (tdep->cris_dwarf2_cfi == 1)
|
4206 |
|
|
{
|
4207 |
|
|
/* Hook in the Dwarf-2 frame sniffer. */
|
4208 |
|
|
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
|
4209 |
|
|
dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
|
4210 |
|
|
dwarf2_append_unwinders (gdbarch);
|
4211 |
|
|
}
|
4212 |
|
|
|
4213 |
|
|
if (tdep->cris_mode != cris_mode_guru)
|
4214 |
|
|
{
|
4215 |
|
|
frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
|
4216 |
|
|
}
|
4217 |
|
|
|
4218 |
|
|
frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
|
4219 |
|
|
frame_base_set_default (gdbarch, &cris_frame_base);
|
4220 |
|
|
|
4221 |
|
|
set_solib_svr4_fetch_link_map_offsets
|
4222 |
|
|
(gdbarch, svr4_ilp32_fetch_link_map_offsets);
|
4223 |
|
|
|
4224 |
|
|
/* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
|
4225 |
|
|
disassembler, even when there is no BFD. Does something like
|
4226 |
|
|
"gdb; target remote; disassmeble *0x123" work? */
|
4227 |
|
|
set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);
|
4228 |
|
|
|
4229 |
|
|
return gdbarch;
|
4230 |
|
|
}
|