OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [gdb/] [features/] [arm-with-iwmmxt.c] - Blame information for rev 832

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* THIS FILE IS GENERATED.  Original: arm-with-iwmmxt.xml */
2
 
3
#include "defs.h"
4
#include "target-descriptions.h"
5
 
6
struct target_desc *tdesc_arm_with_iwmmxt;
7
static void
8
initialize_tdesc_arm_with_iwmmxt (void)
9
{
10
  struct target_desc *result = allocate_target_description ();
11
  struct tdesc_feature *feature;
12
  struct tdesc_type *field_type, *type;
13
 
14
  set_tdesc_architecture (result, bfd_scan_arch ("iwmmxt"));
15
 
16
  feature = tdesc_create_feature (result, "org.gnu.gdb.arm.core");
17
  tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
18
  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
19
  tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
20
  tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
21
  tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
22
  tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int");
23
  tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int");
24
  tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int");
25
  tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int");
26
  tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int");
27
  tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int");
28
  tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int");
29
  tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int");
30
  tdesc_create_reg (feature, "sp", 13, 1, NULL, 32, "data_ptr");
31
  tdesc_create_reg (feature, "lr", 14, 1, NULL, 32, "int");
32
  tdesc_create_reg (feature, "pc", 15, 1, NULL, 32, "code_ptr");
33
  tdesc_create_reg (feature, "cpsr", 25, 1, NULL, 32, "int");
34
 
35
  feature = tdesc_create_feature (result, "org.gnu.gdb.xscale.iwmmxt");
36
  field_type = tdesc_named_type (feature, "uint8");
37
  tdesc_create_vector (feature, "iwmmxt_v8u8", field_type, 8);
38
 
39
  field_type = tdesc_named_type (feature, "uint16");
40
  tdesc_create_vector (feature, "iwmmxt_v4u16", field_type, 4);
41
 
42
  field_type = tdesc_named_type (feature, "uint32");
43
  tdesc_create_vector (feature, "iwmmxt_v2u32", field_type, 2);
44
 
45
  type = tdesc_create_union (feature, "iwmmxt_vec64i");
46
  field_type = tdesc_named_type (feature, "iwmmxt_v8u8");
47
  tdesc_add_field (type, "u8", field_type);
48
  field_type = tdesc_named_type (feature, "iwmmxt_v4u16");
49
  tdesc_add_field (type, "u16", field_type);
50
  field_type = tdesc_named_type (feature, "iwmmxt_v2u32");
51
  tdesc_add_field (type, "u32", field_type);
52
  field_type = tdesc_named_type (feature, "uint64");
53
  tdesc_add_field (type, "u64", field_type);
54
 
55
  tdesc_create_reg (feature, "wR0", 26, 1, NULL, 64, "iwmmxt_vec64i");
56
  tdesc_create_reg (feature, "wR1", 27, 1, NULL, 64, "iwmmxt_vec64i");
57
  tdesc_create_reg (feature, "wR2", 28, 1, NULL, 64, "iwmmxt_vec64i");
58
  tdesc_create_reg (feature, "wR3", 29, 1, NULL, 64, "iwmmxt_vec64i");
59
  tdesc_create_reg (feature, "wR4", 30, 1, NULL, 64, "iwmmxt_vec64i");
60
  tdesc_create_reg (feature, "wR5", 31, 1, NULL, 64, "iwmmxt_vec64i");
61
  tdesc_create_reg (feature, "wR6", 32, 1, NULL, 64, "iwmmxt_vec64i");
62
  tdesc_create_reg (feature, "wR7", 33, 1, NULL, 64, "iwmmxt_vec64i");
63
  tdesc_create_reg (feature, "wR8", 34, 1, NULL, 64, "iwmmxt_vec64i");
64
  tdesc_create_reg (feature, "wR9", 35, 1, NULL, 64, "iwmmxt_vec64i");
65
  tdesc_create_reg (feature, "wR10", 36, 1, NULL, 64, "iwmmxt_vec64i");
66
  tdesc_create_reg (feature, "wR11", 37, 1, NULL, 64, "iwmmxt_vec64i");
67
  tdesc_create_reg (feature, "wR12", 38, 1, NULL, 64, "iwmmxt_vec64i");
68
  tdesc_create_reg (feature, "wR13", 39, 1, NULL, 64, "iwmmxt_vec64i");
69
  tdesc_create_reg (feature, "wR14", 40, 1, NULL, 64, "iwmmxt_vec64i");
70
  tdesc_create_reg (feature, "wR15", 41, 1, NULL, 64, "iwmmxt_vec64i");
71
  tdesc_create_reg (feature, "wCSSF", 42, 1, "vector", 32, "int");
72
  tdesc_create_reg (feature, "wCASF", 43, 1, "vector", 32, "int");
73
  tdesc_create_reg (feature, "wCGR0", 44, 1, "vector", 32, "int");
74
  tdesc_create_reg (feature, "wCGR1", 45, 1, "vector", 32, "int");
75
  tdesc_create_reg (feature, "wCGR2", 46, 1, "vector", 32, "int");
76
  tdesc_create_reg (feature, "wCGR3", 47, 1, "vector", 32, "int");
77
 
78
  tdesc_arm_with_iwmmxt = result;
79
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.