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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [gdb/] [i386-nat.c] - Blame information for rev 853

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1 227 jeremybenn
/* Native-dependent code for the i386.
2
 
3
   Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
#include "i386-nat.h"
22
#include "defs.h"
23
#include "breakpoint.h"
24
#include "command.h"
25
#include "gdbcmd.h"
26
#include "target.h"
27
#include "gdb_assert.h"
28
 
29
/* Support for hardware watchpoints and breakpoints using the i386
30
   debug registers.
31
 
32
   This provides several functions for inserting and removing
33
   hardware-assisted breakpoints and watchpoints, testing if one or
34
   more of the watchpoints triggered and at what address, checking
35
   whether a given region can be watched, etc.
36
 
37
   The functions below implement debug registers sharing by reference
38
   counts, and allow to watch regions up to 16 bytes long.  */
39
 
40
struct i386_dr_low_type i386_dr_low;
41
 
42
 
43
/* Support for 8-byte wide hw watchpoints.  */
44
#define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8)
45
 
46
/* Debug registers' indices.  */
47
#define DR_NADDR        4       /* The number of debug address registers.  */
48
#define DR_STATUS       6       /* Index of debug status register (DR6).  */
49
#define DR_CONTROL      7       /* Index of debug control register (DR7). */
50
 
51
/* DR7 Debug Control register fields.  */
52
 
53
/* How many bits to skip in DR7 to get to R/W and LEN fields.  */
54
#define DR_CONTROL_SHIFT        16
55
/* How many bits in DR7 per R/W and LEN field for each watchpoint.  */
56
#define DR_CONTROL_SIZE         4
57
 
58
/* Watchpoint/breakpoint read/write fields in DR7.  */
59
#define DR_RW_EXECUTE   (0x0)   /* Break on instruction execution.  */
60
#define DR_RW_WRITE     (0x1)   /* Break on data writes.  */
61
#define DR_RW_READ      (0x3)   /* Break on data reads or writes.  */
62
 
63
/* This is here for completeness.  No platform supports this
64
   functionality yet (as of March 2001).  Note that the DE flag in the
65
   CR4 register needs to be set to support this.  */
66
#ifndef DR_RW_IORW
67
#define DR_RW_IORW      (0x2)   /* Break on I/O reads or writes.  */
68
#endif
69
 
70
/* Watchpoint/breakpoint length fields in DR7.  The 2-bit left shift
71
   is so we could OR this with the read/write field defined above.  */
72
#define DR_LEN_1        (0x0 << 2) /* 1-byte region watch or breakpoint.  */
73
#define DR_LEN_2        (0x1 << 2) /* 2-byte region watch.  */
74
#define DR_LEN_4        (0x3 << 2) /* 4-byte region watch.  */
75
#define DR_LEN_8        (0x2 << 2) /* 8-byte region watch (AMD64).  */
76
 
77
/* Local and Global Enable flags in DR7.
78
 
79
   When the Local Enable flag is set, the breakpoint/watchpoint is
80
   enabled only for the current task; the processor automatically
81
   clears this flag on every task switch.  When the Global Enable flag
82
   is set, the breakpoint/watchpoint is enabled for all tasks; the
83
   processor never clears this flag.
84
 
85
   Currently, all watchpoint are locally enabled.  If you need to
86
   enable them globally, read the comment which pertains to this in
87
   i386_insert_aligned_watchpoint below.  */
88
#define DR_LOCAL_ENABLE_SHIFT   0 /* Extra shift to the local enable bit.  */
89
#define DR_GLOBAL_ENABLE_SHIFT  1 /* Extra shift to the global enable bit.  */
90
#define DR_ENABLE_SIZE          2 /* Two enable bits per debug register.  */
91
 
92
/* Local and global exact breakpoint enable flags (a.k.a. slowdown
93
   flags).  These are only required on i386, to allow detection of the
94
   exact instruction which caused a watchpoint to break; i486 and
95
   later processors do that automatically.  We set these flags for
96
   backwards compatibility.  */
97
#define DR_LOCAL_SLOWDOWN       (0x100)
98
#define DR_GLOBAL_SLOWDOWN      (0x200)
99
 
100
/* Fields reserved by Intel.  This includes the GD (General Detect
101
   Enable) flag, which causes a debug exception to be generated when a
102
   MOV instruction accesses one of the debug registers.
103
 
104
   FIXME: My Intel manual says we should use 0xF800, not 0xFC00.  */
105
#define DR_CONTROL_RESERVED     (0xFC00)
106
 
107
/* Auxiliary helper macros.  */
108
 
109
/* A value that masks all fields in DR7 that are reserved by Intel.  */
110
#define I386_DR_CONTROL_MASK    (~DR_CONTROL_RESERVED)
111
 
112
/* The I'th debug register is vacant if its Local and Global Enable
113
   bits are reset in the Debug Control register.  */
114
#define I386_DR_VACANT(i) \
115
  ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
116
 
117
/* Locally enable the break/watchpoint in the I'th debug register.  */
118
#define I386_DR_LOCAL_ENABLE(i) \
119
  dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
120
 
121
/* Globally enable the break/watchpoint in the I'th debug register.  */
122
#define I386_DR_GLOBAL_ENABLE(i) \
123
  dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
124
 
125
/* Disable the break/watchpoint in the I'th debug register.  */
126
#define I386_DR_DISABLE(i) \
127
  dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
128
 
129
/* Set in DR7 the RW and LEN fields for the I'th debug register.  */
130
#define I386_DR_SET_RW_LEN(i,rwlen) \
131
  do { \
132
    dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i)));   \
133
    dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
134
  } while (0)
135
 
136
/* Get from DR7 the RW and LEN fields for the I'th debug register.  */
137
#define I386_DR_GET_RW_LEN(i) \
138
  ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
139
 
140
/* Mask that this I'th watchpoint has triggered.  */
141
#define I386_DR_WATCH_MASK(i)   (1 << (i))
142
 
143
/* Did the watchpoint whose address is in the I'th register break?  */
144
#define I386_DR_WATCH_HIT(i)    (dr_status_mirror & I386_DR_WATCH_MASK (i))
145
 
146
/* A macro to loop over all debug registers.  */
147
#define ALL_DEBUG_REGISTERS(i)  for (i = 0; i < DR_NADDR; i++)
148
 
149
/* Mirror the inferior's DRi registers.  We keep the status and
150
   control registers separated because they don't hold addresses.  */
151
static CORE_ADDR dr_mirror[DR_NADDR];
152
static unsigned long dr_status_mirror, dr_control_mirror;
153
 
154
/* Reference counts for each debug register.  */
155
static int dr_ref_count[DR_NADDR];
156
 
157
/* Whether or not to print the mirrored debug registers.  */
158
static int maint_show_dr;
159
 
160
/* Types of operations supported by i386_handle_nonaligned_watchpoint.  */
161
typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
162
 
163
/* Internal functions.  */
164
 
165
/* Return the value of a 4-bit field for DR7 suitable for watching a
166
   region of LEN bytes for accesses of type TYPE.  LEN is assumed to
167
   have the value of 1, 2, or 4.  */
168
static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type);
169
 
170
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
171
   according to the length of the region to watch.  LEN_RW_BITS is the
172
   value of the bit-field from DR7 which describes the length and
173
   access type of the region to be watched by this watchpoint.  Return
174
 
175
static int i386_insert_aligned_watchpoint (CORE_ADDR addr,
176
                                           unsigned len_rw_bits);
177
 
178
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
179
   according to the length of the region to watch.  LEN_RW_BITS is the
180
   value of the bits from DR7 which describes the length and access
181
   type of the region watched by this watchpoint.  Return 0 on
182
   success, -1 on failure.  */
183
static int i386_remove_aligned_watchpoint (CORE_ADDR addr,
184
                                           unsigned len_rw_bits);
185
 
186
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
187
   number of debug registers required to watch a region at address
188
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
189
   successful insertion or removal, a positive number when queried
190
   about the number of registers, or -1 on failure.  If WHAT is not a
191
   valid value, bombs through internal_error.  */
192
static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what,
193
                                              CORE_ADDR addr, int len,
194
                                              enum target_hw_bp_type type);
195
 
196
/* Implementation.  */
197
 
198
/* Clear the reference counts and forget everything we knew about the
199
   debug registers.  */
200
 
201
void
202
i386_cleanup_dregs (void)
203
{
204
  int i;
205
 
206
  ALL_DEBUG_REGISTERS(i)
207
    {
208
      dr_mirror[i] = 0;
209
      dr_ref_count[i] = 0;
210
    }
211
  dr_control_mirror = 0;
212
  dr_status_mirror  = 0;
213
}
214
 
215
/* Print the values of the mirrored debug registers.  This is called
216
   when maint_show_dr is non-zero.  To set that up, type "maint
217
   show-debug-regs" at GDB's prompt.  */
218
 
219
static void
220
i386_show_dr (const char *func, CORE_ADDR addr,
221
              int len, enum target_hw_bp_type type)
222
{
223
  int addr_size = gdbarch_addr_bit (target_gdbarch) / 8;
224
  int i;
225
 
226
  puts_unfiltered (func);
227
  if (addr || len)
228
    printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
229
                       /* This code is for ia32, so casting CORE_ADDR
230
                          to unsigned long should be okay.  */
231
                       (unsigned long)addr, len,
232
                       type == hw_write ? "data-write"
233
                       : (type == hw_read ? "data-read"
234
                          : (type == hw_access ? "data-read/write"
235
                             : (type == hw_execute ? "instruction-execute"
236
                                /* FIXME: if/when I/O read/write
237
                                   watchpoints are supported, add them
238
                                   here.  */
239
                                : "??unknown??"))));
240
  puts_unfiltered (":\n");
241
  printf_unfiltered ("\tCONTROL (DR7): %s          STATUS (DR6): %s\n",
242
                     phex (dr_control_mirror, 8), phex (dr_status_mirror, 8));
243
  ALL_DEBUG_REGISTERS(i)
244
    {
245
      printf_unfiltered ("\
246
\tDR%d: addr=0x%s, ref.count=%d  DR%d: addr=0x%s, ref.count=%d\n",
247
                 i, phex (dr_mirror[i], addr_size), dr_ref_count[i],
248
                 i+1, phex (dr_mirror[i+1], addr_size), dr_ref_count[i+1]);
249
      i++;
250
    }
251
}
252
 
253
/* Return the value of a 4-bit field for DR7 suitable for watching a
254
   region of LEN bytes for accesses of type TYPE.  LEN is assumed to
255
   have the value of 1, 2, or 4.  */
256
 
257
static unsigned
258
i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
259
{
260
  unsigned rw;
261
 
262
  switch (type)
263
    {
264
      case hw_execute:
265
        rw = DR_RW_EXECUTE;
266
        break;
267
      case hw_write:
268
        rw = DR_RW_WRITE;
269
        break;
270
      case hw_read:
271
        /* The i386 doesn't support data-read watchpoints.  */
272
      case hw_access:
273
        rw = DR_RW_READ;
274
        break;
275
#if 0
276
        /* Not yet supported.  */
277
      case hw_io_access:
278
        rw = DR_RW_IORW;
279
        break;
280
#endif
281
      default:
282
        internal_error (__FILE__, __LINE__, _("\
283
Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
284
                        (int) type);
285
    }
286
 
287
  switch (len)
288
    {
289
      case 1:
290
        return (DR_LEN_1 | rw);
291
      case 2:
292
        return (DR_LEN_2 | rw);
293
      case 4:
294
        return (DR_LEN_4 | rw);
295
      case 8:
296
        if (TARGET_HAS_DR_LEN_8)
297
          return (DR_LEN_8 | rw);
298
      default:
299
        internal_error (__FILE__, __LINE__, _("\
300
Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len);
301
    }
302
}
303
 
304
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
305
   according to the length of the region to watch.  LEN_RW_BITS is the
306
   value of the bits from DR7 which describes the length and access
307
   type of the region to be watched by this watchpoint.  Return 0 on
308
   success, -1 on failure.  */
309
 
310
static int
311
i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
312
{
313
  int i;
314
 
315
  if (!i386_dr_low.set_addr || !i386_dr_low.set_control)
316
    return -1;
317
 
318
  /* First, look for an occupied debug register with the same address
319
     and the same RW and LEN definitions.  If we find one, we can
320
     reuse it for this watchpoint as well (and save a register).  */
321
  ALL_DEBUG_REGISTERS(i)
322
    {
323
      if (!I386_DR_VACANT (i)
324
          && dr_mirror[i] == addr
325
          && I386_DR_GET_RW_LEN (i) == len_rw_bits)
326
        {
327
          dr_ref_count[i]++;
328
          return 0;
329
        }
330
    }
331
 
332
  /* Next, look for a vacant debug register.  */
333
  ALL_DEBUG_REGISTERS(i)
334
    {
335
      if (I386_DR_VACANT (i))
336
        break;
337
    }
338
 
339
  /* No more debug registers!  */
340
  if (i >= DR_NADDR)
341
    return -1;
342
 
343
  /* Now set up the register I to watch our region.  */
344
 
345
  /* Record the info in our local mirrored array.  */
346
  dr_mirror[i] = addr;
347
  dr_ref_count[i] = 1;
348
  I386_DR_SET_RW_LEN (i, len_rw_bits);
349
  /* Note: we only enable the watchpoint locally, i.e. in the current
350
     task.  Currently, no i386 target allows or supports global
351
     watchpoints; however, if any target would want that in the
352
     future, GDB should probably provide a command to control whether
353
     to enable watchpoints globally or locally, and the code below
354
     should use global or local enable and slow-down flags as
355
     appropriate.  */
356
  I386_DR_LOCAL_ENABLE (i);
357
  dr_control_mirror |= DR_LOCAL_SLOWDOWN;
358
  dr_control_mirror &= I386_DR_CONTROL_MASK;
359
 
360
  /* Finally, actually pass the info to the inferior.  */
361
  i386_dr_low.set_addr (i, addr);
362
  i386_dr_low.set_control (dr_control_mirror);
363
 
364
  /* Only a sanity check for leftover bits (set possibly only by inferior).  */
365
  if (i386_dr_low.unset_status)
366
    i386_dr_low.unset_status (I386_DR_WATCH_MASK (i));
367
 
368
  return 0;
369
}
370
 
371
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
372
   according to the length of the region to watch.  LEN_RW_BITS is the
373
   value of the bits from DR7 which describes the length and access
374
   type of the region watched by this watchpoint.  Return 0 on
375
   success, -1 on failure.  */
376
 
377
static int
378
i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
379
{
380
  int i, retval = -1;
381
 
382
  ALL_DEBUG_REGISTERS(i)
383
    {
384
      if (!I386_DR_VACANT (i)
385
          && dr_mirror[i] == addr
386
          && I386_DR_GET_RW_LEN (i) == len_rw_bits)
387
        {
388
          if (--dr_ref_count[i] == 0) /* no longer in use? */
389
            {
390
              /* Reset our mirror.  */
391
              dr_mirror[i] = 0;
392
              I386_DR_DISABLE (i);
393
              /* Reset it in the inferior.  */
394
              i386_dr_low.set_control (dr_control_mirror);
395
              if (i386_dr_low.reset_addr)
396
                i386_dr_low.reset_addr (i);
397
            }
398
          retval = 0;
399
        }
400
    }
401
 
402
  return retval;
403
}
404
 
405
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
406
   number of debug registers required to watch a region at address
407
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
408
   successful insertion or removal, a positive number when queried
409
   about the number of registers, or -1 on failure.  If WHAT is not a
410
   valid value, bombs through internal_error.  */
411
 
412
static int
413
i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len,
414
                                   enum target_hw_bp_type type)
415
{
416
  int retval = 0, status = 0;
417
  int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
418
 
419
  static int size_try_array[8][8] =
420
  {
421
    {1, 1, 1, 1, 1, 1, 1, 1},   /* Trying size one.  */
422
    {2, 1, 2, 1, 2, 1, 2, 1},   /* Trying size two.  */
423
    {2, 1, 2, 1, 2, 1, 2, 1},   /* Trying size three.  */
424
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size four.  */
425
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size five.  */
426
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size six.  */
427
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size seven.  */
428
    {8, 1, 2, 1, 4, 1, 2, 1},   /* Trying size eight.  */
429
  };
430
 
431
  while (len > 0)
432
    {
433
      int align = addr % max_wp_len;
434
      /* Four (eight on AMD64) is the maximum length a debug register
435
         can watch.  */
436
      int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
437
      int size = size_try_array[try][align];
438
 
439
      if (what == WP_COUNT)
440
        {
441
          /* size_try_array[] is defined such that each iteration
442
             through the loop is guaranteed to produce an address and a
443
             size that can be watched with a single debug register.
444
             Thus, for counting the registers required to watch a
445
             region, we simply need to increment the count on each
446
             iteration.  */
447
          retval++;
448
        }
449
      else
450
        {
451
          unsigned len_rw = i386_length_and_rw_bits (size, type);
452
 
453
          if (what == WP_INSERT)
454
            status = i386_insert_aligned_watchpoint (addr, len_rw);
455
          else if (what == WP_REMOVE)
456
            status = i386_remove_aligned_watchpoint (addr, len_rw);
457
          else
458
            internal_error (__FILE__, __LINE__, _("\
459
Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
460
                            (int)what);
461
          /* We keep the loop going even after a failure, because some
462
             of the other aligned watchpoints might still succeed
463
             (e.g. if they watch addresses that are already watched,
464
             in which case we just increment the reference counts of
465
             occupied debug registers).  If we break out of the loop
466
             too early, we could cause those addresses watched by
467
             other watchpoints to be disabled when breakpoint.c reacts
468
             to our failure to insert this watchpoint and tries to
469
             remove it.  */
470
          if (status)
471
            retval = status;
472
        }
473
 
474
      addr += size;
475
      len -= size;
476
    }
477
 
478
  return retval;
479
}
480
 
481
/* Insert a watchpoint to watch a memory region which starts at
482
   address ADDR and whose length is LEN bytes.  Watch memory accesses
483
   of the type TYPE.  Return 0 on success, -1 on failure.  */
484
 
485
static int
486
i386_insert_watchpoint (CORE_ADDR addr, int len, int type)
487
{
488
  int retval;
489
 
490
  if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
491
      || addr % len != 0)
492
    retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type);
493
  else
494
    {
495
      unsigned len_rw = i386_length_and_rw_bits (len, type);
496
 
497
      retval = i386_insert_aligned_watchpoint (addr, len_rw);
498
    }
499
 
500
  if (maint_show_dr)
501
    i386_show_dr ("insert_watchpoint", addr, len, type);
502
 
503
  return retval;
504
}
505
 
506
/* Remove a watchpoint that watched the memory region which starts at
507
   address ADDR, whose length is LEN bytes, and for accesses of the
508
   type TYPE.  Return 0 on success, -1 on failure.  */
509
static int
510
i386_remove_watchpoint (CORE_ADDR addr, int len, int type)
511
{
512
  int retval;
513
 
514
  if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
515
      || addr % len != 0)
516
    retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type);
517
  else
518
    {
519
      unsigned len_rw = i386_length_and_rw_bits (len, type);
520
 
521
      retval = i386_remove_aligned_watchpoint (addr, len_rw);
522
    }
523
 
524
  if (maint_show_dr)
525
    i386_show_dr ("remove_watchpoint", addr, len, type);
526
 
527
  return retval;
528
}
529
 
530
/* Return non-zero if we can watch a memory region that starts at
531
   address ADDR and whose length is LEN bytes.  */
532
 
533
static int
534
i386_region_ok_for_watchpoint (CORE_ADDR addr, int len)
535
{
536
  int nregs;
537
 
538
  /* Compute how many aligned watchpoints we would need to cover this
539
     region.  */
540
  nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write);
541
  return nregs <= DR_NADDR ? 1 : 0;
542
}
543
 
544
/* If the inferior has some watchpoint that triggered, set the
545
   address associated with that watchpoint and return non-zero.
546
   Otherwise, return zero.  */
547
 
548
static int
549
i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
550
{
551
  CORE_ADDR addr = 0;
552
  int i;
553
  int rc = 0;
554
 
555
  dr_status_mirror = i386_dr_low.get_status ();
556
 
557
  ALL_DEBUG_REGISTERS(i)
558
    {
559
      if (I386_DR_WATCH_HIT (i)
560
          /* This second condition makes sure DRi is set up for a data
561
             watchpoint, not a hardware breakpoint.  The reason is
562
             that GDB doesn't call the target_stopped_data_address
563
             method except for data watchpoints.  In other words, I'm
564
             being paranoiac.  */
565
          && I386_DR_GET_RW_LEN (i) != 0
566
          /* This third condition makes sure DRi is not vacant, this
567
             avoids false positives in windows-nat.c.  */
568
          && !I386_DR_VACANT (i))
569
        {
570
          addr = dr_mirror[i];
571
          rc = 1;
572
          if (maint_show_dr)
573
            i386_show_dr ("watchpoint_hit", addr, -1, hw_write);
574
        }
575
    }
576
  if (maint_show_dr && addr == 0)
577
    i386_show_dr ("stopped_data_addr", 0, 0, hw_write);
578
 
579
  if (rc)
580
    *addr_p = addr;
581
  return rc;
582
}
583
 
584
static int
585
i386_stopped_by_watchpoint (void)
586
{
587
  CORE_ADDR addr = 0;
588
  return i386_stopped_data_address (&current_target, &addr);
589
}
590
 
591
/* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
592
   Return 0 on success, EBUSY on failure.  */
593
static int
594
i386_insert_hw_breakpoint (struct gdbarch *gdbarch,
595
                           struct bp_target_info *bp_tgt)
596
{
597
  unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
598
  CORE_ADDR addr = bp_tgt->placed_address;
599
  int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0;
600
 
601
  if (maint_show_dr)
602
    i386_show_dr ("insert_hwbp", addr, 1, hw_execute);
603
 
604
  return retval;
605
}
606
 
607
/* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
608
   Return 0 on success, -1 on failure.  */
609
 
610
static int
611
i386_remove_hw_breakpoint (struct gdbarch *gdbarch,
612
                           struct bp_target_info *bp_tgt)
613
{
614
  unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
615
  CORE_ADDR addr = bp_tgt->placed_address;
616
  int retval = i386_remove_aligned_watchpoint (addr, len_rw);
617
 
618
  if (maint_show_dr)
619
    i386_show_dr ("remove_hwbp", addr, 1, hw_execute);
620
 
621
  return retval;
622
}
623
 
624
/* Returns the number of hardware watchpoints of type TYPE that we can
625
   set.  Value is positive if we can set CNT watchpoints, zero if
626
   setting watchpoints of type TYPE is not supported, and negative if
627
   CNT is more than the maximum number of watchpoints of type TYPE
628
   that we can support.  TYPE is one of bp_hardware_watchpoint,
629
   bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
630
   CNT is the number of such watchpoints used so far (including this
631
   one).  OTHERTYPE is non-zero if other types of watchpoints are
632
   currently enabled.
633
 
634
   We always return 1 here because we don't have enough information
635
   about possible overlap of addresses that they want to watch.  As an
636
   extreme example, consider the case where all the watchpoints watch
637
   the same address and the same region length: then we can handle a
638
   virtually unlimited number of watchpoints, due to debug register
639
   sharing implemented via reference counts in i386-nat.c.  */
640
 
641
static int
642
i386_can_use_hw_breakpoint (int type, int cnt, int othertype)
643
{
644
  return 1;
645
}
646
 
647
static void
648
add_show_debug_regs_command (void)
649
{
650
  /* A maintenance command to enable printing the internal DRi mirror
651
     variables.  */
652
  add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
653
                           &maint_show_dr, _("\
654
Set whether to show variables that mirror the x86 debug registers."), _("\
655
Show whether to show variables that mirror the x86 debug registers."), _("\
656
Use \"on\" to enable, \"off\" to disable.\n\
657
If enabled, the debug registers values are shown when GDB inserts\n\
658
or removes a hardware breakpoint or watchpoint, and when the inferior\n\
659
triggers a breakpoint or watchpoint."),
660
                           NULL,
661
                           NULL,
662
                           &maintenance_set_cmdlist,
663
                           &maintenance_show_cmdlist);
664
}
665
 
666
/* There are only two global functions left.  */
667
 
668
void
669
i386_use_watchpoints (struct target_ops *t)
670
{
671
  /* After a watchpoint trap, the PC points to the instruction after the
672
     one that caused the trap.  Therefore we don't need to step over it.
673
     But we do need to reset the status register to avoid another trap.  */
674
  t->to_have_continuable_watchpoint = 1;
675
 
676
  t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint;
677
  t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint;
678
  t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint;
679
  t->to_stopped_data_address = i386_stopped_data_address;
680
  t->to_insert_watchpoint = i386_insert_watchpoint;
681
  t->to_remove_watchpoint = i386_remove_watchpoint;
682
  t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint;
683
  t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint;
684
}
685
 
686
void
687
i386_set_debug_register_length (int len)
688
{
689
  /* This function should be called only once for each native target.  */
690
  gdb_assert (i386_dr_low.debug_register_length == 0);
691
  gdb_assert (len == 4 || len == 8);
692
  i386_dr_low.debug_register_length = len;
693
  add_show_debug_regs_command ();
694
}

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