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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [gdb/] [mips-tdep.c] - Blame information for rev 842

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1 227 jeremybenn
/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2
 
3
   Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4
   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5
   2010 Free Software Foundation, Inc.
6
 
7
   Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8
   and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9
 
10
   This file is part of GDB.
11
 
12
   This program is free software; you can redistribute it and/or modify
13
   it under the terms of the GNU General Public License as published by
14
   the Free Software Foundation; either version 3 of the License, or
15
   (at your option) any later version.
16
 
17
   This program is distributed in the hope that it will be useful,
18
   but WITHOUT ANY WARRANTY; without even the implied warranty of
19
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20
   GNU General Public License for more details.
21
 
22
   You should have received a copy of the GNU General Public License
23
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
24
 
25
#include "defs.h"
26
#include "gdb_string.h"
27
#include "gdb_assert.h"
28
#include "frame.h"
29
#include "inferior.h"
30
#include "symtab.h"
31
#include "value.h"
32
#include "gdbcmd.h"
33
#include "language.h"
34
#include "gdbcore.h"
35
#include "symfile.h"
36
#include "objfiles.h"
37
#include "gdbtypes.h"
38
#include "target.h"
39
#include "arch-utils.h"
40
#include "regcache.h"
41
#include "osabi.h"
42
#include "mips-tdep.h"
43
#include "block.h"
44
#include "reggroups.h"
45
#include "opcode/mips.h"
46
#include "elf/mips.h"
47
#include "elf-bfd.h"
48
#include "symcat.h"
49
#include "sim-regno.h"
50
#include "dis-asm.h"
51
#include "frame-unwind.h"
52
#include "frame-base.h"
53
#include "trad-frame.h"
54
#include "infcall.h"
55
#include "floatformat.h"
56
#include "remote.h"
57
#include "target-descriptions.h"
58
#include "dwarf2-frame.h"
59
#include "user-regs.h"
60
#include "valprint.h"
61
 
62
static const struct objfile_data *mips_pdr_data;
63
 
64
static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65
 
66
/* A useful bit in the CP0 status register (MIPS_PS_REGNUM).  */
67
/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip.  */
68
#define ST0_FR (1 << 26)
69
 
70
/* The sizes of floating point registers.  */
71
 
72
enum
73
{
74
  MIPS_FPU_SINGLE_REGSIZE = 4,
75
  MIPS_FPU_DOUBLE_REGSIZE = 8
76
};
77
 
78
enum
79
{
80
  MIPS32_REGSIZE = 4,
81
  MIPS64_REGSIZE = 8
82
};
83
 
84
static const char *mips_abi_string;
85
 
86
static const char *mips_abi_strings[] = {
87
  "auto",
88
  "n32",
89
  "o32",
90
  "n64",
91
  "o64",
92
  "eabi32",
93
  "eabi64",
94
  NULL
95
};
96
 
97
/* The standard register names, and all the valid aliases for them.  */
98
struct register_alias
99
{
100
  const char *name;
101
  int regnum;
102
};
103
 
104
/* Aliases for o32 and most other ABIs.  */
105
const struct register_alias mips_o32_aliases[] = {
106
  { "ta0", 12 },
107
  { "ta1", 13 },
108
  { "ta2", 14 },
109
  { "ta3", 15 }
110
};
111
 
112
/* Aliases for n32 and n64.  */
113
const struct register_alias mips_n32_n64_aliases[] = {
114
  { "ta0", 8 },
115
  { "ta1", 9 },
116
  { "ta2", 10 },
117
  { "ta3", 11 }
118
};
119
 
120
/* Aliases for ABI-independent registers.  */
121
const struct register_alias mips_register_aliases[] = {
122
  /* The architecture manuals specify these ABI-independent names for
123
     the GPRs.  */
124
#define R(n) { "r" #n, n }
125
  R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126
  R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127
  R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128
  R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
129
#undef R
130
 
131
  /* k0 and k1 are sometimes called these instead (for "kernel
132
     temp").  */
133
  { "kt0", 26 },
134
  { "kt1", 27 },
135
 
136
  /* This is the traditional GDB name for the CP0 status register.  */
137
  { "sr", MIPS_PS_REGNUM },
138
 
139
  /* This is the traditional GDB name for the CP0 BadVAddr register.  */
140
  { "bad", MIPS_EMBED_BADVADDR_REGNUM },
141
 
142
  /* This is the traditional GDB name for the FCSR.  */
143
  { "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
144
};
145
 
146
const struct register_alias mips_numeric_register_aliases[] = {
147
#define R(n) { #n, n }
148
  R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149
  R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150
  R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151
  R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
152
#undef R
153
};
154
 
155
#ifndef MIPS_DEFAULT_FPU_TYPE
156
#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157
#endif
158
static int mips_fpu_type_auto = 1;
159
static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
160
 
161
static int mips_debug = 0;
162
 
163
/* Properties (for struct target_desc) describing the g/G packet
164
   layout.  */
165
#define PROPERTY_GP32 "internal: transfers-32bit-registers"
166
#define PROPERTY_GP64 "internal: transfers-64bit-registers"
167
 
168
struct target_desc *mips_tdesc_gp32;
169
struct target_desc *mips_tdesc_gp64;
170
 
171
const struct mips_regnum *
172
mips_regnum (struct gdbarch *gdbarch)
173
{
174
  return gdbarch_tdep (gdbarch)->regnum;
175
}
176
 
177
static int
178
mips_fpa0_regnum (struct gdbarch *gdbarch)
179
{
180
  return mips_regnum (gdbarch)->fp0 + 12;
181
}
182
 
183
#define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
184
                     == MIPS_ABI_EABI32 \
185
                   || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
186
 
187
#define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
188
 
189
#define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
190
 
191
#define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
192
 
193
/* MIPS16 function addresses are odd (bit 0 is set).  Here are some
194
   functions to test, set, or clear bit 0 of addresses.  */
195
 
196
static CORE_ADDR
197
is_mips16_addr (CORE_ADDR addr)
198
{
199
  return ((addr) & 1);
200
}
201
 
202
static CORE_ADDR
203
unmake_mips16_addr (CORE_ADDR addr)
204
{
205
  return ((addr) & ~(CORE_ADDR) 1);
206
}
207
 
208
/* Return the MIPS ABI associated with GDBARCH.  */
209
enum mips_abi
210
mips_abi (struct gdbarch *gdbarch)
211
{
212
  return gdbarch_tdep (gdbarch)->mips_abi;
213
}
214
 
215
int
216
mips_isa_regsize (struct gdbarch *gdbarch)
217
{
218
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
219
 
220
  /* If we know how big the registers are, use that size.  */
221
  if (tdep->register_size_valid_p)
222
    return tdep->register_size;
223
 
224
  /* Fall back to the previous behavior.  */
225
  return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
226
          / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
227
}
228
 
229
/* Return the currently configured (or set) saved register size. */
230
 
231
unsigned int
232
mips_abi_regsize (struct gdbarch *gdbarch)
233
{
234
  switch (mips_abi (gdbarch))
235
    {
236
    case MIPS_ABI_EABI32:
237
    case MIPS_ABI_O32:
238
      return 4;
239
    case MIPS_ABI_N32:
240
    case MIPS_ABI_N64:
241
    case MIPS_ABI_O64:
242
    case MIPS_ABI_EABI64:
243
      return 8;
244
    case MIPS_ABI_UNKNOWN:
245
    case MIPS_ABI_LAST:
246
    default:
247
      internal_error (__FILE__, __LINE__, _("bad switch"));
248
    }
249
}
250
 
251
/* Functions for setting and testing a bit in a minimal symbol that
252
   marks it as 16-bit function.  The MSB of the minimal symbol's
253
   "info" field is used for this purpose.
254
 
255
   gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
256
   i.e. refers to a 16-bit function, and sets a "special" bit in a
257
   minimal symbol to mark it as a 16-bit function
258
 
259
   MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol  */
260
 
261
static void
262
mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
263
{
264
  if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
265
    {
266
      MSYMBOL_TARGET_FLAG_1 (msym) = 1;
267
      SYMBOL_VALUE_ADDRESS (msym) |= 1;
268
    }
269
}
270
 
271
static int
272
msymbol_is_special (struct minimal_symbol *msym)
273
{
274
  return MSYMBOL_TARGET_FLAG_1 (msym);
275
}
276
 
277
/* XFER a value from the big/little/left end of the register.
278
   Depending on the size of the value it might occupy the entire
279
   register or just part of it.  Make an allowance for this, aligning
280
   things accordingly.  */
281
 
282
static void
283
mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
284
                    int reg_num, int length,
285
                    enum bfd_endian endian, gdb_byte *in,
286
                    const gdb_byte *out, int buf_offset)
287
{
288
  int reg_offset = 0;
289
 
290
  gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
291
  /* Need to transfer the left or right part of the register, based on
292
     the targets byte order.  */
293
  switch (endian)
294
    {
295
    case BFD_ENDIAN_BIG:
296
      reg_offset = register_size (gdbarch, reg_num) - length;
297
      break;
298
    case BFD_ENDIAN_LITTLE:
299
      reg_offset = 0;
300
      break;
301
    case BFD_ENDIAN_UNKNOWN:    /* Indicates no alignment.  */
302
      reg_offset = 0;
303
      break;
304
    default:
305
      internal_error (__FILE__, __LINE__, _("bad switch"));
306
    }
307
  if (mips_debug)
308
    fprintf_unfiltered (gdb_stderr,
309
                        "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310
                        reg_num, reg_offset, buf_offset, length);
311
  if (mips_debug && out != NULL)
312
    {
313
      int i;
314
      fprintf_unfiltered (gdb_stdlog, "out ");
315
      for (i = 0; i < length; i++)
316
        fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
317
    }
318
  if (in != NULL)
319
    regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
320
                               in + buf_offset);
321
  if (out != NULL)
322
    regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
323
                                out + buf_offset);
324
  if (mips_debug && in != NULL)
325
    {
326
      int i;
327
      fprintf_unfiltered (gdb_stdlog, "in ");
328
      for (i = 0; i < length; i++)
329
        fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
330
    }
331
  if (mips_debug)
332
    fprintf_unfiltered (gdb_stdlog, "\n");
333
}
334
 
335
/* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
336
   compatiblity mode.  A return value of 1 means that we have
337
   physical 64-bit registers, but should treat them as 32-bit registers.  */
338
 
339
static int
340
mips2_fp_compat (struct frame_info *frame)
341
{
342
  struct gdbarch *gdbarch = get_frame_arch (frame);
343
  /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
344
     meaningful.  */
345
  if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
346
    return 0;
347
 
348
#if 0
349
  /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350
     in all the places we deal with FP registers.  PR gdb/413.  */
351
  /* Otherwise check the FR bit in the status register - it controls
352
     the FP compatiblity mode.  If it is clear we are in compatibility
353
     mode.  */
354
  if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
355
    return 1;
356
#endif
357
 
358
  return 0;
359
}
360
 
361
#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
362
 
363
static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
364
 
365
static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
366
 
367
/* The list of available "set mips " and "show mips " commands */
368
 
369
static struct cmd_list_element *setmipscmdlist = NULL;
370
static struct cmd_list_element *showmipscmdlist = NULL;
371
 
372
/* Integer registers 0 thru 31 are handled explicitly by
373
   mips_register_name().  Processor specific registers 32 and above
374
   are listed in the following tables.  */
375
 
376
enum
377
{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
378
 
379
/* Generic MIPS.  */
380
 
381
static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
382
  "sr", "lo", "hi", "bad", "cause", "pc",
383
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
384
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
385
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
386
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
387
  "fsr", "fir", "" /*"fp" */ , "",
388
  "", "", "", "", "", "", "", "",
389
  "", "", "", "", "", "", "", "",
390
};
391
 
392
/* Names of IDT R3041 registers.  */
393
 
394
static const char *mips_r3041_reg_names[] = {
395
  "sr", "lo", "hi", "bad", "cause", "pc",
396
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
397
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
398
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
399
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
400
  "fsr", "fir", "", /*"fp" */ "",
401
  "", "", "bus", "ccfg", "", "", "", "",
402
  "", "", "port", "cmp", "", "", "epc", "prid",
403
};
404
 
405
/* Names of tx39 registers.  */
406
 
407
static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
408
  "sr", "lo", "hi", "bad", "cause", "pc",
409
  "", "", "", "", "", "", "", "",
410
  "", "", "", "", "", "", "", "",
411
  "", "", "", "", "", "", "", "",
412
  "", "", "", "", "", "", "", "",
413
  "", "", "", "",
414
  "", "", "", "", "", "", "", "",
415
  "", "", "config", "cache", "debug", "depc", "epc", ""
416
};
417
 
418
/* Names of IRIX registers.  */
419
static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
420
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
421
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
422
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
423
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
424
  "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
425
};
426
 
427
 
428
/* Return the name of the register corresponding to REGNO.  */
429
static const char *
430
mips_register_name (struct gdbarch *gdbarch, int regno)
431
{
432
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
433
  /* GPR names for all ABIs other than n32/n64.  */
434
  static char *mips_gpr_names[] = {
435
    "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
436
    "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
437
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
438
    "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
439
  };
440
 
441
  /* GPR names for n32 and n64 ABIs.  */
442
  static char *mips_n32_n64_gpr_names[] = {
443
    "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444
    "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
445
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446
    "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
447
  };
448
 
449
  enum mips_abi abi = mips_abi (gdbarch);
450
 
451
  /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
452
     but then don't make the raw register names visible.  */
453
  int rawnum = regno % gdbarch_num_regs (gdbarch);
454
  if (regno < gdbarch_num_regs (gdbarch))
455
    return "";
456
 
457
  /* The MIPS integer registers are always mapped from 0 to 31.  The
458
     names of the registers (which reflects the conventions regarding
459
     register use) vary depending on the ABI.  */
460
  if (0 <= rawnum && rawnum < 32)
461
    {
462
      if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
463
        return mips_n32_n64_gpr_names[rawnum];
464
      else
465
        return mips_gpr_names[rawnum];
466
    }
467
  else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
468
    return tdesc_register_name (gdbarch, rawnum);
469
  else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
470
    {
471
      gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
472
      return tdep->mips_processor_reg_names[rawnum - 32];
473
    }
474
  else
475
    internal_error (__FILE__, __LINE__,
476
                    _("mips_register_name: bad register number %d"), rawnum);
477
}
478
 
479
/* Return the groups that a MIPS register can be categorised into.  */
480
 
481
static int
482
mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
483
                          struct reggroup *reggroup)
484
{
485
  int vector_p;
486
  int float_p;
487
  int raw_p;
488
  int rawnum = regnum % gdbarch_num_regs (gdbarch);
489
  int pseudo = regnum / gdbarch_num_regs (gdbarch);
490
  if (reggroup == all_reggroup)
491
    return pseudo;
492
  vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
493
  float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
494
  /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
495
     (gdbarch), as not all architectures are multi-arch.  */
496
  raw_p = rawnum < gdbarch_num_regs (gdbarch);
497
  if (gdbarch_register_name (gdbarch, regnum) == NULL
498
      || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
499
    return 0;
500
  if (reggroup == float_reggroup)
501
    return float_p && pseudo;
502
  if (reggroup == vector_reggroup)
503
    return vector_p && pseudo;
504
  if (reggroup == general_reggroup)
505
    return (!vector_p && !float_p) && pseudo;
506
  /* Save the pseudo registers.  Need to make certain that any code
507
     extracting register values from a saved register cache also uses
508
     pseudo registers.  */
509
  if (reggroup == save_reggroup)
510
    return raw_p && pseudo;
511
  /* Restore the same pseudo register.  */
512
  if (reggroup == restore_reggroup)
513
    return raw_p && pseudo;
514
  return 0;
515
}
516
 
517
/* Return the groups that a MIPS register can be categorised into.
518
   This version is only used if we have a target description which
519
   describes real registers (and their groups).  */
520
 
521
static int
522
mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
523
                                struct reggroup *reggroup)
524
{
525
  int rawnum = regnum % gdbarch_num_regs (gdbarch);
526
  int pseudo = regnum / gdbarch_num_regs (gdbarch);
527
  int ret;
528
 
529
  /* Only save, restore, and display the pseudo registers.  Need to
530
     make certain that any code extracting register values from a
531
     saved register cache also uses pseudo registers.
532
 
533
     Note: saving and restoring the pseudo registers is slightly
534
     strange; if we have 64 bits, we should save and restore all
535
     64 bits.  But this is hard and has little benefit.  */
536
  if (!pseudo)
537
    return 0;
538
 
539
  ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
540
  if (ret != -1)
541
    return ret;
542
 
543
  return mips_register_reggroup_p (gdbarch, regnum, reggroup);
544
}
545
 
546
/* Map the symbol table registers which live in the range [1 *
547
   gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
548
   registers.  Take care of alignment and size problems.  */
549
 
550
static void
551
mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
552
                           int cookednum, gdb_byte *buf)
553
{
554
  int rawnum = cookednum % gdbarch_num_regs (gdbarch);
555
  gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
556
              && cookednum < 2 * gdbarch_num_regs (gdbarch));
557
  if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
558
    regcache_raw_read (regcache, rawnum, buf);
559
  else if (register_size (gdbarch, rawnum) >
560
           register_size (gdbarch, cookednum))
561
    {
562
      if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
563
          || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
564
        regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
565
      else
566
        regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
567
    }
568
  else
569
    internal_error (__FILE__, __LINE__, _("bad register size"));
570
}
571
 
572
static void
573
mips_pseudo_register_write (struct gdbarch *gdbarch,
574
                            struct regcache *regcache, int cookednum,
575
                            const gdb_byte *buf)
576
{
577
  int rawnum = cookednum % gdbarch_num_regs (gdbarch);
578
  gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
579
              && cookednum < 2 * gdbarch_num_regs (gdbarch));
580
  if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
581
    regcache_raw_write (regcache, rawnum, buf);
582
  else if (register_size (gdbarch, rawnum) >
583
           register_size (gdbarch, cookednum))
584
    {
585
      if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
586
          || gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
587
        regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
588
      else
589
        regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
590
    }
591
  else
592
    internal_error (__FILE__, __LINE__, _("bad register size"));
593
}
594
 
595
/* Table to translate MIPS16 register field to actual register number.  */
596
static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
597
 
598
/* Heuristic_proc_start may hunt through the text section for a long
599
   time across a 2400 baud serial line.  Allows the user to limit this
600
   search.  */
601
 
602
static unsigned int heuristic_fence_post = 0;
603
 
604
/* Number of bytes of storage in the actual machine representation for
605
   register N.  NOTE: This defines the pseudo register type so need to
606
   rebuild the architecture vector.  */
607
 
608
static int mips64_transfers_32bit_regs_p = 0;
609
 
610
static void
611
set_mips64_transfers_32bit_regs (char *args, int from_tty,
612
                                 struct cmd_list_element *c)
613
{
614
  struct gdbarch_info info;
615
  gdbarch_info_init (&info);
616
  /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
617
     instead of relying on globals.  Doing that would let generic code
618
     handle the search for this specific architecture.  */
619
  if (!gdbarch_update_p (info))
620
    {
621
      mips64_transfers_32bit_regs_p = 0;
622
      error (_("32-bit compatibility mode not supported"));
623
    }
624
}
625
 
626
/* Convert to/from a register and the corresponding memory value.  */
627
 
628
static int
629
mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type)
630
{
631
  return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
632
          && register_size (gdbarch, regnum) == 4
633
          && (regnum % gdbarch_num_regs (gdbarch))
634
                >= mips_regnum (gdbarch)->fp0
635
          && (regnum % gdbarch_num_regs (gdbarch))
636
                < mips_regnum (gdbarch)->fp0 + 32
637
          && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
638
}
639
 
640
static void
641
mips_register_to_value (struct frame_info *frame, int regnum,
642
                        struct type *type, gdb_byte *to)
643
{
644
  get_frame_register (frame, regnum + 0, to + 4);
645
  get_frame_register (frame, regnum + 1, to + 0);
646
}
647
 
648
static void
649
mips_value_to_register (struct frame_info *frame, int regnum,
650
                        struct type *type, const gdb_byte *from)
651
{
652
  put_frame_register (frame, regnum + 0, from + 4);
653
  put_frame_register (frame, regnum + 1, from + 0);
654
}
655
 
656
/* Return the GDB type object for the "standard" data type of data in
657
   register REG.  */
658
 
659
static struct type *
660
mips_register_type (struct gdbarch *gdbarch, int regnum)
661
{
662
  gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch));
663
  if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0
664
      && (regnum % gdbarch_num_regs (gdbarch))
665
         < mips_regnum (gdbarch)->fp0 + 32)
666
    {
667
      /* The floating-point registers raw, or cooked, always match
668
         mips_isa_regsize(), and also map 1:1, byte for byte.  */
669
      if (mips_isa_regsize (gdbarch) == 4)
670
        return builtin_type (gdbarch)->builtin_float;
671
      else
672
        return builtin_type (gdbarch)->builtin_double;
673
    }
674
  else if (regnum < gdbarch_num_regs (gdbarch))
675
    {
676
      /* The raw or ISA registers.  These are all sized according to
677
         the ISA regsize.  */
678
      if (mips_isa_regsize (gdbarch) == 4)
679
        return builtin_type (gdbarch)->builtin_int32;
680
      else
681
        return builtin_type (gdbarch)->builtin_int64;
682
    }
683
  else
684
    {
685
      /* The cooked or ABI registers.  These are sized according to
686
         the ABI (with a few complications).  */
687
      if (regnum >= (gdbarch_num_regs (gdbarch)
688
                     + mips_regnum (gdbarch)->fp_control_status)
689
          && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM)
690
        /* The pseudo/cooked view of the embedded registers is always
691
           32-bit.  The raw view is handled below.  */
692
        return builtin_type (gdbarch)->builtin_int32;
693
      else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
694
        /* The target, while possibly using a 64-bit register buffer,
695
           is only transfering 32-bits of each integer register.
696
           Reflect this in the cooked/pseudo (ABI) register value.  */
697
        return builtin_type (gdbarch)->builtin_int32;
698
      else if (mips_abi_regsize (gdbarch) == 4)
699
        /* The ABI is restricted to 32-bit registers (the ISA could be
700
           32- or 64-bit).  */
701
        return builtin_type (gdbarch)->builtin_int32;
702
      else
703
        /* 64-bit ABI.  */
704
        return builtin_type (gdbarch)->builtin_int64;
705
    }
706
}
707
 
708
/* Return the GDB type for the pseudo register REGNUM, which is the
709
   ABI-level view.  This function is only called if there is a target
710
   description which includes registers, so we know precisely the
711
   types of hardware registers.  */
712
 
713
static struct type *
714
mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
715
{
716
  const int num_regs = gdbarch_num_regs (gdbarch);
717
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
718
  int rawnum = regnum % num_regs;
719
  struct type *rawtype;
720
 
721
  gdb_assert (regnum >= num_regs && regnum < 2 * num_regs);
722
 
723
  /* Absent registers are still absent.  */
724
  rawtype = gdbarch_register_type (gdbarch, rawnum);
725
  if (TYPE_LENGTH (rawtype) == 0)
726
    return rawtype;
727
 
728
  if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32)
729
    /* Present the floating point registers however the hardware did;
730
       do not try to convert between FPU layouts.  */
731
    return rawtype;
732
 
733
  if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM)
734
    {
735
      /* The pseudo/cooked view of embedded registers is always
736
         32-bit, even if the target transfers 64-bit values for them.
737
         New targets relying on XML descriptions should only transfer
738
         the necessary 32 bits, but older versions of GDB expected 64,
739
         so allow the target to provide 64 bits without interfering
740
         with the displayed type.  */
741
      return builtin_type (gdbarch)->builtin_int32;
742
    }
743
 
744
  /* Use pointer types for registers if we can.  For n32 we can not,
745
     since we do not have a 64-bit pointer type.  */
746
  if (mips_abi_regsize (gdbarch)
747
      == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
748
    {
749
      if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM)
750
        return builtin_type (gdbarch)->builtin_data_ptr;
751
      else if (rawnum == MIPS_EMBED_PC_REGNUM)
752
        return builtin_type (gdbarch)->builtin_func_ptr;
753
    }
754
 
755
  if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
756
      && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM)
757
    return builtin_type (gdbarch)->builtin_int32;
758
 
759
  /* For all other registers, pass through the hardware type.  */
760
  return rawtype;
761
}
762
 
763
/* Should the upper word of 64-bit addresses be zeroed? */
764
enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
765
 
766
static int
767
mips_mask_address_p (struct gdbarch_tdep *tdep)
768
{
769
  switch (mask_address_var)
770
    {
771
    case AUTO_BOOLEAN_TRUE:
772
      return 1;
773
    case AUTO_BOOLEAN_FALSE:
774
      return 0;
775
      break;
776
    case AUTO_BOOLEAN_AUTO:
777
      return tdep->default_mask_address_p;
778
    default:
779
      internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
780
      return -1;
781
    }
782
}
783
 
784
static void
785
show_mask_address (struct ui_file *file, int from_tty,
786
                   struct cmd_list_element *c, const char *value)
787
{
788
  struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
789
 
790
  deprecated_show_value_hack (file, from_tty, c, value);
791
  switch (mask_address_var)
792
    {
793
    case AUTO_BOOLEAN_TRUE:
794
      printf_filtered ("The 32 bit mips address mask is enabled\n");
795
      break;
796
    case AUTO_BOOLEAN_FALSE:
797
      printf_filtered ("The 32 bit mips address mask is disabled\n");
798
      break;
799
    case AUTO_BOOLEAN_AUTO:
800
      printf_filtered
801
        ("The 32 bit address mask is set automatically.  Currently %s\n",
802
         mips_mask_address_p (tdep) ? "enabled" : "disabled");
803
      break;
804
    default:
805
      internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
806
      break;
807
    }
808
}
809
 
810
/* Tell if the program counter value in MEMADDR is in a MIPS16 function.  */
811
 
812
int
813
mips_pc_is_mips16 (CORE_ADDR memaddr)
814
{
815
  struct minimal_symbol *sym;
816
 
817
  /* If bit 0 of the address is set, assume this is a MIPS16 address. */
818
  if (is_mips16_addr (memaddr))
819
    return 1;
820
 
821
  /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
822
     the high bit of the info field.  Use this to decide if the function is
823
     MIPS16 or normal MIPS.  */
824
  sym = lookup_minimal_symbol_by_pc (memaddr);
825
  if (sym)
826
    return msymbol_is_special (sym);
827
  else
828
    return 0;
829
}
830
 
831
/* MIPS believes that the PC has a sign extended value.  Perhaps the
832
   all registers should be sign extended for simplicity? */
833
 
834
static CORE_ADDR
835
mips_read_pc (struct regcache *regcache)
836
{
837
  ULONGEST pc;
838
  int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
839
  regcache_cooked_read_signed (regcache, regnum, &pc);
840
  return pc;
841
}
842
 
843
static CORE_ADDR
844
mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
845
{
846
  return frame_unwind_register_signed
847
           (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc);
848
}
849
 
850
static CORE_ADDR
851
mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
852
{
853
  return frame_unwind_register_signed
854
           (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
855
}
856
 
857
/* Assuming THIS_FRAME is a dummy, return the frame ID of that
858
   dummy frame.  The frame ID's base needs to match the TOS value
859
   saved by save_dummy_frame_tos(), and the PC match the dummy frame's
860
   breakpoint.  */
861
 
862
static struct frame_id
863
mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
864
{
865
  return frame_id_build
866
           (get_frame_register_signed (this_frame,
867
                                       gdbarch_num_regs (gdbarch)
868
                                       + MIPS_SP_REGNUM),
869
            get_frame_pc (this_frame));
870
}
871
 
872
static void
873
mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
874
{
875
  int regnum = mips_regnum (get_regcache_arch (regcache))->pc;
876
  regcache_cooked_write_unsigned (regcache, regnum, pc);
877
}
878
 
879
/* Fetch and return instruction from the specified location.  If the PC
880
   is odd, assume it's a MIPS16 instruction; otherwise MIPS32.  */
881
 
882
static ULONGEST
883
mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr)
884
{
885
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
886
  gdb_byte buf[MIPS_INSN32_SIZE];
887
  int instlen;
888
  int status;
889
 
890
  if (mips_pc_is_mips16 (addr))
891
    {
892
      instlen = MIPS_INSN16_SIZE;
893
      addr = unmake_mips16_addr (addr);
894
    }
895
  else
896
    instlen = MIPS_INSN32_SIZE;
897
  status = target_read_memory (addr, buf, instlen);
898
  if (status)
899
    memory_error (status, addr);
900
  return extract_unsigned_integer (buf, instlen, byte_order);
901
}
902
 
903
/* These the fields of 32 bit mips instructions */
904
#define mips32_op(x) (x >> 26)
905
#define itype_op(x) (x >> 26)
906
#define itype_rs(x) ((x >> 21) & 0x1f)
907
#define itype_rt(x) ((x >> 16) & 0x1f)
908
#define itype_immediate(x) (x & 0xffff)
909
 
910
#define jtype_op(x) (x >> 26)
911
#define jtype_target(x) (x & 0x03ffffff)
912
 
913
#define rtype_op(x) (x >> 26)
914
#define rtype_rs(x) ((x >> 21) & 0x1f)
915
#define rtype_rt(x) ((x >> 16) & 0x1f)
916
#define rtype_rd(x) ((x >> 11) & 0x1f)
917
#define rtype_shamt(x) ((x >> 6) & 0x1f)
918
#define rtype_funct(x) (x & 0x3f)
919
 
920
static LONGEST
921
mips32_relative_offset (ULONGEST inst)
922
{
923
  return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
924
}
925
 
926
/* Determine where to set a single step breakpoint while considering
927
   branch prediction.  */
928
static CORE_ADDR
929
mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
930
{
931
  struct gdbarch *gdbarch = get_frame_arch (frame);
932
  unsigned long inst;
933
  int op;
934
  inst = mips_fetch_instruction (gdbarch, pc);
935
  if ((inst & 0xe0000000) != 0)  /* Not a special, jump or branch instruction */
936
    {
937
      if (itype_op (inst) >> 2 == 5)
938
        /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
939
        {
940
          op = (itype_op (inst) & 0x03);
941
          switch (op)
942
            {
943
            case 0:              /* BEQL */
944
              goto equal_branch;
945
            case 1:             /* BNEL */
946
              goto neq_branch;
947
            case 2:             /* BLEZL */
948
              goto less_branch;
949
            case 3:             /* BGTZL */
950
              goto greater_branch;
951
            default:
952
              pc += 4;
953
            }
954
        }
955
      else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
956
        /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
957
        {
958
          int tf = itype_rt (inst) & 0x01;
959
          int cnum = itype_rt (inst) >> 2;
960
          int fcrcs =
961
            get_frame_register_signed (frame,
962
                                       mips_regnum (get_frame_arch (frame))->
963
                                                fp_control_status);
964
          int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
965
 
966
          if (((cond >> cnum) & 0x01) == tf)
967
            pc += mips32_relative_offset (inst) + 4;
968
          else
969
            pc += 8;
970
        }
971
      else
972
        pc += 4;                /* Not a branch, next instruction is easy */
973
    }
974
  else
975
    {                           /* This gets way messy */
976
 
977
      /* Further subdivide into SPECIAL, REGIMM and other */
978
      switch (op = itype_op (inst) & 0x07)      /* extract bits 28,27,26 */
979
        {
980
        case 0:          /* SPECIAL */
981
          op = rtype_funct (inst);
982
          switch (op)
983
            {
984
            case 8:             /* JR */
985
            case 9:             /* JALR */
986
              /* Set PC to that address */
987
              pc = get_frame_register_signed (frame, rtype_rs (inst));
988
              break;
989
            case 12:            /* SYSCALL */
990
              {
991
                struct gdbarch_tdep *tdep;
992
 
993
                tdep = gdbarch_tdep (get_frame_arch (frame));
994
                if (tdep->syscall_next_pc != NULL)
995
                  pc = tdep->syscall_next_pc (frame);
996
                else
997
                  pc += 4;
998
              }
999
              break;
1000
            default:
1001
              pc += 4;
1002
            }
1003
 
1004
          break;                /* end SPECIAL */
1005
        case 1:         /* REGIMM */
1006
          {
1007
            op = itype_rt (inst);       /* branch condition */
1008
            switch (op)
1009
              {
1010
              case 0:            /* BLTZ */
1011
              case 2:           /* BLTZL */
1012
              case 16:          /* BLTZAL */
1013
              case 18:          /* BLTZALL */
1014
              less_branch:
1015
                if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
1016
                  pc += mips32_relative_offset (inst) + 4;
1017
                else
1018
                  pc += 8;      /* after the delay slot */
1019
                break;
1020
              case 1:           /* BGEZ */
1021
              case 3:           /* BGEZL */
1022
              case 17:          /* BGEZAL */
1023
              case 19:          /* BGEZALL */
1024
                if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
1025
                  pc += mips32_relative_offset (inst) + 4;
1026
                else
1027
                  pc += 8;      /* after the delay slot */
1028
                break;
1029
                /* All of the other instructions in the REGIMM category */
1030
              default:
1031
                pc += 4;
1032
              }
1033
          }
1034
          break;                /* end REGIMM */
1035
        case 2:         /* J */
1036
        case 3:         /* JAL */
1037
          {
1038
            unsigned long reg;
1039
            reg = jtype_target (inst) << 2;
1040
            /* Upper four bits get never changed... */
1041
            pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1042
          }
1043
          break;
1044
          /* FIXME case JALX : */
1045
          {
1046
            unsigned long reg;
1047
            reg = jtype_target (inst) << 2;
1048
            pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1;        /* yes, +1 */
1049
            /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1050
          }
1051
          break;                /* The new PC will be alternate mode */
1052
        case 4:         /* BEQ, BEQL */
1053
        equal_branch:
1054
          if (get_frame_register_signed (frame, itype_rs (inst)) ==
1055
              get_frame_register_signed (frame, itype_rt (inst)))
1056
            pc += mips32_relative_offset (inst) + 4;
1057
          else
1058
            pc += 8;
1059
          break;
1060
        case 5:         /* BNE, BNEL */
1061
        neq_branch:
1062
          if (get_frame_register_signed (frame, itype_rs (inst)) !=
1063
              get_frame_register_signed (frame, itype_rt (inst)))
1064
            pc += mips32_relative_offset (inst) + 4;
1065
          else
1066
            pc += 8;
1067
          break;
1068
        case 6:         /* BLEZ, BLEZL */
1069
          if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
1070
            pc += mips32_relative_offset (inst) + 4;
1071
          else
1072
            pc += 8;
1073
          break;
1074
        case 7:
1075
        default:
1076
        greater_branch: /* BGTZ, BGTZL */
1077
          if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
1078
            pc += mips32_relative_offset (inst) + 4;
1079
          else
1080
            pc += 8;
1081
          break;
1082
        }                       /* switch */
1083
    }                           /* else */
1084
  return pc;
1085
}                               /* mips32_next_pc */
1086
 
1087
/* Decoding the next place to set a breakpoint is irregular for the
1088
   mips 16 variant, but fortunately, there fewer instructions. We have to cope
1089
   ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1090
   We dont want to set a single step instruction on the extend instruction
1091
   either.
1092
 */
1093
 
1094
/* Lots of mips16 instruction formats */
1095
/* Predicting jumps requires itype,ritype,i8type
1096
   and their extensions      extItype,extritype,extI8type
1097
 */
1098
enum mips16_inst_fmts
1099
{
1100
  itype,                        /* 0  immediate 5,10 */
1101
  ritype,                       /* 1   5,3,8 */
1102
  rrtype,                       /* 2   5,3,3,5 */
1103
  rritype,                      /* 3   5,3,3,5 */
1104
  rrrtype,                      /* 4   5,3,3,3,2 */
1105
  rriatype,                     /* 5   5,3,3,1,4 */
1106
  shifttype,                    /* 6   5,3,3,3,2 */
1107
  i8type,                       /* 7   5,3,8 */
1108
  i8movtype,                    /* 8   5,3,3,5 */
1109
  i8mov32rtype,                 /* 9   5,3,5,3 */
1110
  i64type,                      /* 10  5,3,8 */
1111
  ri64type,                     /* 11  5,3,3,5 */
1112
  jalxtype,                     /* 12  5,1,5,5,16 - a 32 bit instruction */
1113
  exiItype,                     /* 13  5,6,5,5,1,1,1,1,1,1,5 */
1114
  extRitype,                    /* 14  5,6,5,5,3,1,1,1,5 */
1115
  extRRItype,                   /* 15  5,5,5,5,3,3,5 */
1116
  extRRIAtype,                  /* 16  5,7,4,5,3,3,1,4 */
1117
  EXTshifttype,                 /* 17  5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1118
  extI8type,                    /* 18  5,6,5,5,3,1,1,1,5 */
1119
  extI64type,                   /* 19  5,6,5,5,3,1,1,1,5 */
1120
  extRi64type,                  /* 20  5,6,5,5,3,3,5 */
1121
  extshift64type                /* 21  5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1122
};
1123
/* I am heaping all the fields of the formats into one structure and
1124
   then, only the fields which are involved in instruction extension */
1125
struct upk_mips16
1126
{
1127
  CORE_ADDR offset;
1128
  unsigned int regx;            /* Function in i8 type */
1129
  unsigned int regy;
1130
};
1131
 
1132
 
1133
/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1134
   for the bits which make up the immediate extension.  */
1135
 
1136
static CORE_ADDR
1137
extended_offset (unsigned int extension)
1138
{
1139
  CORE_ADDR value;
1140
  value = (extension >> 21) & 0x3f;     /* * extract 15:11 */
1141
  value = value << 6;
1142
  value |= (extension >> 16) & 0x1f;    /* extrace 10:5 */
1143
  value = value << 5;
1144
  value |= extension & 0x01f;   /* extract 4:0 */
1145
  return value;
1146
}
1147
 
1148
/* Only call this function if you know that this is an extendable
1149
   instruction.  It won't malfunction, but why make excess remote memory
1150
   references?  If the immediate operands get sign extended or something,
1151
   do it after the extension is performed.  */
1152
/* FIXME: Every one of these cases needs to worry about sign extension
1153
   when the offset is to be used in relative addressing.  */
1154
 
1155
static unsigned int
1156
fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc)
1157
{
1158
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1159
  gdb_byte buf[8];
1160
  pc &= 0xfffffffe;             /* clear the low order bit */
1161
  target_read_memory (pc, buf, 2);
1162
  return extract_unsigned_integer (buf, 2, byte_order);
1163
}
1164
 
1165
static void
1166
unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc,
1167
               unsigned int extension,
1168
               unsigned int inst,
1169
               enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1170
{
1171
  CORE_ADDR offset;
1172
  int regx;
1173
  int regy;
1174
  switch (insn_format)
1175
    {
1176
    case itype:
1177
      {
1178
        CORE_ADDR value;
1179
        if (extension)
1180
          {
1181
            value = extended_offset (extension);
1182
            value = value << 11;        /* rom for the original value */
1183
            value |= inst & 0x7ff;      /* eleven bits from instruction */
1184
          }
1185
        else
1186
          {
1187
            value = inst & 0x7ff;
1188
            /* FIXME : Consider sign extension */
1189
          }
1190
        offset = value;
1191
        regx = -1;
1192
        regy = -1;
1193
      }
1194
      break;
1195
    case ritype:
1196
    case i8type:
1197
      {                         /* A register identifier and an offset */
1198
        /* Most of the fields are the same as I type but the
1199
           immediate value is of a different length */
1200
        CORE_ADDR value;
1201
        if (extension)
1202
          {
1203
            value = extended_offset (extension);
1204
            value = value << 8; /* from the original instruction */
1205
            value |= inst & 0xff;       /* eleven bits from instruction */
1206
            regx = (extension >> 8) & 0x07;     /* or i8 funct */
1207
            if (value & 0x4000) /* test the sign bit , bit 26 */
1208
              {
1209
                value &= ~0x3fff;       /* remove the sign bit */
1210
                value = -value;
1211
              }
1212
          }
1213
        else
1214
          {
1215
            value = inst & 0xff;        /* 8 bits */
1216
            regx = (inst >> 8) & 0x07;  /* or i8 funct */
1217
            /* FIXME: Do sign extension , this format needs it */
1218
            if (value & 0x80)   /* THIS CONFUSES ME */
1219
              {
1220
                value &= 0xef;  /* remove the sign bit */
1221
                value = -value;
1222
              }
1223
          }
1224
        offset = value;
1225
        regy = -1;
1226
        break;
1227
      }
1228
    case jalxtype:
1229
      {
1230
        unsigned long value;
1231
        unsigned int nexthalf;
1232
        value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1233
        value = value << 16;
1234
        nexthalf = mips_fetch_instruction (gdbarch, pc + 2);    /* low bit still set */
1235
        value |= nexthalf;
1236
        offset = value;
1237
        regx = -1;
1238
        regy = -1;
1239
        break;
1240
      }
1241
    default:
1242
      internal_error (__FILE__, __LINE__, _("bad switch"));
1243
    }
1244
  upk->offset = offset;
1245
  upk->regx = regx;
1246
  upk->regy = regy;
1247
}
1248
 
1249
 
1250
static CORE_ADDR
1251
add_offset_16 (CORE_ADDR pc, int offset)
1252
{
1253
  return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1254
}
1255
 
1256
static CORE_ADDR
1257
extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
1258
                         unsigned int extension, unsigned int insn)
1259
{
1260
  struct gdbarch *gdbarch = get_frame_arch (frame);
1261
  int op = (insn >> 11);
1262
  switch (op)
1263
    {
1264
    case 2:                     /* Branch */
1265
      {
1266
        CORE_ADDR offset;
1267
        struct upk_mips16 upk;
1268
        unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk);
1269
        offset = upk.offset;
1270
        if (offset & 0x800)
1271
          {
1272
            offset &= 0xeff;
1273
            offset = -offset;
1274
          }
1275
        pc += (offset << 1) + 2;
1276
        break;
1277
      }
1278
    case 3:                     /* JAL , JALX - Watch out, these are 32 bit instruction */
1279
      {
1280
        struct upk_mips16 upk;
1281
        unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk);
1282
        pc = add_offset_16 (pc, upk.offset);
1283
        if ((insn >> 10) & 0x01)        /* Exchange mode */
1284
          pc = pc & ~0x01;      /* Clear low bit, indicate 32 bit mode */
1285
        else
1286
          pc |= 0x01;
1287
        break;
1288
      }
1289
    case 4:                     /* beqz */
1290
      {
1291
        struct upk_mips16 upk;
1292
        int reg;
1293
        unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
1294
        reg = get_frame_register_signed (frame, upk.regx);
1295
        if (reg == 0)
1296
          pc += (upk.offset << 1) + 2;
1297
        else
1298
          pc += 2;
1299
        break;
1300
      }
1301
    case 5:                     /* bnez */
1302
      {
1303
        struct upk_mips16 upk;
1304
        int reg;
1305
        unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
1306
        reg = get_frame_register_signed (frame, upk.regx);
1307
        if (reg != 0)
1308
          pc += (upk.offset << 1) + 2;
1309
        else
1310
          pc += 2;
1311
        break;
1312
      }
1313
    case 12:                    /* I8 Formats btez btnez */
1314
      {
1315
        struct upk_mips16 upk;
1316
        int reg;
1317
        unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
1318
        /* upk.regx contains the opcode */
1319
        reg = get_frame_register_signed (frame, 24);  /* Test register is 24 */
1320
        if (((upk.regx == 0) && (reg == 0))       /* BTEZ */
1321
            || ((upk.regx == 1) && (reg != 0)))  /* BTNEZ */
1322
          /* pc = add_offset_16(pc,upk.offset) ; */
1323
          pc += (upk.offset << 1) + 2;
1324
        else
1325
          pc += 2;
1326
        break;
1327
      }
1328
    case 29:                    /* RR Formats JR, JALR, JALR-RA */
1329
      {
1330
        struct upk_mips16 upk;
1331
        /* upk.fmt = rrtype; */
1332
        op = insn & 0x1f;
1333
        if (op == 0)
1334
          {
1335
            int reg;
1336
            upk.regx = (insn >> 8) & 0x07;
1337
            upk.regy = (insn >> 5) & 0x07;
1338
            switch (upk.regy)
1339
              {
1340
              case 0:
1341
                reg = upk.regx;
1342
                break;
1343
              case 1:
1344
                reg = 31;
1345
                break;          /* Function return instruction */
1346
              case 2:
1347
                reg = upk.regx;
1348
                break;
1349
              default:
1350
                reg = 31;
1351
                break;          /* BOGUS Guess */
1352
              }
1353
            pc = get_frame_register_signed (frame, reg);
1354
          }
1355
        else
1356
          pc += 2;
1357
        break;
1358
      }
1359
    case 30:
1360
      /* This is an instruction extension.  Fetch the real instruction
1361
         (which follows the extension) and decode things based on
1362
         that. */
1363
      {
1364
        pc += 2;
1365
        pc = extended_mips16_next_pc (frame, pc, insn,
1366
                                      fetch_mips_16 (gdbarch, pc));
1367
        break;
1368
      }
1369
    default:
1370
      {
1371
        pc += 2;
1372
        break;
1373
      }
1374
    }
1375
  return pc;
1376
}
1377
 
1378
static CORE_ADDR
1379
mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
1380
{
1381
  struct gdbarch *gdbarch = get_frame_arch (frame);
1382
  unsigned int insn = fetch_mips_16 (gdbarch, pc);
1383
  return extended_mips16_next_pc (frame, pc, 0, insn);
1384
}
1385
 
1386
/* The mips_next_pc function supports single_step when the remote
1387
   target monitor or stub is not developed enough to do a single_step.
1388
   It works by decoding the current instruction and predicting where a
1389
   branch will go. This isnt hard because all the data is available.
1390
   The MIPS32 and MIPS16 variants are quite different.  */
1391
static CORE_ADDR
1392
mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
1393
{
1394
  if (is_mips16_addr (pc))
1395
    return mips16_next_pc (frame, pc);
1396
  else
1397
    return mips32_next_pc (frame, pc);
1398
}
1399
 
1400
struct mips_frame_cache
1401
{
1402
  CORE_ADDR base;
1403
  struct trad_frame_saved_reg *saved_regs;
1404
};
1405
 
1406
/* Set a register's saved stack address in temp_saved_regs.  If an
1407
   address has already been set for this register, do nothing; this
1408
   way we will only recognize the first save of a given register in a
1409
   function prologue.
1410
 
1411
   For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1412
   [gdbarch_num_regs .. 2*gdbarch_num_regs).
1413
   Strictly speaking, only the second range is used as it is only second
1414
   range (the ABI instead of ISA registers) that comes into play when finding
1415
   saved registers in a frame.  */
1416
 
1417
static void
1418
set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache,
1419
                int regnum, CORE_ADDR offset)
1420
{
1421
  if (this_cache != NULL
1422
      && this_cache->saved_regs[regnum].addr == -1)
1423
    {
1424
      this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
1425
        = offset;
1426
      this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
1427
        = offset;
1428
    }
1429
}
1430
 
1431
 
1432
/* Fetch the immediate value from a MIPS16 instruction.
1433
   If the previous instruction was an EXTEND, use it to extend
1434
   the upper bits of the immediate value.  This is a helper function
1435
   for mips16_scan_prologue.  */
1436
 
1437
static int
1438
mips16_get_imm (unsigned short prev_inst,       /* previous instruction */
1439
                unsigned short inst,    /* current instruction */
1440
                int nbits,      /* number of bits in imm field */
1441
                int scale,      /* scale factor to be applied to imm */
1442
                int is_signed)  /* is the imm field signed? */
1443
{
1444
  int offset;
1445
 
1446
  if ((prev_inst & 0xf800) == 0xf000)   /* prev instruction was EXTEND? */
1447
    {
1448
      offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1449
      if (offset & 0x8000)      /* check for negative extend */
1450
        offset = 0 - (0x10000 - (offset & 0xffff));
1451
      return offset | (inst & 0x1f);
1452
    }
1453
  else
1454
    {
1455
      int max_imm = 1 << nbits;
1456
      int mask = max_imm - 1;
1457
      int sign_bit = max_imm >> 1;
1458
 
1459
      offset = inst & mask;
1460
      if (is_signed && (offset & sign_bit))
1461
        offset = 0 - (max_imm - offset);
1462
      return offset * scale;
1463
    }
1464
}
1465
 
1466
 
1467
/* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1468
   the associated FRAME_CACHE if not null.
1469
   Return the address of the first instruction past the prologue.  */
1470
 
1471
static CORE_ADDR
1472
mips16_scan_prologue (struct gdbarch *gdbarch,
1473
                      CORE_ADDR start_pc, CORE_ADDR limit_pc,
1474
                      struct frame_info *this_frame,
1475
                      struct mips_frame_cache *this_cache)
1476
{
1477
  CORE_ADDR cur_pc;
1478
  CORE_ADDR frame_addr = 0;      /* Value of $r17, used as frame pointer */
1479
  CORE_ADDR sp;
1480
  long frame_offset = 0;        /* Size of stack frame.  */
1481
  long frame_adjust = 0;        /* Offset of FP from SP.  */
1482
  int frame_reg = MIPS_SP_REGNUM;
1483
  unsigned short prev_inst = 0;  /* saved copy of previous instruction */
1484
  unsigned inst = 0;             /* current instruction */
1485
  unsigned entry_inst = 0;       /* the entry instruction */
1486
  unsigned save_inst = 0;        /* the save instruction */
1487
  int reg, offset;
1488
 
1489
  int extend_bytes = 0;
1490
  int prev_extend_bytes;
1491
  CORE_ADDR end_prologue_addr = 0;
1492
 
1493
  /* Can be called when there's no process, and hence when there's no
1494
     THIS_FRAME.  */
1495
  if (this_frame != NULL)
1496
    sp = get_frame_register_signed (this_frame,
1497
                                    gdbarch_num_regs (gdbarch)
1498
                                    + MIPS_SP_REGNUM);
1499
  else
1500
    sp = 0;
1501
 
1502
  if (limit_pc > start_pc + 200)
1503
    limit_pc = start_pc + 200;
1504
 
1505
  for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1506
    {
1507
      /* Save the previous instruction.  If it's an EXTEND, we'll extract
1508
         the immediate offset extension from it in mips16_get_imm.  */
1509
      prev_inst = inst;
1510
 
1511
      /* Fetch and decode the instruction.   */
1512
      inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc);
1513
 
1514
      /* Normally we ignore extend instructions.  However, if it is
1515
         not followed by a valid prologue instruction, then this
1516
         instruction is not part of the prologue either.  We must
1517
         remember in this case to adjust the end_prologue_addr back
1518
         over the extend.  */
1519
      if ((inst & 0xf800) == 0xf000)    /* extend */
1520
        {
1521
          extend_bytes = MIPS_INSN16_SIZE;
1522
          continue;
1523
        }
1524
 
1525
      prev_extend_bytes = extend_bytes;
1526
      extend_bytes = 0;
1527
 
1528
      if ((inst & 0xff00) == 0x6300     /* addiu sp */
1529
          || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1530
        {
1531
          offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1532
          if (offset < 0)        /* negative stack adjustment? */
1533
            frame_offset -= offset;
1534
          else
1535
            /* Exit loop if a positive stack adjustment is found, which
1536
               usually means that the stack cleanup code in the function
1537
               epilogue is reached.  */
1538
            break;
1539
        }
1540
      else if ((inst & 0xf800) == 0xd000)       /* sw reg,n($sp) */
1541
        {
1542
          offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1543
          reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1544
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1545
        }
1546
      else if ((inst & 0xff00) == 0xf900)       /* sd reg,n($sp) */
1547
        {
1548
          offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1549
          reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1550
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1551
        }
1552
      else if ((inst & 0xff00) == 0x6200)       /* sw $ra,n($sp) */
1553
        {
1554
          offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1555
          set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1556
        }
1557
      else if ((inst & 0xff00) == 0xfa00)       /* sd $ra,n($sp) */
1558
        {
1559
          offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1560
          set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1561
        }
1562
      else if (inst == 0x673d)  /* move $s1, $sp */
1563
        {
1564
          frame_addr = sp;
1565
          frame_reg = 17;
1566
        }
1567
      else if ((inst & 0xff00) == 0x0100)       /* addiu $s1,sp,n */
1568
        {
1569
          offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1570
          frame_addr = sp + offset;
1571
          frame_reg = 17;
1572
          frame_adjust = offset;
1573
        }
1574
      else if ((inst & 0xFF00) == 0xd900)       /* sw reg,offset($s1) */
1575
        {
1576
          offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1577
          reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1578
          set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1579
        }
1580
      else if ((inst & 0xFF00) == 0x7900)       /* sd reg,offset($s1) */
1581
        {
1582
          offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1583
          reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1584
          set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
1585
        }
1586
      else if ((inst & 0xf81f) == 0xe809
1587
               && (inst & 0x700) != 0x700)      /* entry */
1588
        entry_inst = inst;      /* save for later processing */
1589
      else if ((inst & 0xff80) == 0x6480)       /* save */
1590
        {
1591
          save_inst = inst;     /* save for later processing */
1592
          if (prev_extend_bytes)                /* extend */
1593
            save_inst |= prev_inst << 16;
1594
        }
1595
      else if ((inst & 0xf800) == 0x1800)       /* jal(x) */
1596
        cur_pc += MIPS_INSN16_SIZE;     /* 32-bit instruction */
1597
      else if ((inst & 0xff1c) == 0x6704)       /* move reg,$a0-$a3 */
1598
        {
1599
          /* This instruction is part of the prologue, but we don't
1600
             need to do anything special to handle it.  */
1601
        }
1602
      else
1603
        {
1604
          /* This instruction is not an instruction typically found
1605
             in a prologue, so we must have reached the end of the
1606
             prologue.  */
1607
          if (end_prologue_addr == 0)
1608
            end_prologue_addr = cur_pc - prev_extend_bytes;
1609
        }
1610
    }
1611
 
1612
  /* The entry instruction is typically the first instruction in a function,
1613
     and it stores registers at offsets relative to the value of the old SP
1614
     (before the prologue).  But the value of the sp parameter to this
1615
     function is the new SP (after the prologue has been executed).  So we
1616
     can't calculate those offsets until we've seen the entire prologue,
1617
     and can calculate what the old SP must have been. */
1618
  if (entry_inst != 0)
1619
    {
1620
      int areg_count = (entry_inst >> 8) & 7;
1621
      int sreg_count = (entry_inst >> 6) & 3;
1622
 
1623
      /* The entry instruction always subtracts 32 from the SP.  */
1624
      frame_offset += 32;
1625
 
1626
      /* Now we can calculate what the SP must have been at the
1627
         start of the function prologue.  */
1628
      sp += frame_offset;
1629
 
1630
      /* Check if a0-a3 were saved in the caller's argument save area.  */
1631
      for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1632
        {
1633
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1634
          offset += mips_abi_regsize (gdbarch);
1635
        }
1636
 
1637
      /* Check if the ra register was pushed on the stack.  */
1638
      offset = -4;
1639
      if (entry_inst & 0x20)
1640
        {
1641
          set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1642
          offset -= mips_abi_regsize (gdbarch);
1643
        }
1644
 
1645
      /* Check if the s0 and s1 registers were pushed on the stack.  */
1646
      for (reg = 16; reg < sreg_count + 16; reg++)
1647
        {
1648
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1649
          offset -= mips_abi_regsize (gdbarch);
1650
        }
1651
    }
1652
 
1653
  /* The SAVE instruction is similar to ENTRY, except that defined by the
1654
     MIPS16e ASE of the MIPS Architecture.  Unlike with ENTRY though, the
1655
     size of the frame is specified as an immediate field of instruction
1656
     and an extended variation exists which lets additional registers and
1657
     frame space to be specified.  The instruction always treats registers
1658
     as 32-bit so its usefulness for 64-bit ABIs is questionable.  */
1659
  if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4)
1660
    {
1661
      static int args_table[16] = {
1662
        0, 0, 0, 0, 1, 1, 1, 1,
1663
        2, 2, 2, 0, 3, 3, 4, -1,
1664
      };
1665
      static int astatic_table[16] = {
1666
        0, 1, 2, 3, 0, 1, 2, 3,
1667
        0, 1, 2, 4, 0, 1, 0, -1,
1668
      };
1669
      int aregs = (save_inst >> 16) & 0xf;
1670
      int xsregs = (save_inst >> 24) & 0x7;
1671
      int args = args_table[aregs];
1672
      int astatic = astatic_table[aregs];
1673
      long frame_size;
1674
 
1675
      if (args < 0)
1676
        {
1677
          warning (_("Invalid number of argument registers encoded in SAVE."));
1678
          args = 0;
1679
        }
1680
      if (astatic < 0)
1681
        {
1682
          warning (_("Invalid number of static registers encoded in SAVE."));
1683
          astatic = 0;
1684
        }
1685
 
1686
      /* For standard SAVE the frame size of 0 means 128.  */
1687
      frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf);
1688
      if (frame_size == 0 && (save_inst >> 16) == 0)
1689
        frame_size = 16;
1690
      frame_size *= 8;
1691
      frame_offset += frame_size;
1692
 
1693
      /* Now we can calculate what the SP must have been at the
1694
         start of the function prologue.  */
1695
      sp += frame_offset;
1696
 
1697
      /* Check if A0-A3 were saved in the caller's argument save area.  */
1698
      for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++)
1699
        {
1700
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1701
          offset += mips_abi_regsize (gdbarch);
1702
        }
1703
 
1704
      offset = -4;
1705
 
1706
      /* Check if the RA register was pushed on the stack.  */
1707
      if (save_inst & 0x40)
1708
        {
1709
          set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset);
1710
          offset -= mips_abi_regsize (gdbarch);
1711
        }
1712
 
1713
      /* Check if the S8 register was pushed on the stack.  */
1714
      if (xsregs > 6)
1715
        {
1716
          set_reg_offset (gdbarch, this_cache, 30, sp + offset);
1717
          offset -= mips_abi_regsize (gdbarch);
1718
          xsregs--;
1719
        }
1720
      /* Check if S2-S7 were pushed on the stack.  */
1721
      for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--)
1722
        {
1723
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1724
          offset -= mips_abi_regsize (gdbarch);
1725
        }
1726
 
1727
      /* Check if the S1 register was pushed on the stack.  */
1728
      if (save_inst & 0x10)
1729
        {
1730
          set_reg_offset (gdbarch, this_cache, 17, sp + offset);
1731
          offset -= mips_abi_regsize (gdbarch);
1732
        }
1733
      /* Check if the S0 register was pushed on the stack.  */
1734
      if (save_inst & 0x20)
1735
        {
1736
          set_reg_offset (gdbarch, this_cache, 16, sp + offset);
1737
          offset -= mips_abi_regsize (gdbarch);
1738
        }
1739
 
1740
      /* Check if A0-A3 were pushed on the stack.  */
1741
      for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--)
1742
        {
1743
          set_reg_offset (gdbarch, this_cache, reg, sp + offset);
1744
          offset -= mips_abi_regsize (gdbarch);
1745
        }
1746
    }
1747
 
1748
  if (this_cache != NULL)
1749
    {
1750
      this_cache->base =
1751
        (get_frame_register_signed (this_frame,
1752
                                    gdbarch_num_regs (gdbarch) + frame_reg)
1753
         + frame_offset - frame_adjust);
1754
      /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1755
         be able to get rid of the assignment below, evetually. But it's
1756
         still needed for now.  */
1757
      this_cache->saved_regs[gdbarch_num_regs (gdbarch)
1758
                             + mips_regnum (gdbarch)->pc]
1759
        = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
1760
    }
1761
 
1762
  /* If we didn't reach the end of the prologue when scanning the function
1763
     instructions, then set end_prologue_addr to the address of the
1764
     instruction immediately after the last one we scanned.  */
1765
  if (end_prologue_addr == 0)
1766
    end_prologue_addr = cur_pc;
1767
 
1768
  return end_prologue_addr;
1769
}
1770
 
1771
/* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1772
   Procedures that use the 32-bit instruction set are handled by the
1773
   mips_insn32 unwinder.  */
1774
 
1775
static struct mips_frame_cache *
1776
mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
1777
{
1778
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1779
  struct mips_frame_cache *cache;
1780
 
1781
  if ((*this_cache) != NULL)
1782
    return (*this_cache);
1783
  cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1784
  (*this_cache) = cache;
1785
  cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1786
 
1787
  /* Analyze the function prologue.  */
1788
  {
1789
    const CORE_ADDR pc = get_frame_address_in_block (this_frame);
1790
    CORE_ADDR start_addr;
1791
 
1792
    find_pc_partial_function (pc, NULL, &start_addr, NULL);
1793
    if (start_addr == 0)
1794
      start_addr = heuristic_proc_start (gdbarch, pc);
1795
    /* We can't analyze the prologue if we couldn't find the begining
1796
       of the function.  */
1797
    if (start_addr == 0)
1798
      return cache;
1799
 
1800
    mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
1801
  }
1802
 
1803
  /* gdbarch_sp_regnum contains the value and not the address.  */
1804
  trad_frame_set_value (cache->saved_regs,
1805
                        gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
1806
                        cache->base);
1807
 
1808
  return (*this_cache);
1809
}
1810
 
1811
static void
1812
mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
1813
                           struct frame_id *this_id)
1814
{
1815
  struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1816
                                                           this_cache);
1817
  /* This marks the outermost frame.  */
1818
  if (info->base == 0)
1819
    return;
1820
  (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
1821
}
1822
 
1823
static struct value *
1824
mips_insn16_frame_prev_register (struct frame_info *this_frame,
1825
                                 void **this_cache, int regnum)
1826
{
1827
  struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1828
                                                           this_cache);
1829
  return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1830
}
1831
 
1832
static int
1833
mips_insn16_frame_sniffer (const struct frame_unwind *self,
1834
                           struct frame_info *this_frame, void **this_cache)
1835
{
1836
  CORE_ADDR pc = get_frame_pc (this_frame);
1837
  if (mips_pc_is_mips16 (pc))
1838
    return 1;
1839
  return 0;
1840
}
1841
 
1842
static const struct frame_unwind mips_insn16_frame_unwind =
1843
{
1844
  NORMAL_FRAME,
1845
  mips_insn16_frame_this_id,
1846
  mips_insn16_frame_prev_register,
1847
  NULL,
1848
  mips_insn16_frame_sniffer
1849
};
1850
 
1851
static CORE_ADDR
1852
mips_insn16_frame_base_address (struct frame_info *this_frame,
1853
                                void **this_cache)
1854
{
1855
  struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
1856
                                                           this_cache);
1857
  return info->base;
1858
}
1859
 
1860
static const struct frame_base mips_insn16_frame_base =
1861
{
1862
  &mips_insn16_frame_unwind,
1863
  mips_insn16_frame_base_address,
1864
  mips_insn16_frame_base_address,
1865
  mips_insn16_frame_base_address
1866
};
1867
 
1868
static const struct frame_base *
1869
mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
1870
{
1871
  CORE_ADDR pc = get_frame_pc (this_frame);
1872
  if (mips_pc_is_mips16 (pc))
1873
    return &mips_insn16_frame_base;
1874
  else
1875
    return NULL;
1876
}
1877
 
1878
/* Mark all the registers as unset in the saved_regs array
1879
   of THIS_CACHE.  Do nothing if THIS_CACHE is null.  */
1880
 
1881
static void
1882
reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache)
1883
{
1884
  if (this_cache == NULL || this_cache->saved_regs == NULL)
1885
    return;
1886
 
1887
  {
1888
    const int num_regs = gdbarch_num_regs (gdbarch);
1889
    int i;
1890
 
1891
    for (i = 0; i < num_regs; i++)
1892
      {
1893
        this_cache->saved_regs[i].addr = -1;
1894
      }
1895
  }
1896
}
1897
 
1898
/* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1899
   the associated FRAME_CACHE if not null.
1900
   Return the address of the first instruction past the prologue.  */
1901
 
1902
static CORE_ADDR
1903
mips32_scan_prologue (struct gdbarch *gdbarch,
1904
                      CORE_ADDR start_pc, CORE_ADDR limit_pc,
1905
                      struct frame_info *this_frame,
1906
                      struct mips_frame_cache *this_cache)
1907
{
1908
  CORE_ADDR cur_pc;
1909
  CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1910
  CORE_ADDR sp;
1911
  long frame_offset;
1912
  int  frame_reg = MIPS_SP_REGNUM;
1913
 
1914
  CORE_ADDR end_prologue_addr = 0;
1915
  int seen_sp_adjust = 0;
1916
  int load_immediate_bytes = 0;
1917
  int in_delay_slot = 0;
1918
  int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8);
1919
 
1920
  /* Can be called when there's no process, and hence when there's no
1921
     THIS_FRAME.  */
1922
  if (this_frame != NULL)
1923
    sp = get_frame_register_signed (this_frame,
1924
                                    gdbarch_num_regs (gdbarch)
1925
                                    + MIPS_SP_REGNUM);
1926
  else
1927
    sp = 0;
1928
 
1929
  if (limit_pc > start_pc + 200)
1930
    limit_pc = start_pc + 200;
1931
 
1932
restart:
1933
 
1934
  frame_offset = 0;
1935
  for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1936
    {
1937
      unsigned long inst, high_word, low_word;
1938
      int reg;
1939
 
1940
      /* Fetch the instruction.   */
1941
      inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc);
1942
 
1943
      /* Save some code by pre-extracting some useful fields.  */
1944
      high_word = (inst >> 16) & 0xffff;
1945
      low_word = inst & 0xffff;
1946
      reg = high_word & 0x1f;
1947
 
1948
      if (high_word == 0x27bd   /* addiu $sp,$sp,-i */
1949
          || high_word == 0x23bd        /* addi $sp,$sp,-i */
1950
          || high_word == 0x67bd)       /* daddiu $sp,$sp,-i */
1951
        {
1952
          if (low_word & 0x8000)        /* negative stack adjustment? */
1953
            frame_offset += 0x10000 - low_word;
1954
          else
1955
            /* Exit loop if a positive stack adjustment is found, which
1956
               usually means that the stack cleanup code in the function
1957
               epilogue is reached.  */
1958
            break;
1959
          seen_sp_adjust = 1;
1960
        }
1961
      else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1962
               && !regsize_is_64_bits)
1963
        {
1964
          set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
1965
        }
1966
      else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1967
               && regsize_is_64_bits)
1968
        {
1969
          /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra.  */
1970
          set_reg_offset (gdbarch, this_cache, reg, sp + low_word);
1971
        }
1972
      else if (high_word == 0x27be)     /* addiu $30,$sp,size */
1973
        {
1974
          /* Old gcc frame, r30 is virtual frame pointer.  */
1975
          if ((long) low_word != frame_offset)
1976
            frame_addr = sp + low_word;
1977
          else if (this_frame && frame_reg == MIPS_SP_REGNUM)
1978
            {
1979
              unsigned alloca_adjust;
1980
 
1981
              frame_reg = 30;
1982
              frame_addr = get_frame_register_signed
1983
                (this_frame, gdbarch_num_regs (gdbarch) + 30);
1984
 
1985
              alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1986
              if (alloca_adjust > 0)
1987
                {
1988
                  /* FP > SP + frame_size. This may be because of
1989
                     an alloca or somethings similar.  Fix sp to
1990
                     "pre-alloca" value, and try again.  */
1991
                  sp += alloca_adjust;
1992
                  /* Need to reset the status of all registers.  Otherwise,
1993
                     we will hit a guard that prevents the new address
1994
                     for each register to be recomputed during the second
1995
                     pass.  */
1996
                  reset_saved_regs (gdbarch, this_cache);
1997
                  goto restart;
1998
                }
1999
            }
2000
        }
2001
      /* move $30,$sp.  With different versions of gas this will be either
2002
         `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2003
         Accept any one of these.  */
2004
      else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2005
        {
2006
          /* New gcc frame, virtual frame pointer is at r30 + frame_size.  */
2007
          if (this_frame && frame_reg == MIPS_SP_REGNUM)
2008
            {
2009
              unsigned alloca_adjust;
2010
 
2011
              frame_reg = 30;
2012
              frame_addr = get_frame_register_signed
2013
                (this_frame, gdbarch_num_regs (gdbarch) + 30);
2014
 
2015
              alloca_adjust = (unsigned) (frame_addr - sp);
2016
              if (alloca_adjust > 0)
2017
                {
2018
                  /* FP > SP + frame_size. This may be because of
2019
                     an alloca or somethings similar.  Fix sp to
2020
                     "pre-alloca" value, and try again.  */
2021
                  sp = frame_addr;
2022
                  /* Need to reset the status of all registers.  Otherwise,
2023
                     we will hit a guard that prevents the new address
2024
                     for each register to be recomputed during the second
2025
                     pass.  */
2026
                  reset_saved_regs (gdbarch, this_cache);
2027
                  goto restart;
2028
                }
2029
            }
2030
        }
2031
      else if ((high_word & 0xFFE0) == 0xafc0   /* sw reg,offset($30) */
2032
               && !regsize_is_64_bits)
2033
        {
2034
          set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word);
2035
        }
2036
      else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2037
               || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2038
               || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2039
               || high_word == 0x3c1c /* lui $gp,n */
2040
               || high_word == 0x279c /* addiu $gp,$gp,n */
2041
               || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2042
               || inst == 0x033ce021 /* addu $gp,$t9,$gp */
2043
              )
2044
       {
2045
         /* These instructions are part of the prologue, but we don't
2046
            need to do anything special to handle them.  */
2047
       }
2048
      /* The instructions below load $at or $t0 with an immediate
2049
         value in preparation for a stack adjustment via
2050
         subu $sp,$sp,[$at,$t0]. These instructions could also
2051
         initialize a local variable, so we accept them only before
2052
         a stack adjustment instruction was seen.  */
2053
      else if (!seen_sp_adjust
2054
               && (high_word == 0x3c01 /* lui $at,n */
2055
                   || high_word == 0x3c08 /* lui $t0,n */
2056
                   || high_word == 0x3421 /* ori $at,$at,n */
2057
                   || high_word == 0x3508 /* ori $t0,$t0,n */
2058
                   || high_word == 0x3401 /* ori $at,$zero,n */
2059
                   || high_word == 0x3408 /* ori $t0,$zero,n */
2060
                  ))
2061
       {
2062
          load_immediate_bytes += MIPS_INSN32_SIZE;             /* FIXME!  */
2063
       }
2064
      else
2065
       {
2066
         /* This instruction is not an instruction typically found
2067
            in a prologue, so we must have reached the end of the
2068
            prologue.  */
2069
         /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2070
            loop now?  Why would we need to continue scanning the function
2071
            instructions?  */
2072
         if (end_prologue_addr == 0)
2073
           end_prologue_addr = cur_pc;
2074
 
2075
         /* Check for branches and jumps.  For now, only jump to
2076
            register are caught (i.e. returns).  */
2077
         if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8)
2078
           in_delay_slot = 1;
2079
       }
2080
 
2081
      /* If the previous instruction was a jump, we must have reached
2082
         the end of the prologue by now.  Stop scanning so that we do
2083
         not go past the function return.  */
2084
      if (in_delay_slot)
2085
        break;
2086
    }
2087
 
2088
  if (this_cache != NULL)
2089
    {
2090
      this_cache->base =
2091
        (get_frame_register_signed (this_frame,
2092
                                    gdbarch_num_regs (gdbarch) + frame_reg)
2093
         + frame_offset);
2094
      /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2095
         this assignment below, eventually.  But it's still needed
2096
         for now.  */
2097
      this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2098
                             + mips_regnum (gdbarch)->pc]
2099
        = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
2100
                                 + MIPS_RA_REGNUM];
2101
    }
2102
 
2103
  /* If we didn't reach the end of the prologue when scanning the function
2104
     instructions, then set end_prologue_addr to the address of the
2105
     instruction immediately after the last one we scanned.  */
2106
  /* brobecker/2004-10-10: I don't think this would ever happen, but
2107
     we may as well be careful and do our best if we have a null
2108
     end_prologue_addr.  */
2109
  if (end_prologue_addr == 0)
2110
    end_prologue_addr = cur_pc;
2111
 
2112
  /* In a frameless function, we might have incorrectly
2113
     skipped some load immediate instructions. Undo the skipping
2114
     if the load immediate was not followed by a stack adjustment.  */
2115
  if (load_immediate_bytes && !seen_sp_adjust)
2116
    end_prologue_addr -= load_immediate_bytes;
2117
 
2118
  return end_prologue_addr;
2119
}
2120
 
2121
/* Heuristic unwinder for procedures using 32-bit instructions (covers
2122
   both 32-bit and 64-bit MIPS ISAs).  Procedures using 16-bit
2123
   instructions (a.k.a. MIPS16) are handled by the mips_insn16
2124
   unwinder.  */
2125
 
2126
static struct mips_frame_cache *
2127
mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
2128
{
2129
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2130
  struct mips_frame_cache *cache;
2131
 
2132
  if ((*this_cache) != NULL)
2133
    return (*this_cache);
2134
 
2135
  cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
2136
  (*this_cache) = cache;
2137
  cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2138
 
2139
  /* Analyze the function prologue.  */
2140
  {
2141
    const CORE_ADDR pc = get_frame_address_in_block (this_frame);
2142
    CORE_ADDR start_addr;
2143
 
2144
    find_pc_partial_function (pc, NULL, &start_addr, NULL);
2145
    if (start_addr == 0)
2146
      start_addr = heuristic_proc_start (gdbarch, pc);
2147
    /* We can't analyze the prologue if we couldn't find the begining
2148
       of the function.  */
2149
    if (start_addr == 0)
2150
      return cache;
2151
 
2152
    mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache);
2153
  }
2154
 
2155
  /* gdbarch_sp_regnum contains the value and not the address.  */
2156
  trad_frame_set_value (cache->saved_regs,
2157
                        gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
2158
                        cache->base);
2159
 
2160
  return (*this_cache);
2161
}
2162
 
2163
static void
2164
mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
2165
                           struct frame_id *this_id)
2166
{
2167
  struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2168
                                                           this_cache);
2169
  /* This marks the outermost frame.  */
2170
  if (info->base == 0)
2171
    return;
2172
  (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2173
}
2174
 
2175
static struct value *
2176
mips_insn32_frame_prev_register (struct frame_info *this_frame,
2177
                                 void **this_cache, int regnum)
2178
{
2179
  struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2180
                                                           this_cache);
2181
  return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2182
}
2183
 
2184
static int
2185
mips_insn32_frame_sniffer (const struct frame_unwind *self,
2186
                           struct frame_info *this_frame, void **this_cache)
2187
{
2188
  CORE_ADDR pc = get_frame_pc (this_frame);
2189
  if (! mips_pc_is_mips16 (pc))
2190
    return 1;
2191
  return 0;
2192
}
2193
 
2194
static const struct frame_unwind mips_insn32_frame_unwind =
2195
{
2196
  NORMAL_FRAME,
2197
  mips_insn32_frame_this_id,
2198
  mips_insn32_frame_prev_register,
2199
  NULL,
2200
  mips_insn32_frame_sniffer
2201
};
2202
 
2203
static CORE_ADDR
2204
mips_insn32_frame_base_address (struct frame_info *this_frame,
2205
                                void **this_cache)
2206
{
2207
  struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
2208
                                                           this_cache);
2209
  return info->base;
2210
}
2211
 
2212
static const struct frame_base mips_insn32_frame_base =
2213
{
2214
  &mips_insn32_frame_unwind,
2215
  mips_insn32_frame_base_address,
2216
  mips_insn32_frame_base_address,
2217
  mips_insn32_frame_base_address
2218
};
2219
 
2220
static const struct frame_base *
2221
mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
2222
{
2223
  CORE_ADDR pc = get_frame_pc (this_frame);
2224
  if (! mips_pc_is_mips16 (pc))
2225
    return &mips_insn32_frame_base;
2226
  else
2227
    return NULL;
2228
}
2229
 
2230
static struct trad_frame_cache *
2231
mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2232
{
2233
  CORE_ADDR pc;
2234
  CORE_ADDR start_addr;
2235
  CORE_ADDR stack_addr;
2236
  struct trad_frame_cache *this_trad_cache;
2237
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2238
  int num_regs = gdbarch_num_regs (gdbarch);
2239
 
2240
  if ((*this_cache) != NULL)
2241
    return (*this_cache);
2242
  this_trad_cache = trad_frame_cache_zalloc (this_frame);
2243
  (*this_cache) = this_trad_cache;
2244
 
2245
  /* The return address is in the link register.  */
2246
  trad_frame_set_reg_realreg (this_trad_cache,
2247
                              gdbarch_pc_regnum (gdbarch),
2248
                              num_regs + MIPS_RA_REGNUM);
2249
 
2250
  /* Frame ID, since it's a frameless / stackless function, no stack
2251
     space is allocated and SP on entry is the current SP.  */
2252
  pc = get_frame_pc (this_frame);
2253
  find_pc_partial_function (pc, NULL, &start_addr, NULL);
2254
  stack_addr = get_frame_register_signed (this_frame,
2255
                                          num_regs + MIPS_SP_REGNUM);
2256
  trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2257
 
2258
  /* Assume that the frame's base is the same as the
2259
     stack-pointer.  */
2260
  trad_frame_set_this_base (this_trad_cache, stack_addr);
2261
 
2262
  return this_trad_cache;
2263
}
2264
 
2265
static void
2266
mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2267
                         struct frame_id *this_id)
2268
{
2269
  struct trad_frame_cache *this_trad_cache
2270
    = mips_stub_frame_cache (this_frame, this_cache);
2271
  trad_frame_get_id (this_trad_cache, this_id);
2272
}
2273
 
2274
static struct value *
2275
mips_stub_frame_prev_register (struct frame_info *this_frame,
2276
                               void **this_cache, int regnum)
2277
{
2278
  struct trad_frame_cache *this_trad_cache
2279
    = mips_stub_frame_cache (this_frame, this_cache);
2280
  return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2281
}
2282
 
2283
static int
2284
mips_stub_frame_sniffer (const struct frame_unwind *self,
2285
                         struct frame_info *this_frame, void **this_cache)
2286
{
2287
  gdb_byte dummy[4];
2288
  struct obj_section *s;
2289
  CORE_ADDR pc = get_frame_address_in_block (this_frame);
2290
  struct minimal_symbol *msym;
2291
 
2292
  /* Use the stub unwinder for unreadable code.  */
2293
  if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2294
    return 1;
2295
 
2296
  if (in_plt_section (pc, NULL))
2297
    return 1;
2298
 
2299
  /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs.  */
2300
  s = find_pc_section (pc);
2301
 
2302
  if (s != NULL
2303
      && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2304
                 ".MIPS.stubs") == 0)
2305
    return 1;
2306
 
2307
  /* Calling a PIC function from a non-PIC function passes through a
2308
     stub.  The stub for foo is named ".pic.foo".  */
2309
  msym = lookup_minimal_symbol_by_pc (pc);
2310
  if (msym != NULL
2311
      && SYMBOL_LINKAGE_NAME (msym) != NULL
2312
      && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0)
2313
    return 1;
2314
 
2315
  return 0;
2316
}
2317
 
2318
static const struct frame_unwind mips_stub_frame_unwind =
2319
{
2320
  NORMAL_FRAME,
2321
  mips_stub_frame_this_id,
2322
  mips_stub_frame_prev_register,
2323
  NULL,
2324
  mips_stub_frame_sniffer
2325
};
2326
 
2327
static CORE_ADDR
2328
mips_stub_frame_base_address (struct frame_info *this_frame,
2329
                              void **this_cache)
2330
{
2331
  struct trad_frame_cache *this_trad_cache
2332
    = mips_stub_frame_cache (this_frame, this_cache);
2333
  return trad_frame_get_this_base (this_trad_cache);
2334
}
2335
 
2336
static const struct frame_base mips_stub_frame_base =
2337
{
2338
  &mips_stub_frame_unwind,
2339
  mips_stub_frame_base_address,
2340
  mips_stub_frame_base_address,
2341
  mips_stub_frame_base_address
2342
};
2343
 
2344
static const struct frame_base *
2345
mips_stub_frame_base_sniffer (struct frame_info *this_frame)
2346
{
2347
  if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
2348
    return &mips_stub_frame_base;
2349
  else
2350
    return NULL;
2351
}
2352
 
2353
/* mips_addr_bits_remove - remove useless address bits  */
2354
 
2355
static CORE_ADDR
2356
mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
2357
{
2358
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2359
  if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2360
    /* This hack is a work-around for existing boards using PMON, the
2361
       simulator, and any other 64-bit targets that doesn't have true
2362
       64-bit addressing.  On these targets, the upper 32 bits of
2363
       addresses are ignored by the hardware.  Thus, the PC or SP are
2364
       likely to have been sign extended to all 1s by instruction
2365
       sequences that load 32-bit addresses.  For example, a typical
2366
       piece of code that loads an address is this:
2367
 
2368
       lui $r2, <upper 16 bits>
2369
       ori $r2, <lower 16 bits>
2370
 
2371
       But the lui sign-extends the value such that the upper 32 bits
2372
       may be all 1s.  The workaround is simply to mask off these
2373
       bits.  In the future, gcc may be changed to support true 64-bit
2374
       addressing, and this masking will have to be disabled.  */
2375
    return addr &= 0xffffffffUL;
2376
  else
2377
    return addr;
2378
}
2379
 
2380
/* Instructions used during single-stepping of atomic sequences.  */
2381
#define LL_OPCODE 0x30
2382
#define LLD_OPCODE 0x34
2383
#define SC_OPCODE 0x38
2384
#define SCD_OPCODE 0x3c
2385
 
2386
/* Checks for an atomic sequence of instructions beginning with a LL/LLD
2387
   instruction and ending with a SC/SCD instruction.  If such a sequence
2388
   is found, attempt to step through it.  A breakpoint is placed at the end of
2389
   the sequence.  */
2390
 
2391
static int
2392
deal_with_atomic_sequence (struct gdbarch *gdbarch,
2393
                           struct address_space *aspace, CORE_ADDR pc)
2394
{
2395
  CORE_ADDR breaks[2] = {-1, -1};
2396
  CORE_ADDR loc = pc;
2397
  CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination.  */
2398
  unsigned long insn;
2399
  int insn_count;
2400
  int index;
2401
  int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */
2402
  const int atomic_sequence_length = 16; /* Instruction sequence length.  */
2403
 
2404
  if (pc & 0x01)
2405
    return 0;
2406
 
2407
  insn = mips_fetch_instruction (gdbarch, loc);
2408
  /* Assume all atomic sequences start with a ll/lld instruction.  */
2409
  if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
2410
    return 0;
2411
 
2412
  /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2413
     instructions.  */
2414
  for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2415
    {
2416
      int is_branch = 0;
2417
      loc += MIPS_INSN32_SIZE;
2418
      insn = mips_fetch_instruction (gdbarch, loc);
2419
 
2420
      /* Assume that there is at most one branch in the atomic
2421
         sequence.  If a branch is found, put a breakpoint in its
2422
         destination address.  */
2423
      switch (itype_op (insn))
2424
        {
2425
        case 0: /* SPECIAL */
2426
          if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
2427
            return 0; /* fallback to the standard single-step code. */
2428
          break;
2429
        case 1: /* REGIMM */
2430
          is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */
2431
          break;
2432
        case 2: /* J */
2433
        case 3: /* JAL */
2434
          return 0; /* fallback to the standard single-step code. */
2435
        case 4: /* BEQ */
2436
        case 5: /* BNE */
2437
        case 6: /* BLEZ */
2438
        case 7: /* BGTZ */
2439
        case 20: /* BEQL */
2440
        case 21: /* BNEL */
2441
        case 22: /* BLEZL */
2442
        case 23: /* BGTTL */
2443
          is_branch = 1;
2444
          break;
2445
        case 17: /* COP1 */
2446
        case 18: /* COP2 */
2447
        case 19: /* COP3 */
2448
          is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2449
          break;
2450
        }
2451
      if (is_branch)
2452
        {
2453
          branch_bp = loc + mips32_relative_offset (insn) + 4;
2454
          if (last_breakpoint >= 1)
2455
            return 0; /* More than one branch found, fallback to the
2456
                         standard single-step code.  */
2457
          breaks[1] = branch_bp;
2458
          last_breakpoint++;
2459
        }
2460
 
2461
      if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE)
2462
        break;
2463
    }
2464
 
2465
  /* Assume that the atomic sequence ends with a sc/scd instruction.  */
2466
  if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
2467
    return 0;
2468
 
2469
  loc += MIPS_INSN32_SIZE;
2470
 
2471
  /* Insert a breakpoint right after the end of the atomic sequence.  */
2472
  breaks[0] = loc;
2473
 
2474
  /* Check for duplicated breakpoints.  Check also for a breakpoint
2475
     placed (branch instruction's destination) in the atomic sequence */
2476
  if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
2477
    last_breakpoint = 0;
2478
 
2479
  /* Effectively inserts the breakpoints.  */
2480
  for (index = 0; index <= last_breakpoint; index++)
2481
    insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
2482
 
2483
  return 1;
2484
}
2485
 
2486
/* mips_software_single_step() is called just before we want to resume
2487
   the inferior, if we want to single-step it but there is no hardware
2488
   or kernel single-step support (MIPS on GNU/Linux for example).  We find
2489
   the target of the coming instruction and breakpoint it.  */
2490
 
2491
int
2492
mips_software_single_step (struct frame_info *frame)
2493
{
2494
  struct gdbarch *gdbarch = get_frame_arch (frame);
2495
  struct address_space *aspace = get_frame_address_space (frame);
2496
  CORE_ADDR pc, next_pc;
2497
 
2498
  pc = get_frame_pc (frame);
2499
  if (deal_with_atomic_sequence (gdbarch, aspace, pc))
2500
    return 1;
2501
 
2502
  next_pc = mips_next_pc (frame, pc);
2503
 
2504
  insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2505
  return 1;
2506
}
2507
 
2508
/* Test whether the PC points to the return instruction at the
2509
   end of a function. */
2510
 
2511
static int
2512
mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc)
2513
{
2514
  if (mips_pc_is_mips16 (pc))
2515
    /* This mips16 case isn't necessarily reliable.  Sometimes the compiler
2516
       generates a "jr $ra"; other times it generates code to load
2517
       the return address from the stack to an accessible register (such
2518
       as $a3), then a "jr" using that register.  This second case
2519
       is almost impossible to distinguish from an indirect jump
2520
       used for switch statements, so we don't even try.  */
2521
    return mips_fetch_instruction (gdbarch, pc) == 0xe820;      /* jr $ra */
2522
  else
2523
    return mips_fetch_instruction (gdbarch, pc) == 0x3e00008;   /* jr $ra */
2524
}
2525
 
2526
 
2527
/* This fencepost looks highly suspicious to me.  Removing it also
2528
   seems suspicious as it could affect remote debugging across serial
2529
   lines.  */
2530
 
2531
static CORE_ADDR
2532
heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
2533
{
2534
  CORE_ADDR start_pc;
2535
  CORE_ADDR fence;
2536
  int instlen;
2537
  int seen_adjsp = 0;
2538
  struct inferior *inf;
2539
 
2540
  pc = gdbarch_addr_bits_remove (gdbarch, pc);
2541
  start_pc = pc;
2542
  fence = start_pc - heuristic_fence_post;
2543
  if (start_pc == 0)
2544
    return 0;
2545
 
2546
  if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2547
    fence = VM_MIN_ADDRESS;
2548
 
2549
  instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2550
 
2551
  inf = current_inferior ();
2552
 
2553
  /* search back for previous return */
2554
  for (start_pc -= instlen;; start_pc -= instlen)
2555
    if (start_pc < fence)
2556
      {
2557
        /* It's not clear to me why we reach this point when
2558
           stop_soon, but with this test, at least we
2559
           don't print out warnings for every child forked (eg, on
2560
           decstation).  22apr93 rich@cygnus.com.  */
2561
        if (inf->stop_soon == NO_STOP_QUIETLY)
2562
          {
2563
            static int blurb_printed = 0;
2564
 
2565
            warning (_("GDB can't find the start of the function at %s."),
2566
                     paddress (gdbarch, pc));
2567
 
2568
            if (!blurb_printed)
2569
              {
2570
                /* This actually happens frequently in embedded
2571
                   development, when you first connect to a board
2572
                   and your stack pointer and pc are nowhere in
2573
                   particular.  This message needs to give people
2574
                   in that situation enough information to
2575
                   determine that it's no big deal.  */
2576
                printf_filtered ("\n\
2577
    GDB is unable to find the start of the function at %s\n\
2578
and thus can't determine the size of that function's stack frame.\n\
2579
This means that GDB may be unable to access that stack frame, or\n\
2580
the frames below it.\n\
2581
    This problem is most likely caused by an invalid program counter or\n\
2582
stack pointer.\n\
2583
    However, if you think GDB should simply search farther back\n\
2584
from %s for code which looks like the beginning of a\n\
2585
function, you can increase the range of the search using the `set\n\
2586
heuristic-fence-post' command.\n",
2587
                        paddress (gdbarch, pc), paddress (gdbarch, pc));
2588
                blurb_printed = 1;
2589
              }
2590
          }
2591
 
2592
        return 0;
2593
      }
2594
    else if (mips_pc_is_mips16 (start_pc))
2595
      {
2596
        unsigned short inst;
2597
 
2598
        /* On MIPS16, any one of the following is likely to be the
2599
           start of a function:
2600
           extend save
2601
           save
2602
           entry
2603
           addiu sp,-n
2604
           daddiu sp,-n
2605
           extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'  */
2606
        inst = mips_fetch_instruction (gdbarch, start_pc);
2607
        if ((inst & 0xff80) == 0x6480)          /* save */
2608
          {
2609
            if (start_pc - instlen >= fence)
2610
              {
2611
                inst = mips_fetch_instruction (gdbarch, start_pc - instlen);
2612
                if ((inst & 0xf800) == 0xf000)  /* extend */
2613
                  start_pc -= instlen;
2614
              }
2615
            break;
2616
          }
2617
        else if (((inst & 0xf81f) == 0xe809
2618
                  && (inst & 0x700) != 0x700)   /* entry */
2619
                 || (inst & 0xff80) == 0x6380   /* addiu sp,-n */
2620
                 || (inst & 0xff80) == 0xfb80   /* daddiu sp,-n */
2621
                 || ((inst & 0xf810) == 0xf010 && seen_adjsp))  /* extend -n */
2622
          break;
2623
        else if ((inst & 0xff00) == 0x6300      /* addiu sp */
2624
                 || (inst & 0xff00) == 0xfb00)  /* daddiu sp */
2625
          seen_adjsp = 1;
2626
        else
2627
          seen_adjsp = 0;
2628
      }
2629
    else if (mips_about_to_return (gdbarch, start_pc))
2630
      {
2631
        /* Skip return and its delay slot.  */
2632
        start_pc += 2 * MIPS_INSN32_SIZE;
2633
        break;
2634
      }
2635
 
2636
  return start_pc;
2637
}
2638
 
2639
struct mips_objfile_private
2640
{
2641
  bfd_size_type size;
2642
  char *contents;
2643
};
2644
 
2645
/* According to the current ABI, should the type be passed in a
2646
   floating-point register (assuming that there is space)?  When there
2647
   is no FPU, FP are not even considered as possible candidates for
2648
   FP registers and, consequently this returns false - forces FP
2649
   arguments into integer registers. */
2650
 
2651
static int
2652
fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode,
2653
                   struct type *arg_type)
2654
{
2655
  return ((typecode == TYPE_CODE_FLT
2656
           || (MIPS_EABI (gdbarch)
2657
               && (typecode == TYPE_CODE_STRUCT
2658
                   || typecode == TYPE_CODE_UNION)
2659
               && TYPE_NFIELDS (arg_type) == 1
2660
               && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2661
               == TYPE_CODE_FLT))
2662
          && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
2663
}
2664
 
2665
/* On o32, argument passing in GPRs depends on the alignment of the type being
2666
   passed.  Return 1 if this type must be aligned to a doubleword boundary. */
2667
 
2668
static int
2669
mips_type_needs_double_align (struct type *type)
2670
{
2671
  enum type_code typecode = TYPE_CODE (type);
2672
 
2673
  if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2674
    return 1;
2675
  else if (typecode == TYPE_CODE_STRUCT)
2676
    {
2677
      if (TYPE_NFIELDS (type) < 1)
2678
        return 0;
2679
      return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2680
    }
2681
  else if (typecode == TYPE_CODE_UNION)
2682
    {
2683
      int i, n;
2684
 
2685
      n = TYPE_NFIELDS (type);
2686
      for (i = 0; i < n; i++)
2687
        if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2688
          return 1;
2689
      return 0;
2690
    }
2691
  return 0;
2692
}
2693
 
2694
/* Adjust the address downward (direction of stack growth) so that it
2695
   is correctly aligned for a new stack frame.  */
2696
static CORE_ADDR
2697
mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2698
{
2699
  return align_down (addr, 16);
2700
}
2701
 
2702
static CORE_ADDR
2703
mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2704
                           struct regcache *regcache, CORE_ADDR bp_addr,
2705
                           int nargs, struct value **args, CORE_ADDR sp,
2706
                           int struct_return, CORE_ADDR struct_addr)
2707
{
2708
  int argreg;
2709
  int float_argreg;
2710
  int argnum;
2711
  int len = 0;
2712
  int stack_offset = 0;
2713
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2714
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2715
  CORE_ADDR func_addr = find_function_addr (function, NULL);
2716
  int regsize = mips_abi_regsize (gdbarch);
2717
 
2718
  /* For shared libraries, "t9" needs to point at the function
2719
     address.  */
2720
  regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2721
 
2722
  /* Set the return address register to point to the entry point of
2723
     the program, where a breakpoint lies in wait.  */
2724
  regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2725
 
2726
  /* First ensure that the stack and structure return address (if any)
2727
     are properly aligned.  The stack has to be at least 64-bit
2728
     aligned even on 32-bit machines, because doubles must be 64-bit
2729
     aligned.  For n32 and n64, stack frames need to be 128-bit
2730
     aligned, so we round to this widest known alignment.  */
2731
 
2732
  sp = align_down (sp, 16);
2733
  struct_addr = align_down (struct_addr, 16);
2734
 
2735
  /* Now make space on the stack for the args.  We allocate more
2736
     than necessary for EABI, because the first few arguments are
2737
     passed in registers, but that's OK.  */
2738
  for (argnum = 0; argnum < nargs; argnum++)
2739
    len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize);
2740
  sp -= align_up (len, 16);
2741
 
2742
  if (mips_debug)
2743
    fprintf_unfiltered (gdb_stdlog,
2744
                        "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2745
                        paddress (gdbarch, sp), (long) align_up (len, 16));
2746
 
2747
  /* Initialize the integer and float register pointers.  */
2748
  argreg = MIPS_A0_REGNUM;
2749
  float_argreg = mips_fpa0_regnum (gdbarch);
2750
 
2751
  /* The struct_return pointer occupies the first parameter-passing reg.  */
2752
  if (struct_return)
2753
    {
2754
      if (mips_debug)
2755
        fprintf_unfiltered (gdb_stdlog,
2756
                            "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2757
                            argreg, paddress (gdbarch, struct_addr));
2758
      regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
2759
    }
2760
 
2761
  /* Now load as many as possible of the first arguments into
2762
     registers, and push the rest onto the stack.  Loop thru args
2763
     from first to last.  */
2764
  for (argnum = 0; argnum < nargs; argnum++)
2765
    {
2766
      const gdb_byte *val;
2767
      gdb_byte valbuf[MAX_REGISTER_SIZE];
2768
      struct value *arg = args[argnum];
2769
      struct type *arg_type = check_typedef (value_type (arg));
2770
      int len = TYPE_LENGTH (arg_type);
2771
      enum type_code typecode = TYPE_CODE (arg_type);
2772
 
2773
      if (mips_debug)
2774
        fprintf_unfiltered (gdb_stdlog,
2775
                            "mips_eabi_push_dummy_call: %d len=%d type=%d",
2776
                            argnum + 1, len, (int) typecode);
2777
 
2778
      /* The EABI passes structures that do not fit in a register by
2779
         reference.  */
2780
      if (len > regsize
2781
          && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2782
        {
2783
          store_unsigned_integer (valbuf, regsize, byte_order,
2784
                                  value_address (arg));
2785
          typecode = TYPE_CODE_PTR;
2786
          len = regsize;
2787
          val = valbuf;
2788
          if (mips_debug)
2789
            fprintf_unfiltered (gdb_stdlog, " push");
2790
        }
2791
      else
2792
        val = value_contents (arg);
2793
 
2794
      /* 32-bit ABIs always start floating point arguments in an
2795
         even-numbered floating point register.  Round the FP register
2796
         up before the check to see if there are any FP registers
2797
         left.  Non MIPS_EABI targets also pass the FP in the integer
2798
         registers so also round up normal registers.  */
2799
      if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
2800
        {
2801
          if ((float_argreg & 1))
2802
            float_argreg++;
2803
        }
2804
 
2805
      /* Floating point arguments passed in registers have to be
2806
         treated specially.  On 32-bit architectures, doubles
2807
         are passed in register pairs; the even register gets
2808
         the low word, and the odd register gets the high word.
2809
         On non-EABI processors, the first two floating point arguments are
2810
         also copied to general registers, because MIPS16 functions
2811
         don't use float registers for arguments.  This duplication of
2812
         arguments in general registers can't hurt non-MIPS16 functions
2813
         because those registers are normally skipped.  */
2814
      /* MIPS_EABI squeezes a struct that contains a single floating
2815
         point value into an FP register instead of pushing it onto the
2816
         stack.  */
2817
      if (fp_register_arg_p (gdbarch, typecode, arg_type)
2818
          && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
2819
        {
2820
          /* EABI32 will pass doubles in consecutive registers, even on
2821
             64-bit cores.  At one time, we used to check the size of
2822
             `float_argreg' to determine whether or not to pass doubles
2823
             in consecutive registers, but this is not sufficient for
2824
             making the ABI determination.  */
2825
          if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32)
2826
            {
2827
              int low_offset = gdbarch_byte_order (gdbarch)
2828
                               == BFD_ENDIAN_BIG ? 4 : 0;
2829
              unsigned long regval;
2830
 
2831
              /* Write the low word of the double to the even register(s).  */
2832
              regval = extract_unsigned_integer (val + low_offset,
2833
                                                 4, byte_order);
2834
              if (mips_debug)
2835
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2836
                                    float_argreg, phex (regval, 4));
2837
              regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2838
 
2839
              /* Write the high word of the double to the odd register(s).  */
2840
              regval = extract_unsigned_integer (val + 4 - low_offset,
2841
                                                 4, byte_order);
2842
              if (mips_debug)
2843
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2844
                                    float_argreg, phex (regval, 4));
2845
              regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2846
            }
2847
          else
2848
            {
2849
              /* This is a floating point value that fits entirely
2850
                 in a single register.  */
2851
              /* On 32 bit ABI's the float_argreg is further adjusted
2852
                 above to ensure that it is even register aligned.  */
2853
              LONGEST regval = extract_unsigned_integer (val, len, byte_order);
2854
              if (mips_debug)
2855
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2856
                                    float_argreg, phex (regval, len));
2857
              regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
2858
            }
2859
        }
2860
      else
2861
        {
2862
          /* Copy the argument to general registers or the stack in
2863
             register-sized pieces.  Large arguments are split between
2864
             registers and stack.  */
2865
          /* Note: structs whose size is not a multiple of regsize
2866
             are treated specially: Irix cc passes
2867
             them in registers where gcc sometimes puts them on the
2868
             stack.  For maximum compatibility, we will put them in
2869
             both places.  */
2870
          int odd_sized_struct = (len > regsize && len % regsize != 0);
2871
 
2872
          /* Note: Floating-point values that didn't fit into an FP
2873
             register are only written to memory.  */
2874
          while (len > 0)
2875
            {
2876
              /* Remember if the argument was written to the stack.  */
2877
              int stack_used_p = 0;
2878
              int partial_len = (len < regsize ? len : regsize);
2879
 
2880
              if (mips_debug)
2881
                fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2882
                                    partial_len);
2883
 
2884
              /* Write this portion of the argument to the stack.  */
2885
              if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
2886
                  || odd_sized_struct
2887
                  || fp_register_arg_p (gdbarch, typecode, arg_type))
2888
                {
2889
                  /* Should shorter than int integer values be
2890
                     promoted to int before being stored? */
2891
                  int longword_offset = 0;
2892
                  CORE_ADDR addr;
2893
                  stack_used_p = 1;
2894
                  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2895
                    {
2896
                      if (regsize == 8
2897
                          && (typecode == TYPE_CODE_INT
2898
                              || typecode == TYPE_CODE_PTR
2899
                              || typecode == TYPE_CODE_FLT) && len <= 4)
2900
                        longword_offset = regsize - len;
2901
                      else if ((typecode == TYPE_CODE_STRUCT
2902
                                || typecode == TYPE_CODE_UNION)
2903
                               && TYPE_LENGTH (arg_type) < regsize)
2904
                        longword_offset = regsize - len;
2905
                    }
2906
 
2907
                  if (mips_debug)
2908
                    {
2909
                      fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
2910
                                          paddress (gdbarch, stack_offset));
2911
                      fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
2912
                                          paddress (gdbarch, longword_offset));
2913
                    }
2914
 
2915
                  addr = sp + stack_offset + longword_offset;
2916
 
2917
                  if (mips_debug)
2918
                    {
2919
                      int i;
2920
                      fprintf_unfiltered (gdb_stdlog, " @%s ",
2921
                                          paddress (gdbarch, addr));
2922
                      for (i = 0; i < partial_len; i++)
2923
                        {
2924
                          fprintf_unfiltered (gdb_stdlog, "%02x",
2925
                                              val[i] & 0xff);
2926
                        }
2927
                    }
2928
                  write_memory (addr, val, partial_len);
2929
                }
2930
 
2931
              /* Note!!! This is NOT an else clause.  Odd sized
2932
                 structs may go thru BOTH paths.  Floating point
2933
                 arguments will not.  */
2934
              /* Write this portion of the argument to a general
2935
                 purpose register.  */
2936
              if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
2937
                  && !fp_register_arg_p (gdbarch, typecode, arg_type))
2938
                {
2939
                  LONGEST regval =
2940
                    extract_unsigned_integer (val, partial_len, byte_order);
2941
 
2942
                  if (mips_debug)
2943
                    fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2944
                                      argreg,
2945
                                      phex (regval, regsize));
2946
                  regcache_cooked_write_unsigned (regcache, argreg, regval);
2947
                  argreg++;
2948
                }
2949
 
2950
              len -= partial_len;
2951
              val += partial_len;
2952
 
2953
              /* Compute the the offset into the stack at which we
2954
                 will copy the next parameter.
2955
 
2956
                 In the new EABI (and the NABI32), the stack_offset
2957
                 only needs to be adjusted when it has been used.  */
2958
 
2959
              if (stack_used_p)
2960
                stack_offset += align_up (partial_len, regsize);
2961
            }
2962
        }
2963
      if (mips_debug)
2964
        fprintf_unfiltered (gdb_stdlog, "\n");
2965
    }
2966
 
2967
  regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2968
 
2969
  /* Return adjusted stack pointer.  */
2970
  return sp;
2971
}
2972
 
2973
/* Determine the return value convention being used.  */
2974
 
2975
static enum return_value_convention
2976
mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type,
2977
                        struct type *type, struct regcache *regcache,
2978
                        gdb_byte *readbuf, const gdb_byte *writebuf)
2979
{
2980
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2981
  int fp_return_type = 0;
2982
  int offset, regnum, xfer;
2983
 
2984
  if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2985
    return RETURN_VALUE_STRUCT_CONVENTION;
2986
 
2987
  /* Floating point type?  */
2988
  if (tdep->mips_fpu_type != MIPS_FPU_NONE)
2989
    {
2990
      if (TYPE_CODE (type) == TYPE_CODE_FLT)
2991
        fp_return_type = 1;
2992
      /* Structs with a single field of float type
2993
         are returned in a floating point register.  */
2994
      if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
2995
           || TYPE_CODE (type) == TYPE_CODE_UNION)
2996
          && TYPE_NFIELDS (type) == 1)
2997
        {
2998
          struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
2999
 
3000
          if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
3001
            fp_return_type = 1;
3002
        }
3003
    }
3004
 
3005
  if (fp_return_type)
3006
    {
3007
      /* A floating-point value belongs in the least significant part
3008
         of FP0/FP1.  */
3009
      if (mips_debug)
3010
        fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3011
      regnum = mips_regnum (gdbarch)->fp0;
3012
    }
3013
  else
3014
    {
3015
      /* An integer value goes in V0/V1.  */
3016
      if (mips_debug)
3017
        fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
3018
      regnum = MIPS_V0_REGNUM;
3019
    }
3020
  for (offset = 0;
3021
       offset < TYPE_LENGTH (type);
3022
       offset += mips_abi_regsize (gdbarch), regnum++)
3023
    {
3024
      xfer = mips_abi_regsize (gdbarch);
3025
      if (offset + xfer > TYPE_LENGTH (type))
3026
        xfer = TYPE_LENGTH (type) - offset;
3027
      mips_xfer_register (gdbarch, regcache,
3028
                          gdbarch_num_regs (gdbarch) + regnum, xfer,
3029
                          gdbarch_byte_order (gdbarch), readbuf, writebuf,
3030
                          offset);
3031
    }
3032
 
3033
  return RETURN_VALUE_REGISTER_CONVENTION;
3034
}
3035
 
3036
 
3037
/* N32/N64 ABI stuff.  */
3038
 
3039
/* Search for a naturally aligned double at OFFSET inside a struct
3040
   ARG_TYPE.  The N32 / N64 ABIs pass these in floating point
3041
   registers.  */
3042
 
3043
static int
3044
mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type,
3045
                            int offset)
3046
{
3047
  int i;
3048
 
3049
  if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
3050
    return 0;
3051
 
3052
  if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
3053
    return 0;
3054
 
3055
  if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
3056
    return 0;
3057
 
3058
  for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
3059
    {
3060
      int pos;
3061
      struct type *field_type;
3062
 
3063
      /* We're only looking at normal fields.  */
3064
      if (field_is_static (&TYPE_FIELD (arg_type, i))
3065
          || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
3066
        continue;
3067
 
3068
      /* If we have gone past the offset, there is no double to pass.  */
3069
      pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
3070
      if (pos > offset)
3071
        return 0;
3072
 
3073
      field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
3074
 
3075
      /* If this field is entirely before the requested offset, go
3076
         on to the next one.  */
3077
      if (pos + TYPE_LENGTH (field_type) <= offset)
3078
        continue;
3079
 
3080
      /* If this is our special aligned double, we can stop.  */
3081
      if (TYPE_CODE (field_type) == TYPE_CODE_FLT
3082
          && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
3083
        return 1;
3084
 
3085
      /* This field starts at or before the requested offset, and
3086
         overlaps it.  If it is a structure, recurse inwards.  */
3087
      return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos);
3088
    }
3089
 
3090
  return 0;
3091
}
3092
 
3093
static CORE_ADDR
3094
mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3095
                             struct regcache *regcache, CORE_ADDR bp_addr,
3096
                             int nargs, struct value **args, CORE_ADDR sp,
3097
                             int struct_return, CORE_ADDR struct_addr)
3098
{
3099
  int argreg;
3100
  int float_argreg;
3101
  int argnum;
3102
  int len = 0;
3103
  int stack_offset = 0;
3104
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3105
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3106
  CORE_ADDR func_addr = find_function_addr (function, NULL);
3107
 
3108
  /* For shared libraries, "t9" needs to point at the function
3109
     address.  */
3110
  regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3111
 
3112
  /* Set the return address register to point to the entry point of
3113
     the program, where a breakpoint lies in wait.  */
3114
  regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3115
 
3116
  /* First ensure that the stack and structure return address (if any)
3117
     are properly aligned.  The stack has to be at least 64-bit
3118
     aligned even on 32-bit machines, because doubles must be 64-bit
3119
     aligned.  For n32 and n64, stack frames need to be 128-bit
3120
     aligned, so we round to this widest known alignment.  */
3121
 
3122
  sp = align_down (sp, 16);
3123
  struct_addr = align_down (struct_addr, 16);
3124
 
3125
  /* Now make space on the stack for the args.  */
3126
  for (argnum = 0; argnum < nargs; argnum++)
3127
    len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
3128
  sp -= align_up (len, 16);
3129
 
3130
  if (mips_debug)
3131
    fprintf_unfiltered (gdb_stdlog,
3132
                        "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3133
                        paddress (gdbarch, sp), (long) align_up (len, 16));
3134
 
3135
  /* Initialize the integer and float register pointers.  */
3136
  argreg = MIPS_A0_REGNUM;
3137
  float_argreg = mips_fpa0_regnum (gdbarch);
3138
 
3139
  /* The struct_return pointer occupies the first parameter-passing reg.  */
3140
  if (struct_return)
3141
    {
3142
      if (mips_debug)
3143
        fprintf_unfiltered (gdb_stdlog,
3144
                            "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3145
                            argreg, paddress (gdbarch, struct_addr));
3146
      regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3147
    }
3148
 
3149
  /* Now load as many as possible of the first arguments into
3150
     registers, and push the rest onto the stack.  Loop thru args
3151
     from first to last.  */
3152
  for (argnum = 0; argnum < nargs; argnum++)
3153
    {
3154
      const gdb_byte *val;
3155
      struct value *arg = args[argnum];
3156
      struct type *arg_type = check_typedef (value_type (arg));
3157
      int len = TYPE_LENGTH (arg_type);
3158
      enum type_code typecode = TYPE_CODE (arg_type);
3159
 
3160
      if (mips_debug)
3161
        fprintf_unfiltered (gdb_stdlog,
3162
                            "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3163
                            argnum + 1, len, (int) typecode);
3164
 
3165
      val = value_contents (arg);
3166
 
3167
      /* A 128-bit long double value requires an even-odd pair of
3168
         floating-point registers.  */
3169
      if (len == 16
3170
          && fp_register_arg_p (gdbarch, typecode, arg_type)
3171
          && (float_argreg & 1))
3172
        {
3173
          float_argreg++;
3174
          argreg++;
3175
        }
3176
 
3177
      if (fp_register_arg_p (gdbarch, typecode, arg_type)
3178
          && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3179
        {
3180
          /* This is a floating point value that fits entirely
3181
             in a single register or a pair of registers.  */
3182
          int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3183
          LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
3184
          if (mips_debug)
3185
            fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3186
                                float_argreg, phex (regval, reglen));
3187
          regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3188
 
3189
          if (mips_debug)
3190
            fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3191
                                argreg, phex (regval, reglen));
3192
          regcache_cooked_write_unsigned (regcache, argreg, regval);
3193
          float_argreg++;
3194
          argreg++;
3195
          if (len == 16)
3196
            {
3197
              regval = extract_unsigned_integer (val + reglen,
3198
                                                 reglen, byte_order);
3199
              if (mips_debug)
3200
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3201
                                    float_argreg, phex (regval, reglen));
3202
              regcache_cooked_write_unsigned (regcache, float_argreg, regval);
3203
 
3204
              if (mips_debug)
3205
                fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3206
                                    argreg, phex (regval, reglen));
3207
              regcache_cooked_write_unsigned (regcache, argreg, regval);
3208
              float_argreg++;
3209
              argreg++;
3210
            }
3211
        }
3212
      else
3213
        {
3214
          /* Copy the argument to general registers or the stack in
3215
             register-sized pieces.  Large arguments are split between
3216
             registers and stack.  */
3217
          /* For N32/N64, structs, unions, or other composite types are
3218
             treated as a sequence of doublewords, and are passed in integer
3219
             or floating point registers as though they were simple scalar
3220
             parameters to the extent that they fit, with any excess on the
3221
             stack packed according to the normal memory layout of the
3222
             object.
3223
             The caller does not reserve space for the register arguments;
3224
             the callee is responsible for reserving it if required.  */
3225
          /* Note: Floating-point values that didn't fit into an FP
3226
             register are only written to memory.  */
3227
          while (len > 0)
3228
            {
3229
              /* Remember if the argument was written to the stack.  */
3230
              int stack_used_p = 0;
3231
              int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
3232
 
3233
              if (mips_debug)
3234
                fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3235
                                    partial_len);
3236
 
3237
              if (fp_register_arg_p (gdbarch, typecode, arg_type))
3238
                gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
3239
 
3240
              /* Write this portion of the argument to the stack.  */
3241
              if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
3242
                {
3243
                  /* Should shorter than int integer values be
3244
                     promoted to int before being stored? */
3245
                  int longword_offset = 0;
3246
                  CORE_ADDR addr;
3247
                  stack_used_p = 1;
3248
                  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
3249
                    {
3250
                      if ((typecode == TYPE_CODE_INT
3251
                           || typecode == TYPE_CODE_PTR)
3252
                          && len <= 4)
3253
                        longword_offset = MIPS64_REGSIZE - len;
3254
                    }
3255
 
3256
                  if (mips_debug)
3257
                    {
3258
                      fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3259
                                          paddress (gdbarch, stack_offset));
3260
                      fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3261
                                          paddress (gdbarch, longword_offset));
3262
                    }
3263
 
3264
                  addr = sp + stack_offset + longword_offset;
3265
 
3266
                  if (mips_debug)
3267
                    {
3268
                      int i;
3269
                      fprintf_unfiltered (gdb_stdlog, " @%s ",
3270
                                          paddress (gdbarch, addr));
3271
                      for (i = 0; i < partial_len; i++)
3272
                        {
3273
                          fprintf_unfiltered (gdb_stdlog, "%02x",
3274
                                              val[i] & 0xff);
3275
                        }
3276
                    }
3277
                  write_memory (addr, val, partial_len);
3278
                }
3279
 
3280
              /* Note!!! This is NOT an else clause.  Odd sized
3281
                 structs may go thru BOTH paths.  */
3282
              /* Write this portion of the argument to a general
3283
                 purpose register.  */
3284
              if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3285
                {
3286
                  LONGEST regval;
3287
 
3288
                  /* Sign extend pointers, 32-bit integers and signed
3289
                     16-bit and 8-bit integers; everything else is taken
3290
                     as is.  */
3291
 
3292
                  if ((partial_len == 4
3293
                       && (typecode == TYPE_CODE_PTR
3294
                           || typecode == TYPE_CODE_INT))
3295
                      || (partial_len < 4
3296
                          && typecode == TYPE_CODE_INT
3297
                          && !TYPE_UNSIGNED (arg_type)))
3298
                    regval = extract_signed_integer (val, partial_len,
3299
                                                     byte_order);
3300
                  else
3301
                    regval = extract_unsigned_integer (val, partial_len,
3302
                                                       byte_order);
3303
 
3304
                  /* A non-floating-point argument being passed in a
3305
                     general register.  If a struct or union, and if
3306
                     the remaining length is smaller than the register
3307
                     size, we have to adjust the register value on
3308
                     big endian targets.
3309
 
3310
                     It does not seem to be necessary to do the
3311
                     same for integral types.  */
3312
 
3313
                  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3314
                      && partial_len < MIPS64_REGSIZE
3315
                      && (typecode == TYPE_CODE_STRUCT
3316
                          || typecode == TYPE_CODE_UNION))
3317
                    regval <<= ((MIPS64_REGSIZE - partial_len)
3318
                                * TARGET_CHAR_BIT);
3319
 
3320
                  if (mips_debug)
3321
                    fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3322
                                      argreg,
3323
                                      phex (regval, MIPS64_REGSIZE));
3324
                  regcache_cooked_write_unsigned (regcache, argreg, regval);
3325
 
3326
                  if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
3327
                                                  TYPE_LENGTH (arg_type) - len))
3328
                    {
3329
                      if (mips_debug)
3330
                        fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
3331
                                          float_argreg,
3332
                                          phex (regval, MIPS64_REGSIZE));
3333
                      regcache_cooked_write_unsigned (regcache, float_argreg,
3334
                                                      regval);
3335
                    }
3336
 
3337
                  float_argreg++;
3338
                  argreg++;
3339
                }
3340
 
3341
              len -= partial_len;
3342
              val += partial_len;
3343
 
3344
              /* Compute the the offset into the stack at which we
3345
                 will copy the next parameter.
3346
 
3347
                 In N32 (N64?), the stack_offset only needs to be
3348
                 adjusted when it has been used.  */
3349
 
3350
              if (stack_used_p)
3351
                stack_offset += align_up (partial_len, MIPS64_REGSIZE);
3352
            }
3353
        }
3354
      if (mips_debug)
3355
        fprintf_unfiltered (gdb_stdlog, "\n");
3356
    }
3357
 
3358
  regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3359
 
3360
  /* Return adjusted stack pointer.  */
3361
  return sp;
3362
}
3363
 
3364
static enum return_value_convention
3365
mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3366
                          struct type *type, struct regcache *regcache,
3367
                          gdb_byte *readbuf, const gdb_byte *writebuf)
3368
{
3369
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3370
 
3371
  /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3372
 
3373
     Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3374
     if needed), as appropriate for the type.  Composite results (struct,
3375
     union, or array) are returned in $2/$f0 and $3/$f2 according to the
3376
     following rules:
3377
 
3378
     * A struct with only one or two floating point fields is returned in $f0
3379
     (and $f2 if necessary).  This is a generalization of the Fortran COMPLEX
3380
     case.
3381
 
3382
     * Any other composite results of at most 128 bits are returned in
3383
     $2 (first 64 bits) and $3 (remainder, if necessary).
3384
 
3385
     * Larger composite results are handled by converting the function to a
3386
     procedure with an implicit first parameter, which is a pointer to an area
3387
     reserved by the caller to receive the result.  [The o32-bit ABI requires
3388
     that all composite results be handled by conversion to implicit first
3389
     parameters.  The MIPS/SGI Fortran implementation has always made a
3390
     specific exception to return COMPLEX results in the floating point
3391
     registers.]  */
3392
 
3393
  if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
3394
    return RETURN_VALUE_STRUCT_CONVENTION;
3395
  else if (TYPE_CODE (type) == TYPE_CODE_FLT
3396
           && TYPE_LENGTH (type) == 16
3397
           && tdep->mips_fpu_type != MIPS_FPU_NONE)
3398
    {
3399
      /* A 128-bit floating-point value fills both $f0 and $f2.  The
3400
         two registers are used in the same as memory order, so the
3401
         eight bytes with the lower memory address are in $f0.  */
3402
      if (mips_debug)
3403
        fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
3404
      mips_xfer_register (gdbarch, regcache,
3405
                          gdbarch_num_regs (gdbarch)
3406
                          + mips_regnum (gdbarch)->fp0,
3407
                          8, gdbarch_byte_order (gdbarch),
3408
                          readbuf, writebuf, 0);
3409
      mips_xfer_register (gdbarch, regcache,
3410
                          gdbarch_num_regs (gdbarch)
3411
                          + mips_regnum (gdbarch)->fp0 + 2,
3412
                          8, gdbarch_byte_order (gdbarch),
3413
                          readbuf ? readbuf + 8 : readbuf,
3414
                          writebuf ? writebuf + 8 : writebuf, 0);
3415
      return RETURN_VALUE_REGISTER_CONVENTION;
3416
    }
3417
  else if (TYPE_CODE (type) == TYPE_CODE_FLT
3418
           && tdep->mips_fpu_type != MIPS_FPU_NONE)
3419
    {
3420
      /* A single or double floating-point value that fits in FP0.  */
3421
      if (mips_debug)
3422
        fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3423
      mips_xfer_register (gdbarch, regcache,
3424
                          gdbarch_num_regs (gdbarch)
3425
                          + mips_regnum (gdbarch)->fp0,
3426
                          TYPE_LENGTH (type),
3427
                          gdbarch_byte_order (gdbarch),
3428
                          readbuf, writebuf, 0);
3429
      return RETURN_VALUE_REGISTER_CONVENTION;
3430
    }
3431
  else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3432
           && TYPE_NFIELDS (type) <= 2
3433
           && TYPE_NFIELDS (type) >= 1
3434
           && ((TYPE_NFIELDS (type) == 1
3435
                && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3436
                    == TYPE_CODE_FLT))
3437
               || (TYPE_NFIELDS (type) == 2
3438
                   && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
3439
                       == TYPE_CODE_FLT)
3440
                   && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
3441
                       == TYPE_CODE_FLT))))
3442
    {
3443
      /* A struct that contains one or two floats.  Each value is part
3444
         in the least significant part of their floating point
3445
         register (or GPR, for soft float).  */
3446
      int regnum;
3447
      int field;
3448
      for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
3449
                                ? mips_regnum (gdbarch)->fp0
3450
                                : MIPS_V0_REGNUM);
3451
           field < TYPE_NFIELDS (type); field++, regnum += 2)
3452
        {
3453
          int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3454
                        / TARGET_CHAR_BIT);
3455
          if (mips_debug)
3456
            fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3457
                                offset);
3458
          if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
3459
            {
3460
              /* A 16-byte long double field goes in two consecutive
3461
                 registers.  */
3462
              mips_xfer_register (gdbarch, regcache,
3463
                                  gdbarch_num_regs (gdbarch) + regnum,
3464
                                  8,
3465
                                  gdbarch_byte_order (gdbarch),
3466
                                  readbuf, writebuf, offset);
3467
              mips_xfer_register (gdbarch, regcache,
3468
                                  gdbarch_num_regs (gdbarch) + regnum + 1,
3469
                                  8,
3470
                                  gdbarch_byte_order (gdbarch),
3471
                                  readbuf, writebuf, offset + 8);
3472
            }
3473
          else
3474
            mips_xfer_register (gdbarch, regcache,
3475
                                gdbarch_num_regs (gdbarch) + regnum,
3476
                                TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3477
                                gdbarch_byte_order (gdbarch),
3478
                                readbuf, writebuf, offset);
3479
        }
3480
      return RETURN_VALUE_REGISTER_CONVENTION;
3481
    }
3482
  else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3483
           || TYPE_CODE (type) == TYPE_CODE_UNION
3484
           || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3485
    {
3486
      /* A composite type.  Extract the left justified value,
3487
         regardless of the byte order.  I.e. DO NOT USE
3488
         mips_xfer_lower.  */
3489
      int offset;
3490
      int regnum;
3491
      for (offset = 0, regnum = MIPS_V0_REGNUM;
3492
           offset < TYPE_LENGTH (type);
3493
           offset += register_size (gdbarch, regnum), regnum++)
3494
        {
3495
          int xfer = register_size (gdbarch, regnum);
3496
          if (offset + xfer > TYPE_LENGTH (type))
3497
            xfer = TYPE_LENGTH (type) - offset;
3498
          if (mips_debug)
3499
            fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3500
                                offset, xfer, regnum);
3501
          mips_xfer_register (gdbarch, regcache,
3502
                              gdbarch_num_regs (gdbarch) + regnum,
3503
                              xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
3504
                              offset);
3505
        }
3506
      return RETURN_VALUE_REGISTER_CONVENTION;
3507
    }
3508
  else
3509
    {
3510
      /* A scalar extract each part but least-significant-byte
3511
         justified.  */
3512
      int offset;
3513
      int regnum;
3514
      for (offset = 0, regnum = MIPS_V0_REGNUM;
3515
           offset < TYPE_LENGTH (type);
3516
           offset += register_size (gdbarch, regnum), regnum++)
3517
        {
3518
          int xfer = register_size (gdbarch, regnum);
3519
          if (offset + xfer > TYPE_LENGTH (type))
3520
            xfer = TYPE_LENGTH (type) - offset;
3521
          if (mips_debug)
3522
            fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3523
                                offset, xfer, regnum);
3524
          mips_xfer_register (gdbarch, regcache,
3525
                              gdbarch_num_regs (gdbarch) + regnum,
3526
                              xfer, gdbarch_byte_order (gdbarch),
3527
                              readbuf, writebuf, offset);
3528
        }
3529
      return RETURN_VALUE_REGISTER_CONVENTION;
3530
    }
3531
}
3532
 
3533
/* O32 ABI stuff.  */
3534
 
3535
static CORE_ADDR
3536
mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3537
                          struct regcache *regcache, CORE_ADDR bp_addr,
3538
                          int nargs, struct value **args, CORE_ADDR sp,
3539
                          int struct_return, CORE_ADDR struct_addr)
3540
{
3541
  int argreg;
3542
  int float_argreg;
3543
  int argnum;
3544
  int len = 0;
3545
  int stack_offset = 0;
3546
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3547
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3548
  CORE_ADDR func_addr = find_function_addr (function, NULL);
3549
 
3550
  /* For shared libraries, "t9" needs to point at the function
3551
     address.  */
3552
  regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3553
 
3554
  /* Set the return address register to point to the entry point of
3555
     the program, where a breakpoint lies in wait.  */
3556
  regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3557
 
3558
  /* First ensure that the stack and structure return address (if any)
3559
     are properly aligned.  The stack has to be at least 64-bit
3560
     aligned even on 32-bit machines, because doubles must be 64-bit
3561
     aligned.  For n32 and n64, stack frames need to be 128-bit
3562
     aligned, so we round to this widest known alignment.  */
3563
 
3564
  sp = align_down (sp, 16);
3565
  struct_addr = align_down (struct_addr, 16);
3566
 
3567
  /* Now make space on the stack for the args.  */
3568
  for (argnum = 0; argnum < nargs; argnum++)
3569
    {
3570
      struct type *arg_type = check_typedef (value_type (args[argnum]));
3571
      int arglen = TYPE_LENGTH (arg_type);
3572
 
3573
      /* Align to double-word if necessary.  */
3574
      if (mips_type_needs_double_align (arg_type))
3575
        len = align_up (len, MIPS32_REGSIZE * 2);
3576
      /* Allocate space on the stack.  */
3577
      len += align_up (arglen, MIPS32_REGSIZE);
3578
    }
3579
  sp -= align_up (len, 16);
3580
 
3581
  if (mips_debug)
3582
    fprintf_unfiltered (gdb_stdlog,
3583
                        "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3584
                        paddress (gdbarch, sp), (long) align_up (len, 16));
3585
 
3586
  /* Initialize the integer and float register pointers.  */
3587
  argreg = MIPS_A0_REGNUM;
3588
  float_argreg = mips_fpa0_regnum (gdbarch);
3589
 
3590
  /* The struct_return pointer occupies the first parameter-passing reg.  */
3591
  if (struct_return)
3592
    {
3593
      if (mips_debug)
3594
        fprintf_unfiltered (gdb_stdlog,
3595
                            "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3596
                            argreg, paddress (gdbarch, struct_addr));
3597
      regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
3598
      stack_offset += MIPS32_REGSIZE;
3599
    }
3600
 
3601
  /* Now load as many as possible of the first arguments into
3602
     registers, and push the rest onto the stack.  Loop thru args
3603
     from first to last.  */
3604
  for (argnum = 0; argnum < nargs; argnum++)
3605
    {
3606
      const gdb_byte *val;
3607
      struct value *arg = args[argnum];
3608
      struct type *arg_type = check_typedef (value_type (arg));
3609
      int len = TYPE_LENGTH (arg_type);
3610
      enum type_code typecode = TYPE_CODE (arg_type);
3611
 
3612
      if (mips_debug)
3613
        fprintf_unfiltered (gdb_stdlog,
3614
                            "mips_o32_push_dummy_call: %d len=%d type=%d",
3615
                            argnum + 1, len, (int) typecode);
3616
 
3617
      val = value_contents (arg);
3618
 
3619
      /* 32-bit ABIs always start floating point arguments in an
3620
         even-numbered floating point register.  Round the FP register
3621
         up before the check to see if there are any FP registers
3622
         left.  O32/O64 targets also pass the FP in the integer
3623
         registers so also round up normal registers.  */
3624
      if (fp_register_arg_p (gdbarch, typecode, arg_type))
3625
        {
3626
          if ((float_argreg & 1))
3627
            float_argreg++;
3628
        }
3629
 
3630
      /* Floating point arguments passed in registers have to be
3631
         treated specially.  On 32-bit architectures, doubles
3632
         are passed in register pairs; the even register gets
3633
         the low word, and the odd register gets the high word.
3634
         On O32/O64, the first two floating point arguments are
3635
         also copied to general registers, because MIPS16 functions
3636
         don't use float registers for arguments.  This duplication of
3637
         arguments in general registers can't hurt non-MIPS16 functions
3638
         because those registers are normally skipped.  */
3639
 
3640
      if (fp_register_arg_p (gdbarch, typecode, arg_type)
3641
          && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
3642
        {
3643
          if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3644
            {
3645
              int low_offset = gdbarch_byte_order (gdbarch)
3646
                               == BFD_ENDIAN_BIG ? 4 : 0;
3647
              unsigned long regval;
3648
 
3649
              /* Write the low word of the double to the even register(s).  */
3650
              regval = extract_unsigned_integer (val + low_offset,
3651
                                                 4, byte_order);
3652
              if (mips_debug)
3653
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3654
                                    float_argreg, phex (regval, 4));
3655
              regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3656
              if (mips_debug)
3657
                fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3658
                                    argreg, phex (regval, 4));
3659
              regcache_cooked_write_unsigned (regcache, argreg++, regval);
3660
 
3661
              /* Write the high word of the double to the odd register(s).  */
3662
              regval = extract_unsigned_integer (val + 4 - low_offset,
3663
                                                 4, byte_order);
3664
              if (mips_debug)
3665
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3666
                                    float_argreg, phex (regval, 4));
3667
              regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3668
 
3669
              if (mips_debug)
3670
                fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3671
                                    argreg, phex (regval, 4));
3672
              regcache_cooked_write_unsigned (regcache, argreg++, regval);
3673
            }
3674
          else
3675
            {
3676
              /* This is a floating point value that fits entirely
3677
                 in a single register.  */
3678
              /* On 32 bit ABI's the float_argreg is further adjusted
3679
                 above to ensure that it is even register aligned.  */
3680
              LONGEST regval = extract_unsigned_integer (val, len, byte_order);
3681
              if (mips_debug)
3682
                fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3683
                                    float_argreg, phex (regval, len));
3684
              regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
3685
              /* Although two FP registers are reserved for each
3686
                 argument, only one corresponding integer register is
3687
                 reserved.  */
3688
              if (mips_debug)
3689
                fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3690
                                    argreg, phex (regval, len));
3691
              regcache_cooked_write_unsigned (regcache, argreg++, regval);
3692
            }
3693
          /* Reserve space for the FP register.  */
3694
          stack_offset += align_up (len, MIPS32_REGSIZE);
3695
        }
3696
      else
3697
        {
3698
          /* Copy the argument to general registers or the stack in
3699
             register-sized pieces.  Large arguments are split between
3700
             registers and stack.  */
3701
          /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3702
             are treated specially: Irix cc passes
3703
             them in registers where gcc sometimes puts them on the
3704
             stack.  For maximum compatibility, we will put them in
3705
             both places.  */
3706
          int odd_sized_struct = (len > MIPS32_REGSIZE
3707
                                  && len % MIPS32_REGSIZE != 0);
3708
          /* Structures should be aligned to eight bytes (even arg registers)
3709
             on MIPS_ABI_O32, if their first member has double precision.  */
3710
          if (mips_type_needs_double_align (arg_type))
3711
            {
3712
              if ((argreg & 1))
3713
                {
3714
                  argreg++;
3715
                  stack_offset += MIPS32_REGSIZE;
3716
                }
3717
            }
3718
          while (len > 0)
3719
            {
3720
              /* Remember if the argument was written to the stack.  */
3721
              int stack_used_p = 0;
3722
              int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
3723
 
3724
              if (mips_debug)
3725
                fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3726
                                    partial_len);
3727
 
3728
              /* Write this portion of the argument to the stack.  */
3729
              if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
3730
                  || odd_sized_struct)
3731
                {
3732
                  /* Should shorter than int integer values be
3733
                     promoted to int before being stored? */
3734
                  int longword_offset = 0;
3735
                  CORE_ADDR addr;
3736
                  stack_used_p = 1;
3737
 
3738
                  if (mips_debug)
3739
                    {
3740
                      fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
3741
                                          paddress (gdbarch, stack_offset));
3742
                      fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
3743
                                          paddress (gdbarch, longword_offset));
3744
                    }
3745
 
3746
                  addr = sp + stack_offset + longword_offset;
3747
 
3748
                  if (mips_debug)
3749
                    {
3750
                      int i;
3751
                      fprintf_unfiltered (gdb_stdlog, " @%s ",
3752
                                          paddress (gdbarch, addr));
3753
                      for (i = 0; i < partial_len; i++)
3754
                        {
3755
                          fprintf_unfiltered (gdb_stdlog, "%02x",
3756
                                              val[i] & 0xff);
3757
                        }
3758
                    }
3759
                  write_memory (addr, val, partial_len);
3760
                }
3761
 
3762
              /* Note!!! This is NOT an else clause.  Odd sized
3763
                 structs may go thru BOTH paths.  */
3764
              /* Write this portion of the argument to a general
3765
                 purpose register.  */
3766
              if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
3767
                {
3768
                  LONGEST regval = extract_signed_integer (val, partial_len,
3769
                                                           byte_order);
3770
                  /* Value may need to be sign extended, because
3771
                     mips_isa_regsize() != mips_abi_regsize().  */
3772
 
3773
                  /* A non-floating-point argument being passed in a
3774
                     general register.  If a struct or union, and if
3775
                     the remaining length is smaller than the register
3776
                     size, we have to adjust the register value on
3777
                     big endian targets.
3778
 
3779
                     It does not seem to be necessary to do the
3780
                     same for integral types.
3781
 
3782
                     Also don't do this adjustment on O64 binaries.
3783
 
3784
                     cagney/2001-07-23: gdb/179: Also, GCC, when
3785
                     outputting LE O32 with sizeof (struct) <
3786
                     mips_abi_regsize(), generates a left shift
3787
                     as part of storing the argument in a register
3788
                     (the left shift isn't generated when
3789
                     sizeof (struct) >= mips_abi_regsize()).  Since
3790
                     it is quite possible that this is GCC
3791
                     contradicting the LE/O32 ABI, GDB has not been
3792
                     adjusted to accommodate this.  Either someone
3793
                     needs to demonstrate that the LE/O32 ABI
3794
                     specifies such a left shift OR this new ABI gets
3795
                     identified as such and GDB gets tweaked
3796
                     accordingly.  */
3797
 
3798
                  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
3799
                      && partial_len < MIPS32_REGSIZE
3800
                      && (typecode == TYPE_CODE_STRUCT
3801
                          || typecode == TYPE_CODE_UNION))
3802
                    regval <<= ((MIPS32_REGSIZE - partial_len)
3803
                                * TARGET_CHAR_BIT);
3804
 
3805
                  if (mips_debug)
3806
                    fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3807
                                      argreg,
3808
                                      phex (regval, MIPS32_REGSIZE));
3809
                  regcache_cooked_write_unsigned (regcache, argreg, regval);
3810
                  argreg++;
3811
 
3812
                  /* Prevent subsequent floating point arguments from
3813
                     being passed in floating point registers.  */
3814
                  float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
3815
                }
3816
 
3817
              len -= partial_len;
3818
              val += partial_len;
3819
 
3820
              /* Compute the the offset into the stack at which we
3821
                 will copy the next parameter.
3822
 
3823
                 In older ABIs, the caller reserved space for
3824
                 registers that contained arguments.  This was loosely
3825
                 refered to as their "home".  Consequently, space is
3826
                 always allocated.  */
3827
 
3828
              stack_offset += align_up (partial_len, MIPS32_REGSIZE);
3829
            }
3830
        }
3831
      if (mips_debug)
3832
        fprintf_unfiltered (gdb_stdlog, "\n");
3833
    }
3834
 
3835
  regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3836
 
3837
  /* Return adjusted stack pointer.  */
3838
  return sp;
3839
}
3840
 
3841
static enum return_value_convention
3842
mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type,
3843
                       struct type *type, struct regcache *regcache,
3844
                       gdb_byte *readbuf, const gdb_byte *writebuf)
3845
{
3846
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3847
 
3848
  if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3849
      || TYPE_CODE (type) == TYPE_CODE_UNION
3850
      || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3851
    return RETURN_VALUE_STRUCT_CONVENTION;
3852
  else if (TYPE_CODE (type) == TYPE_CODE_FLT
3853
           && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3854
    {
3855
      /* A single-precision floating-point value.  It fits in the
3856
         least significant part of FP0.  */
3857
      if (mips_debug)
3858
        fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3859
      mips_xfer_register (gdbarch, regcache,
3860
                          gdbarch_num_regs (gdbarch)
3861
                            + mips_regnum (gdbarch)->fp0,
3862
                          TYPE_LENGTH (type),
3863
                          gdbarch_byte_order (gdbarch),
3864
                          readbuf, writebuf, 0);
3865
      return RETURN_VALUE_REGISTER_CONVENTION;
3866
    }
3867
  else if (TYPE_CODE (type) == TYPE_CODE_FLT
3868
           && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3869
    {
3870
      /* A double-precision floating-point value.  The most
3871
         significant part goes in FP1, and the least significant in
3872
         FP0.  */
3873
      if (mips_debug)
3874
        fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3875
      switch (gdbarch_byte_order (gdbarch))
3876
        {
3877
        case BFD_ENDIAN_LITTLE:
3878
          mips_xfer_register (gdbarch, regcache,
3879
                              gdbarch_num_regs (gdbarch)
3880
                                + mips_regnum (gdbarch)->fp0 +
3881
                              0, 4, gdbarch_byte_order (gdbarch),
3882
                              readbuf, writebuf, 0);
3883
          mips_xfer_register (gdbarch, regcache,
3884
                              gdbarch_num_regs (gdbarch)
3885
                                + mips_regnum (gdbarch)->fp0 + 1,
3886
                              4, gdbarch_byte_order (gdbarch),
3887
                              readbuf, writebuf, 4);
3888
          break;
3889
        case BFD_ENDIAN_BIG:
3890
          mips_xfer_register (gdbarch, regcache,
3891
                              gdbarch_num_regs (gdbarch)
3892
                                + mips_regnum (gdbarch)->fp0 + 1,
3893
                              4, gdbarch_byte_order (gdbarch),
3894
                              readbuf, writebuf, 0);
3895
          mips_xfer_register (gdbarch, regcache,
3896
                              gdbarch_num_regs (gdbarch)
3897
                                + mips_regnum (gdbarch)->fp0 + 0,
3898
                              4, gdbarch_byte_order (gdbarch),
3899
                              readbuf, writebuf, 4);
3900
          break;
3901
        default:
3902
          internal_error (__FILE__, __LINE__, _("bad switch"));
3903
        }
3904
      return RETURN_VALUE_REGISTER_CONVENTION;
3905
    }
3906
#if 0
3907
  else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3908
           && TYPE_NFIELDS (type) <= 2
3909
           && TYPE_NFIELDS (type) >= 1
3910
           && ((TYPE_NFIELDS (type) == 1
3911
                && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3912
                    == TYPE_CODE_FLT))
3913
               || (TYPE_NFIELDS (type) == 2
3914
                   && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3915
                       == TYPE_CODE_FLT)
3916
                   && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3917
                       == TYPE_CODE_FLT)))
3918
           && tdep->mips_fpu_type != MIPS_FPU_NONE)
3919
    {
3920
      /* A struct that contains one or two floats.  Each value is part
3921
         in the least significant part of their floating point
3922
         register..  */
3923
      gdb_byte reg[MAX_REGISTER_SIZE];
3924
      int regnum;
3925
      int field;
3926
      for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
3927
           field < TYPE_NFIELDS (type); field++, regnum += 2)
3928
        {
3929
          int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3930
                        / TARGET_CHAR_BIT);
3931
          if (mips_debug)
3932
            fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3933
                                offset);
3934
          mips_xfer_register (gdbarch, regcache,
3935
                              gdbarch_num_regs (gdbarch) + regnum,
3936
                              TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3937
                              gdbarch_byte_order (gdbarch),
3938
                              readbuf, writebuf, offset);
3939
        }
3940
      return RETURN_VALUE_REGISTER_CONVENTION;
3941
    }
3942
#endif
3943
#if 0
3944
  else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3945
           || TYPE_CODE (type) == TYPE_CODE_UNION)
3946
    {
3947
      /* A structure or union.  Extract the left justified value,
3948
         regardless of the byte order.  I.e. DO NOT USE
3949
         mips_xfer_lower.  */
3950
      int offset;
3951
      int regnum;
3952
      for (offset = 0, regnum = MIPS_V0_REGNUM;
3953
           offset < TYPE_LENGTH (type);
3954
           offset += register_size (gdbarch, regnum), regnum++)
3955
        {
3956
          int xfer = register_size (gdbarch, regnum);
3957
          if (offset + xfer > TYPE_LENGTH (type))
3958
            xfer = TYPE_LENGTH (type) - offset;
3959
          if (mips_debug)
3960
            fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3961
                                offset, xfer, regnum);
3962
          mips_xfer_register (gdbarch, regcache,
3963
                              gdbarch_num_regs (gdbarch) + regnum, xfer,
3964
                              BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3965
        }
3966
      return RETURN_VALUE_REGISTER_CONVENTION;
3967
    }
3968
#endif
3969
  else
3970
    {
3971
      /* A scalar extract each part but least-significant-byte
3972
         justified.  o32 thinks registers are 4 byte, regardless of
3973
         the ISA.  */
3974
      int offset;
3975
      int regnum;
3976
      for (offset = 0, regnum = MIPS_V0_REGNUM;
3977
           offset < TYPE_LENGTH (type);
3978
           offset += MIPS32_REGSIZE, regnum++)
3979
        {
3980
          int xfer = MIPS32_REGSIZE;
3981
          if (offset + xfer > TYPE_LENGTH (type))
3982
            xfer = TYPE_LENGTH (type) - offset;
3983
          if (mips_debug)
3984
            fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3985
                                offset, xfer, regnum);
3986
          mips_xfer_register (gdbarch, regcache,
3987
                              gdbarch_num_regs (gdbarch) + regnum, xfer,
3988
                              gdbarch_byte_order (gdbarch),
3989
                              readbuf, writebuf, offset);
3990
        }
3991
      return RETURN_VALUE_REGISTER_CONVENTION;
3992
    }
3993
}
3994
 
3995
/* O64 ABI.  This is a hacked up kind of 64-bit version of the o32
3996
   ABI.  */
3997
 
3998
static CORE_ADDR
3999
mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
4000
                          struct regcache *regcache, CORE_ADDR bp_addr,
4001
                          int nargs,
4002
                          struct value **args, CORE_ADDR sp,
4003
                          int struct_return, CORE_ADDR struct_addr)
4004
{
4005
  int argreg;
4006
  int float_argreg;
4007
  int argnum;
4008
  int len = 0;
4009
  int stack_offset = 0;
4010
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4011
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4012
  CORE_ADDR func_addr = find_function_addr (function, NULL);
4013
 
4014
  /* For shared libraries, "t9" needs to point at the function
4015
     address.  */
4016
  regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
4017
 
4018
  /* Set the return address register to point to the entry point of
4019
     the program, where a breakpoint lies in wait.  */
4020
  regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
4021
 
4022
  /* First ensure that the stack and structure return address (if any)
4023
     are properly aligned.  The stack has to be at least 64-bit
4024
     aligned even on 32-bit machines, because doubles must be 64-bit
4025
     aligned.  For n32 and n64, stack frames need to be 128-bit
4026
     aligned, so we round to this widest known alignment.  */
4027
 
4028
  sp = align_down (sp, 16);
4029
  struct_addr = align_down (struct_addr, 16);
4030
 
4031
  /* Now make space on the stack for the args.  */
4032
  for (argnum = 0; argnum < nargs; argnum++)
4033
    {
4034
      struct type *arg_type = check_typedef (value_type (args[argnum]));
4035
      int arglen = TYPE_LENGTH (arg_type);
4036
 
4037
      /* Allocate space on the stack.  */
4038
      len += align_up (arglen, MIPS64_REGSIZE);
4039
    }
4040
  sp -= align_up (len, 16);
4041
 
4042
  if (mips_debug)
4043
    fprintf_unfiltered (gdb_stdlog,
4044
                        "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4045
                        paddress (gdbarch, sp), (long) align_up (len, 16));
4046
 
4047
  /* Initialize the integer and float register pointers.  */
4048
  argreg = MIPS_A0_REGNUM;
4049
  float_argreg = mips_fpa0_regnum (gdbarch);
4050
 
4051
  /* The struct_return pointer occupies the first parameter-passing reg.  */
4052
  if (struct_return)
4053
    {
4054
      if (mips_debug)
4055
        fprintf_unfiltered (gdb_stdlog,
4056
                            "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4057
                            argreg, paddress (gdbarch, struct_addr));
4058
      regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
4059
      stack_offset += MIPS64_REGSIZE;
4060
    }
4061
 
4062
  /* Now load as many as possible of the first arguments into
4063
     registers, and push the rest onto the stack.  Loop thru args
4064
     from first to last.  */
4065
  for (argnum = 0; argnum < nargs; argnum++)
4066
    {
4067
      const gdb_byte *val;
4068
      struct value *arg = args[argnum];
4069
      struct type *arg_type = check_typedef (value_type (arg));
4070
      int len = TYPE_LENGTH (arg_type);
4071
      enum type_code typecode = TYPE_CODE (arg_type);
4072
 
4073
      if (mips_debug)
4074
        fprintf_unfiltered (gdb_stdlog,
4075
                            "mips_o64_push_dummy_call: %d len=%d type=%d",
4076
                            argnum + 1, len, (int) typecode);
4077
 
4078
      val = value_contents (arg);
4079
 
4080
      /* Floating point arguments passed in registers have to be
4081
         treated specially.  On 32-bit architectures, doubles
4082
         are passed in register pairs; the even register gets
4083
         the low word, and the odd register gets the high word.
4084
         On O32/O64, the first two floating point arguments are
4085
         also copied to general registers, because MIPS16 functions
4086
         don't use float registers for arguments.  This duplication of
4087
         arguments in general registers can't hurt non-MIPS16 functions
4088
         because those registers are normally skipped.  */
4089
 
4090
      if (fp_register_arg_p (gdbarch, typecode, arg_type)
4091
          && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
4092
        {
4093
          LONGEST regval = extract_unsigned_integer (val, len, byte_order);
4094
          if (mips_debug)
4095
            fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
4096
                                float_argreg, phex (regval, len));
4097
          regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
4098
          if (mips_debug)
4099
            fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
4100
                                argreg, phex (regval, len));
4101
          regcache_cooked_write_unsigned (regcache, argreg, regval);
4102
          argreg++;
4103
          /* Reserve space for the FP register.  */
4104
          stack_offset += align_up (len, MIPS64_REGSIZE);
4105
        }
4106
      else
4107
        {
4108
          /* Copy the argument to general registers or the stack in
4109
             register-sized pieces.  Large arguments are split between
4110
             registers and stack.  */
4111
          /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4112
             are treated specially: Irix cc passes them in registers
4113
             where gcc sometimes puts them on the stack.  For maximum
4114
             compatibility, we will put them in both places.  */
4115
          int odd_sized_struct = (len > MIPS64_REGSIZE
4116
                                  && len % MIPS64_REGSIZE != 0);
4117
          while (len > 0)
4118
            {
4119
              /* Remember if the argument was written to the stack.  */
4120
              int stack_used_p = 0;
4121
              int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
4122
 
4123
              if (mips_debug)
4124
                fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4125
                                    partial_len);
4126
 
4127
              /* Write this portion of the argument to the stack.  */
4128
              if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
4129
                  || odd_sized_struct)
4130
                {
4131
                  /* Should shorter than int integer values be
4132
                     promoted to int before being stored? */
4133
                  int longword_offset = 0;
4134
                  CORE_ADDR addr;
4135
                  stack_used_p = 1;
4136
                  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4137
                    {
4138
                      if ((typecode == TYPE_CODE_INT
4139
                           || typecode == TYPE_CODE_PTR
4140
                           || typecode == TYPE_CODE_FLT)
4141
                          && len <= 4)
4142
                        longword_offset = MIPS64_REGSIZE - len;
4143
                    }
4144
 
4145
                  if (mips_debug)
4146
                    {
4147
                      fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
4148
                                          paddress (gdbarch, stack_offset));
4149
                      fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
4150
                                          paddress (gdbarch, longword_offset));
4151
                    }
4152
 
4153
                  addr = sp + stack_offset + longword_offset;
4154
 
4155
                  if (mips_debug)
4156
                    {
4157
                      int i;
4158
                      fprintf_unfiltered (gdb_stdlog, " @%s ",
4159
                                          paddress (gdbarch, addr));
4160
                      for (i = 0; i < partial_len; i++)
4161
                        {
4162
                          fprintf_unfiltered (gdb_stdlog, "%02x",
4163
                                              val[i] & 0xff);
4164
                        }
4165
                    }
4166
                  write_memory (addr, val, partial_len);
4167
                }
4168
 
4169
              /* Note!!! This is NOT an else clause.  Odd sized
4170
                 structs may go thru BOTH paths.  */
4171
              /* Write this portion of the argument to a general
4172
                 purpose register.  */
4173
              if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
4174
                {
4175
                  LONGEST regval = extract_signed_integer (val, partial_len,
4176
                                                           byte_order);
4177
                  /* Value may need to be sign extended, because
4178
                     mips_isa_regsize() != mips_abi_regsize().  */
4179
 
4180
                  /* A non-floating-point argument being passed in a
4181
                     general register.  If a struct or union, and if
4182
                     the remaining length is smaller than the register
4183
                     size, we have to adjust the register value on
4184
                     big endian targets.
4185
 
4186
                     It does not seem to be necessary to do the
4187
                     same for integral types. */
4188
 
4189
                  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
4190
                      && partial_len < MIPS64_REGSIZE
4191
                      && (typecode == TYPE_CODE_STRUCT
4192
                          || typecode == TYPE_CODE_UNION))
4193
                    regval <<= ((MIPS64_REGSIZE - partial_len)
4194
                                * TARGET_CHAR_BIT);
4195
 
4196
                  if (mips_debug)
4197
                    fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4198
                                      argreg,
4199
                                      phex (regval, MIPS64_REGSIZE));
4200
                  regcache_cooked_write_unsigned (regcache, argreg, regval);
4201
                  argreg++;
4202
 
4203
                  /* Prevent subsequent floating point arguments from
4204
                     being passed in floating point registers.  */
4205
                  float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
4206
                }
4207
 
4208
              len -= partial_len;
4209
              val += partial_len;
4210
 
4211
              /* Compute the the offset into the stack at which we
4212
                 will copy the next parameter.
4213
 
4214
                 In older ABIs, the caller reserved space for
4215
                 registers that contained arguments.  This was loosely
4216
                 refered to as their "home".  Consequently, space is
4217
                 always allocated.  */
4218
 
4219
              stack_offset += align_up (partial_len, MIPS64_REGSIZE);
4220
            }
4221
        }
4222
      if (mips_debug)
4223
        fprintf_unfiltered (gdb_stdlog, "\n");
4224
    }
4225
 
4226
  regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
4227
 
4228
  /* Return adjusted stack pointer.  */
4229
  return sp;
4230
}
4231
 
4232
static enum return_value_convention
4233
mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type,
4234
                       struct type *type, struct regcache *regcache,
4235
                       gdb_byte *readbuf, const gdb_byte *writebuf)
4236
{
4237
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4238
 
4239
  if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4240
      || TYPE_CODE (type) == TYPE_CODE_UNION
4241
      || TYPE_CODE (type) == TYPE_CODE_ARRAY)
4242
    return RETURN_VALUE_STRUCT_CONVENTION;
4243
  else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
4244
    {
4245
      /* A floating-point value.  It fits in the least significant
4246
         part of FP0.  */
4247
      if (mips_debug)
4248
        fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4249
      mips_xfer_register (gdbarch, regcache,
4250
                          gdbarch_num_regs (gdbarch)
4251
                            + mips_regnum (gdbarch)->fp0,
4252
                          TYPE_LENGTH (type),
4253
                          gdbarch_byte_order (gdbarch),
4254
                          readbuf, writebuf, 0);
4255
      return RETURN_VALUE_REGISTER_CONVENTION;
4256
    }
4257
  else
4258
    {
4259
      /* A scalar extract each part but least-significant-byte
4260
         justified. */
4261
      int offset;
4262
      int regnum;
4263
      for (offset = 0, regnum = MIPS_V0_REGNUM;
4264
           offset < TYPE_LENGTH (type);
4265
           offset += MIPS64_REGSIZE, regnum++)
4266
        {
4267
          int xfer = MIPS64_REGSIZE;
4268
          if (offset + xfer > TYPE_LENGTH (type))
4269
            xfer = TYPE_LENGTH (type) - offset;
4270
          if (mips_debug)
4271
            fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4272
                                offset, xfer, regnum);
4273
          mips_xfer_register (gdbarch, regcache,
4274
                              gdbarch_num_regs (gdbarch) + regnum,
4275
                              xfer, gdbarch_byte_order (gdbarch),
4276
                              readbuf, writebuf, offset);
4277
        }
4278
      return RETURN_VALUE_REGISTER_CONVENTION;
4279
    }
4280
}
4281
 
4282
/* Floating point register management.
4283
 
4284
   Background: MIPS1 & 2 fp registers are 32 bits wide.  To support
4285
   64bit operations, these early MIPS cpus treat fp register pairs
4286
   (f0,f1) as a single register (d0).  Later MIPS cpu's have 64 bit fp
4287
   registers and offer a compatibility mode that emulates the MIPS2 fp
4288
   model.  When operating in MIPS2 fp compat mode, later cpu's split
4289
   double precision floats into two 32-bit chunks and store them in
4290
   consecutive fp regs.  To display 64-bit floats stored in this
4291
   fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4292
   Throw in user-configurable endianness and you have a real mess.
4293
 
4294
   The way this works is:
4295
     - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4296
       double-precision value will be split across two logical registers.
4297
       The lower-numbered logical register will hold the low-order bits,
4298
       regardless of the processor's endianness.
4299
     - If we are on a 64-bit processor, and we are looking for a
4300
       single-precision value, it will be in the low ordered bits
4301
       of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4302
       save slot in memory.
4303
     - If we are in 64-bit mode, everything is straightforward.
4304
 
4305
   Note that this code only deals with "live" registers at the top of the
4306
   stack.  We will attempt to deal with saved registers later, when
4307
   the raw/cooked register interface is in place. (We need a general
4308
   interface that can deal with dynamic saved register sizes -- fp
4309
   regs could be 32 bits wide in one frame and 64 on the frame above
4310
   and below).  */
4311
 
4312
/* Copy a 32-bit single-precision value from the current frame
4313
   into rare_buffer.  */
4314
 
4315
static void
4316
mips_read_fp_register_single (struct frame_info *frame, int regno,
4317
                              gdb_byte *rare_buffer)
4318
{
4319
  struct gdbarch *gdbarch = get_frame_arch (frame);
4320
  int raw_size = register_size (gdbarch, regno);
4321
  gdb_byte *raw_buffer = alloca (raw_size);
4322
 
4323
  if (!frame_register_read (frame, regno, raw_buffer))
4324
    error (_("can't read register %d (%s)"),
4325
           regno, gdbarch_register_name (gdbarch, regno));
4326
  if (raw_size == 8)
4327
    {
4328
      /* We have a 64-bit value for this register.  Find the low-order
4329
         32 bits.  */
4330
      int offset;
4331
 
4332
      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4333
        offset = 4;
4334
      else
4335
        offset = 0;
4336
 
4337
      memcpy (rare_buffer, raw_buffer + offset, 4);
4338
    }
4339
  else
4340
    {
4341
      memcpy (rare_buffer, raw_buffer, 4);
4342
    }
4343
}
4344
 
4345
/* Copy a 64-bit double-precision value from the current frame into
4346
   rare_buffer.  This may include getting half of it from the next
4347
   register.  */
4348
 
4349
static void
4350
mips_read_fp_register_double (struct frame_info *frame, int regno,
4351
                              gdb_byte *rare_buffer)
4352
{
4353
  struct gdbarch *gdbarch = get_frame_arch (frame);
4354
  int raw_size = register_size (gdbarch, regno);
4355
 
4356
  if (raw_size == 8 && !mips2_fp_compat (frame))
4357
    {
4358
      /* We have a 64-bit value for this register, and we should use
4359
         all 64 bits.  */
4360
      if (!frame_register_read (frame, regno, rare_buffer))
4361
        error (_("can't read register %d (%s)"),
4362
               regno, gdbarch_register_name (gdbarch, regno));
4363
    }
4364
  else
4365
    {
4366
      int rawnum = regno % gdbarch_num_regs (gdbarch);
4367
 
4368
      if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
4369
        internal_error (__FILE__, __LINE__,
4370
                        _("mips_read_fp_register_double: bad access to "
4371
                        "odd-numbered FP register"));
4372
 
4373
      /* mips_read_fp_register_single will find the correct 32 bits from
4374
         each register.  */
4375
      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4376
        {
4377
          mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4378
          mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4379
        }
4380
      else
4381
        {
4382
          mips_read_fp_register_single (frame, regno, rare_buffer);
4383
          mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4384
        }
4385
    }
4386
}
4387
 
4388
static void
4389
mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4390
                        int regnum)
4391
{                               /* do values for FP (float) regs */
4392
  struct gdbarch *gdbarch = get_frame_arch (frame);
4393
  gdb_byte *raw_buffer;
4394
  double doub, flt1;    /* doubles extracted from raw hex data */
4395
  int inv1, inv2;
4396
 
4397
  raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0));
4398
 
4399
  fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
4400
  fprintf_filtered (file, "%*s",
4401
                    4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
4402
                    "");
4403
 
4404
  if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
4405
    {
4406
      struct value_print_options opts;
4407
 
4408
      /* 4-byte registers: Print hex and floating.  Also print even
4409
         numbered registers as doubles.  */
4410
      mips_read_fp_register_single (frame, regnum, raw_buffer);
4411
      flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1);
4412
 
4413
      get_formatted_print_options (&opts, 'x');
4414
      print_scalar_formatted (raw_buffer,
4415
                              builtin_type (gdbarch)->builtin_uint32,
4416
                              &opts, 'w', file);
4417
 
4418
      fprintf_filtered (file, " flt: ");
4419
      if (inv1)
4420
        fprintf_filtered (file, " <invalid float> ");
4421
      else
4422
        fprintf_filtered (file, "%-17.9g", flt1);
4423
 
4424
      if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
4425
        {
4426
          mips_read_fp_register_double (frame, regnum, raw_buffer);
4427
          doub = unpack_double (builtin_type (gdbarch)->builtin_double,
4428
                                raw_buffer, &inv2);
4429
 
4430
          fprintf_filtered (file, " dbl: ");
4431
          if (inv2)
4432
            fprintf_filtered (file, "<invalid double>");
4433
          else
4434
            fprintf_filtered (file, "%-24.17g", doub);
4435
        }
4436
    }
4437
  else
4438
    {
4439
      struct value_print_options opts;
4440
 
4441
      /* Eight byte registers: print each one as hex, float and double.  */
4442
      mips_read_fp_register_single (frame, regnum, raw_buffer);
4443
      flt1 = unpack_double (builtin_type (gdbarch)->builtin_float,
4444
                            raw_buffer, &inv1);
4445
 
4446
      mips_read_fp_register_double (frame, regnum, raw_buffer);
4447
      doub = unpack_double (builtin_type (gdbarch)->builtin_double,
4448
                            raw_buffer, &inv2);
4449
 
4450
      get_formatted_print_options (&opts, 'x');
4451
      print_scalar_formatted (raw_buffer,
4452
                              builtin_type (gdbarch)->builtin_uint64,
4453
                              &opts, 'g', file);
4454
 
4455
      fprintf_filtered (file, " flt: ");
4456
      if (inv1)
4457
        fprintf_filtered (file, "<invalid float>");
4458
      else
4459
        fprintf_filtered (file, "%-17.9g", flt1);
4460
 
4461
      fprintf_filtered (file, " dbl: ");
4462
      if (inv2)
4463
        fprintf_filtered (file, "<invalid double>");
4464
      else
4465
        fprintf_filtered (file, "%-24.17g", doub);
4466
    }
4467
}
4468
 
4469
static void
4470
mips_print_register (struct ui_file *file, struct frame_info *frame,
4471
                     int regnum)
4472
{
4473
  struct gdbarch *gdbarch = get_frame_arch (frame);
4474
  gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4475
  int offset;
4476
  struct value_print_options opts;
4477
 
4478
  if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4479
    {
4480
      mips_print_fp_register (file, frame, regnum);
4481
      return;
4482
    }
4483
 
4484
  /* Get the data in raw format.  */
4485
  if (!frame_register_read (frame, regnum, raw_buffer))
4486
    {
4487
      fprintf_filtered (file, "%s: [Invalid]",
4488
                        gdbarch_register_name (gdbarch, regnum));
4489
      return;
4490
    }
4491
 
4492
  fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
4493
 
4494
  /* The problem with printing numeric register names (r26, etc.) is that
4495
     the user can't use them on input.  Probably the best solution is to
4496
     fix it so that either the numeric or the funky (a2, etc.) names
4497
     are accepted on input.  */
4498
  if (regnum < MIPS_NUMREGS)
4499
    fprintf_filtered (file, "(r%d): ", regnum);
4500
  else
4501
    fprintf_filtered (file, ": ");
4502
 
4503
  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4504
    offset =
4505
      register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4506
  else
4507
    offset = 0;
4508
 
4509
  get_formatted_print_options (&opts, 'x');
4510
  print_scalar_formatted (raw_buffer + offset,
4511
                          register_type (gdbarch, regnum), &opts, 0,
4512
                          file);
4513
}
4514
 
4515
/* Replacement for generic do_registers_info.
4516
   Print regs in pretty columns.  */
4517
 
4518
static int
4519
print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4520
                       int regnum)
4521
{
4522
  fprintf_filtered (file, " ");
4523
  mips_print_fp_register (file, frame, regnum);
4524
  fprintf_filtered (file, "\n");
4525
  return regnum + 1;
4526
}
4527
 
4528
 
4529
/* Print a row's worth of GP (int) registers, with name labels above */
4530
 
4531
static int
4532
print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4533
                       int start_regnum)
4534
{
4535
  struct gdbarch *gdbarch = get_frame_arch (frame);
4536
  /* do values for GP (int) regs */
4537
  gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4538
  int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8);        /* display cols per row */
4539
  int col, byte;
4540
  int regnum;
4541
 
4542
  /* For GP registers, we print a separate row of names above the vals */
4543
  for (col = 0, regnum = start_regnum;
4544
       col < ncols && regnum < gdbarch_num_regs (gdbarch)
4545
                               + gdbarch_num_pseudo_regs (gdbarch);
4546
       regnum++)
4547
    {
4548
      if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4549
        continue;               /* unused register */
4550
      if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4551
          TYPE_CODE_FLT)
4552
        break;                  /* end the row: reached FP register */
4553
      /* Large registers are handled separately.  */
4554
      if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4555
        {
4556
          if (col > 0)
4557
            break;              /* End the row before this register.  */
4558
 
4559
          /* Print this register on a row by itself.  */
4560
          mips_print_register (file, frame, regnum);
4561
          fprintf_filtered (file, "\n");
4562
          return regnum + 1;
4563
        }
4564
      if (col == 0)
4565
        fprintf_filtered (file, "     ");
4566
      fprintf_filtered (file,
4567
                        mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
4568
                        gdbarch_register_name (gdbarch, regnum));
4569
      col++;
4570
    }
4571
 
4572
  if (col == 0)
4573
    return regnum;
4574
 
4575
  /* print the R0 to R31 names */
4576
  if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
4577
    fprintf_filtered (file, "\n R%-4d",
4578
                      start_regnum % gdbarch_num_regs (gdbarch));
4579
  else
4580
    fprintf_filtered (file, "\n      ");
4581
 
4582
  /* now print the values in hex, 4 or 8 to the row */
4583
  for (col = 0, regnum = start_regnum;
4584
       col < ncols && regnum < gdbarch_num_regs (gdbarch)
4585
                               + gdbarch_num_pseudo_regs (gdbarch);
4586
       regnum++)
4587
    {
4588
      if (*gdbarch_register_name (gdbarch, regnum) == '\0')
4589
        continue;               /* unused register */
4590
      if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4591
          TYPE_CODE_FLT)
4592
        break;                  /* end row: reached FP register */
4593
      if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
4594
        break;                  /* End row: large register.  */
4595
 
4596
      /* OK: get the data in raw format.  */
4597
      if (!frame_register_read (frame, regnum, raw_buffer))
4598
        error (_("can't read register %d (%s)"),
4599
               regnum, gdbarch_register_name (gdbarch, regnum));
4600
      /* pad small registers */
4601
      for (byte = 0;
4602
           byte < (mips_abi_regsize (gdbarch)
4603
                   - register_size (gdbarch, regnum)); byte++)
4604
        printf_filtered ("  ");
4605
      /* Now print the register value in hex, endian order. */
4606
      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4607
        for (byte =
4608
             register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
4609
             byte < register_size (gdbarch, regnum); byte++)
4610
          fprintf_filtered (file, "%02x", raw_buffer[byte]);
4611
      else
4612
        for (byte = register_size (gdbarch, regnum) - 1;
4613
             byte >= 0; byte--)
4614
          fprintf_filtered (file, "%02x", raw_buffer[byte]);
4615
      fprintf_filtered (file, " ");
4616
      col++;
4617
    }
4618
  if (col > 0)                   /* ie. if we actually printed anything... */
4619
    fprintf_filtered (file, "\n");
4620
 
4621
  return regnum;
4622
}
4623
 
4624
/* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4625
 
4626
static void
4627
mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4628
                           struct frame_info *frame, int regnum, int all)
4629
{
4630
  if (regnum != -1)             /* do one specified register */
4631
    {
4632
      gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
4633
      if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
4634
        error (_("Not a valid register for the current processor type"));
4635
 
4636
      mips_print_register (file, frame, regnum);
4637
      fprintf_filtered (file, "\n");
4638
    }
4639
  else
4640
    /* do all (or most) registers */
4641
    {
4642
      regnum = gdbarch_num_regs (gdbarch);
4643
      while (regnum < gdbarch_num_regs (gdbarch)
4644
                      + gdbarch_num_pseudo_regs (gdbarch))
4645
        {
4646
          if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4647
              TYPE_CODE_FLT)
4648
            {
4649
              if (all)          /* true for "INFO ALL-REGISTERS" command */
4650
                regnum = print_fp_register_row (file, frame, regnum);
4651
              else
4652
                regnum += MIPS_NUMREGS; /* skip floating point regs */
4653
            }
4654
          else
4655
            regnum = print_gp_register_row (file, frame, regnum);
4656
        }
4657
    }
4658
}
4659
 
4660
/* Is this a branch with a delay slot?  */
4661
 
4662
static int
4663
is_delayed (unsigned long insn)
4664
{
4665
  int i;
4666
  for (i = 0; i < NUMOPCODES; ++i)
4667
    if (mips_opcodes[i].pinfo != INSN_MACRO
4668
        && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4669
      break;
4670
  return (i < NUMOPCODES
4671
          && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4672
                                       | INSN_COND_BRANCH_DELAY
4673
                                       | INSN_COND_BRANCH_LIKELY)));
4674
}
4675
 
4676
static int
4677
mips_single_step_through_delay (struct gdbarch *gdbarch,
4678
                                struct frame_info *frame)
4679
{
4680
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4681
  CORE_ADDR pc = get_frame_pc (frame);
4682
  gdb_byte buf[MIPS_INSN32_SIZE];
4683
 
4684
  /* There is no branch delay slot on MIPS16.  */
4685
  if (mips_pc_is_mips16 (pc))
4686
    return 0;
4687
 
4688
  if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4))
4689
    return 0;
4690
 
4691
  if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4692
    /* If error reading memory, guess that it is not a delayed
4693
       branch.  */
4694
    return 0;
4695
  return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order));
4696
}
4697
 
4698
/* To skip prologues, I use this predicate.  Returns either PC itself
4699
   if the code at PC does not look like a function prologue; otherwise
4700
   returns an address that (if we're lucky) follows the prologue.  If
4701
   LENIENT, then we must skip everything which is involved in setting
4702
   up the frame (it's OK to skip more, just so long as we don't skip
4703
   anything which might clobber the registers which are being saved.
4704
   We must skip more in the case where part of the prologue is in the
4705
   delay slot of a non-prologue instruction).  */
4706
 
4707
static CORE_ADDR
4708
mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
4709
{
4710
  CORE_ADDR limit_pc;
4711
  CORE_ADDR func_addr;
4712
 
4713
  /* See if we can determine the end of the prologue via the symbol table.
4714
     If so, then return either PC, or the PC after the prologue, whichever
4715
     is greater.  */
4716
  if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4717
    {
4718
      CORE_ADDR post_prologue_pc
4719
        = skip_prologue_using_sal (gdbarch, func_addr);
4720
      if (post_prologue_pc != 0)
4721
        return max (pc, post_prologue_pc);
4722
    }
4723
 
4724
  /* Can't determine prologue from the symbol table, need to examine
4725
     instructions.  */
4726
 
4727
  /* Find an upper limit on the function prologue using the debug
4728
     information.  If the debug information could not be used to provide
4729
     that bound, then use an arbitrary large number as the upper bound.  */
4730
  limit_pc = skip_prologue_using_sal (gdbarch, pc);
4731
  if (limit_pc == 0)
4732
    limit_pc = pc + 100;          /* Magic.  */
4733
 
4734
  if (mips_pc_is_mips16 (pc))
4735
    return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
4736
  else
4737
    return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
4738
}
4739
 
4740
/* Check whether the PC is in a function epilogue (32-bit version).
4741
   This is a helper function for mips_in_function_epilogue_p.  */
4742
static int
4743
mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4744
{
4745
  CORE_ADDR func_addr = 0, func_end = 0;
4746
 
4747
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4748
    {
4749
      /* The MIPS epilogue is max. 12 bytes long.  */
4750
      CORE_ADDR addr = func_end - 12;
4751
 
4752
      if (addr < func_addr + 4)
4753
        addr = func_addr + 4;
4754
      if (pc < addr)
4755
        return 0;
4756
 
4757
      for (; pc < func_end; pc += MIPS_INSN32_SIZE)
4758
        {
4759
          unsigned long high_word;
4760
          unsigned long inst;
4761
 
4762
          inst = mips_fetch_instruction (gdbarch, pc);
4763
          high_word = (inst >> 16) & 0xffff;
4764
 
4765
          if (high_word != 0x27bd       /* addiu $sp,$sp,offset */
4766
              && high_word != 0x67bd    /* daddiu $sp,$sp,offset */
4767
              && inst != 0x03e00008     /* jr $ra */
4768
              && inst != 0x00000000)    /* nop */
4769
            return 0;
4770
        }
4771
 
4772
      return 1;
4773
    }
4774
 
4775
  return 0;
4776
}
4777
 
4778
/* Check whether the PC is in a function epilogue (16-bit version).
4779
   This is a helper function for mips_in_function_epilogue_p.  */
4780
static int
4781
mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4782
{
4783
  CORE_ADDR func_addr = 0, func_end = 0;
4784
 
4785
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
4786
    {
4787
      /* The MIPS epilogue is max. 12 bytes long.  */
4788
      CORE_ADDR addr = func_end - 12;
4789
 
4790
      if (addr < func_addr + 4)
4791
        addr = func_addr + 4;
4792
      if (pc < addr)
4793
        return 0;
4794
 
4795
      for (; pc < func_end; pc += MIPS_INSN16_SIZE)
4796
        {
4797
          unsigned short inst;
4798
 
4799
          inst = mips_fetch_instruction (gdbarch, pc);
4800
 
4801
          if ((inst & 0xf800) == 0xf000)        /* extend */
4802
            continue;
4803
 
4804
          if (inst != 0x6300            /* addiu $sp,offset */
4805
              && inst != 0xfb00         /* daddiu $sp,$sp,offset */
4806
              && inst != 0xe820         /* jr $ra */
4807
              && inst != 0xe8a0         /* jrc $ra */
4808
              && inst != 0x6500)        /* nop */
4809
            return 0;
4810
        }
4811
 
4812
      return 1;
4813
    }
4814
 
4815
  return 0;
4816
}
4817
 
4818
/* The epilogue is defined here as the area at the end of a function,
4819
   after an instruction which destroys the function's stack frame.  */
4820
static int
4821
mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
4822
{
4823
  if (mips_pc_is_mips16 (pc))
4824
    return mips16_in_function_epilogue_p (gdbarch, pc);
4825
  else
4826
    return mips32_in_function_epilogue_p (gdbarch, pc);
4827
}
4828
 
4829
/* Root of all "set mips "/"show mips " commands. This will eventually be
4830
   used for all MIPS-specific commands.  */
4831
 
4832
static void
4833
show_mips_command (char *args, int from_tty)
4834
{
4835
  help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4836
}
4837
 
4838
static void
4839
set_mips_command (char *args, int from_tty)
4840
{
4841
  printf_unfiltered
4842
    ("\"set mips\" must be followed by an appropriate subcommand.\n");
4843
  help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4844
}
4845
 
4846
/* Commands to show/set the MIPS FPU type.  */
4847
 
4848
static void
4849
show_mipsfpu_command (char *args, int from_tty)
4850
{
4851
  char *fpu;
4852
 
4853
  if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
4854
    {
4855
      printf_unfiltered
4856
        ("The MIPS floating-point coprocessor is unknown "
4857
         "because the current architecture is not MIPS.\n");
4858
      return;
4859
    }
4860
 
4861
  switch (MIPS_FPU_TYPE (target_gdbarch))
4862
    {
4863
    case MIPS_FPU_SINGLE:
4864
      fpu = "single-precision";
4865
      break;
4866
    case MIPS_FPU_DOUBLE:
4867
      fpu = "double-precision";
4868
      break;
4869
    case MIPS_FPU_NONE:
4870
      fpu = "absent (none)";
4871
      break;
4872
    default:
4873
      internal_error (__FILE__, __LINE__, _("bad switch"));
4874
    }
4875
  if (mips_fpu_type_auto)
4876
    printf_unfiltered
4877
      ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4878
       fpu);
4879
  else
4880
    printf_unfiltered
4881
      ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4882
}
4883
 
4884
 
4885
static void
4886
set_mipsfpu_command (char *args, int from_tty)
4887
{
4888
  printf_unfiltered
4889
    ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4890
  show_mipsfpu_command (args, from_tty);
4891
}
4892
 
4893
static void
4894
set_mipsfpu_single_command (char *args, int from_tty)
4895
{
4896
  struct gdbarch_info info;
4897
  gdbarch_info_init (&info);
4898
  mips_fpu_type = MIPS_FPU_SINGLE;
4899
  mips_fpu_type_auto = 0;
4900
  /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4901
     instead of relying on globals.  Doing that would let generic code
4902
     handle the search for this specific architecture.  */
4903
  if (!gdbarch_update_p (info))
4904
    internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4905
}
4906
 
4907
static void
4908
set_mipsfpu_double_command (char *args, int from_tty)
4909
{
4910
  struct gdbarch_info info;
4911
  gdbarch_info_init (&info);
4912
  mips_fpu_type = MIPS_FPU_DOUBLE;
4913
  mips_fpu_type_auto = 0;
4914
  /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4915
     instead of relying on globals.  Doing that would let generic code
4916
     handle the search for this specific architecture.  */
4917
  if (!gdbarch_update_p (info))
4918
    internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4919
}
4920
 
4921
static void
4922
set_mipsfpu_none_command (char *args, int from_tty)
4923
{
4924
  struct gdbarch_info info;
4925
  gdbarch_info_init (&info);
4926
  mips_fpu_type = MIPS_FPU_NONE;
4927
  mips_fpu_type_auto = 0;
4928
  /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4929
     instead of relying on globals.  Doing that would let generic code
4930
     handle the search for this specific architecture.  */
4931
  if (!gdbarch_update_p (info))
4932
    internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4933
}
4934
 
4935
static void
4936
set_mipsfpu_auto_command (char *args, int from_tty)
4937
{
4938
  mips_fpu_type_auto = 1;
4939
}
4940
 
4941
/* Attempt to identify the particular processor model by reading the
4942
   processor id.  NOTE: cagney/2003-11-15: Firstly it isn't clear that
4943
   the relevant processor still exists (it dates back to '94) and
4944
   secondly this is not the way to do this.  The processor type should
4945
   be set by forcing an architecture change.  */
4946
 
4947
void
4948
deprecated_mips_set_processor_regs_hack (void)
4949
{
4950
  struct regcache *regcache = get_current_regcache ();
4951
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
4952
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4953
  ULONGEST prid;
4954
 
4955
  regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid);
4956
  if ((prid & ~0xf) == 0x700)
4957
    tdep->mips_processor_reg_names = mips_r3041_reg_names;
4958
}
4959
 
4960
/* Just like reinit_frame_cache, but with the right arguments to be
4961
   callable as an sfunc.  */
4962
 
4963
static void
4964
reinit_frame_cache_sfunc (char *args, int from_tty,
4965
                          struct cmd_list_element *c)
4966
{
4967
  reinit_frame_cache ();
4968
}
4969
 
4970
static int
4971
gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4972
{
4973
  /* FIXME: cagney/2003-06-26: Is this even necessary?  The
4974
     disassembler needs to be able to locally determine the ISA, and
4975
     not rely on GDB.  Otherwize the stand-alone 'objdump -d' will not
4976
     work.  */
4977
  if (mips_pc_is_mips16 (memaddr))
4978
    info->mach = bfd_mach_mips16;
4979
 
4980
  /* Round down the instruction address to the appropriate boundary.  */
4981
  memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4982
 
4983
  /* Set the disassembler options.  */
4984
  if (!info->disassembler_options)
4985
    /* This string is not recognized explicitly by the disassembler,
4986
       but it tells the disassembler to not try to guess the ABI from
4987
       the bfd elf headers, such that, if the user overrides the ABI
4988
       of a program linked as NewABI, the disassembly will follow the
4989
       register naming conventions specified by the user.  */
4990
    info->disassembler_options = "gpr-names=32";
4991
 
4992
  /* Call the appropriate disassembler based on the target endian-ness.  */
4993
  if (info->endian == BFD_ENDIAN_BIG)
4994
    return print_insn_big_mips (memaddr, info);
4995
  else
4996
    return print_insn_little_mips (memaddr, info);
4997
}
4998
 
4999
static int
5000
gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
5001
{
5002
  /* Set up the disassembler info, so that we get the right
5003
     register names from libopcodes.  */
5004
  info->disassembler_options = "gpr-names=n32";
5005
  info->flavour = bfd_target_elf_flavour;
5006
 
5007
  return gdb_print_insn_mips (memaddr, info);
5008
}
5009
 
5010
static int
5011
gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
5012
{
5013
  /* Set up the disassembler info, so that we get the right
5014
     register names from libopcodes.  */
5015
  info->disassembler_options = "gpr-names=64";
5016
  info->flavour = bfd_target_elf_flavour;
5017
 
5018
  return gdb_print_insn_mips (memaddr, info);
5019
}
5020
 
5021
/* This function implements gdbarch_breakpoint_from_pc.  It uses the program
5022
   counter value to determine whether a 16- or 32-bit breakpoint should be used.
5023
   It returns a pointer to a string of bytes that encode a breakpoint
5024
   instruction, stores the length of the string to *lenptr, and adjusts pc (if
5025
   necessary) to point to the actual memory location where the breakpoint
5026
   should be inserted.  */
5027
 
5028
static const gdb_byte *
5029
mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
5030
{
5031
  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
5032
    {
5033
      if (mips_pc_is_mips16 (*pcptr))
5034
        {
5035
          static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5036
          *pcptr = unmake_mips16_addr (*pcptr);
5037
          *lenptr = sizeof (mips16_big_breakpoint);
5038
          return mips16_big_breakpoint;
5039
        }
5040
      else
5041
        {
5042
          /* The IDT board uses an unusual breakpoint value, and
5043
             sometimes gets confused when it sees the usual MIPS
5044
             breakpoint instruction.  */
5045
          static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
5046
          static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5047
          static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5048
          /* Likewise, IRIX appears to expect a different breakpoint,
5049
             although this is not apparent until you try to use pthreads. */
5050
          static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd };
5051
 
5052
          *lenptr = sizeof (big_breakpoint);
5053
 
5054
          if (strcmp (target_shortname, "mips") == 0)
5055
            return idt_big_breakpoint;
5056
          else if (strcmp (target_shortname, "ddb") == 0
5057
                   || strcmp (target_shortname, "pmon") == 0
5058
                   || strcmp (target_shortname, "lsi") == 0)
5059
            return pmon_big_breakpoint;
5060
          else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX)
5061
            return irix_big_breakpoint;
5062
          else
5063
            return big_breakpoint;
5064
        }
5065
    }
5066
  else
5067
    {
5068
      if (mips_pc_is_mips16 (*pcptr))
5069
        {
5070
          static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5071
          *pcptr = unmake_mips16_addr (*pcptr);
5072
          *lenptr = sizeof (mips16_little_breakpoint);
5073
          return mips16_little_breakpoint;
5074
        }
5075
      else
5076
        {
5077
          static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5078
          static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5079
          static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5080
 
5081
          *lenptr = sizeof (little_breakpoint);
5082
 
5083
          if (strcmp (target_shortname, "mips") == 0)
5084
            return idt_little_breakpoint;
5085
          else if (strcmp (target_shortname, "ddb") == 0
5086
                   || strcmp (target_shortname, "pmon") == 0
5087
                   || strcmp (target_shortname, "lsi") == 0)
5088
            return pmon_little_breakpoint;
5089
          else
5090
            return little_breakpoint;
5091
        }
5092
    }
5093
}
5094
 
5095
/* If PC is in a mips16 call or return stub, return the address of the target
5096
   PC, which is either the callee or the caller.  There are several
5097
   cases which must be handled:
5098
 
5099
   * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5100
   target PC is in $31 ($ra).
5101
   * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5102
   and the target PC is in $2.
5103
   * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5104
   before the jal instruction, this is effectively a call stub
5105
   and the the target PC is in $2.  Otherwise this is effectively
5106
   a return stub and the target PC is in $18.
5107
 
5108
   See the source code for the stubs in gcc/config/mips/mips16.S for
5109
   gory details.  */
5110
 
5111
static CORE_ADDR
5112
mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5113
{
5114
  struct gdbarch *gdbarch = get_frame_arch (frame);
5115
  char *name;
5116
  CORE_ADDR start_addr;
5117
 
5118
  /* Find the starting address and name of the function containing the PC.  */
5119
  if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5120
    return 0;
5121
 
5122
  /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5123
     target PC is in $31 ($ra).  */
5124
  if (strcmp (name, "__mips16_ret_sf") == 0
5125
      || strcmp (name, "__mips16_ret_df") == 0)
5126
    return get_frame_register_signed (frame, MIPS_RA_REGNUM);
5127
 
5128
  if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5129
    {
5130
      /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5131
         and the target PC is in $2.  */
5132
      if (name[19] >= '0' && name[19] <= '9')
5133
        return get_frame_register_signed (frame, 2);
5134
 
5135
      /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5136
         before the jal instruction, this is effectively a call stub
5137
         and the the target PC is in $2.  Otherwise this is effectively
5138
         a return stub and the target PC is in $18.  */
5139
      else if (name[19] == 's' || name[19] == 'd')
5140
        {
5141
          if (pc == start_addr)
5142
            {
5143
              /* Check if the target of the stub is a compiler-generated
5144
                 stub.  Such a stub for a function bar might have a name
5145
                 like __fn_stub_bar, and might look like this:
5146
                 mfc1    $4,$f13
5147
                 mfc1    $5,$f12
5148
                 mfc1    $6,$f15
5149
                 mfc1    $7,$f14
5150
                 la      $1,bar   (becomes a lui/addiu pair)
5151
                 jr      $1
5152
                 So scan down to the lui/addi and extract the target
5153
                 address from those two instructions.  */
5154
 
5155
              CORE_ADDR target_pc = get_frame_register_signed (frame, 2);
5156
              ULONGEST inst;
5157
              int i;
5158
 
5159
              /* See if the name of the target function is  __fn_stub_*.  */
5160
              if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5161
                  0)
5162
                return target_pc;
5163
              if (strncmp (name, "__fn_stub_", 10) != 0
5164
                  && strcmp (name, "etext") != 0
5165
                  && strcmp (name, "_etext") != 0)
5166
                return target_pc;
5167
 
5168
              /* Scan through this _fn_stub_ code for the lui/addiu pair.
5169
                 The limit on the search is arbitrarily set to 20
5170
                 instructions.  FIXME.  */
5171
              for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
5172
                {
5173
                  inst = mips_fetch_instruction (gdbarch, target_pc);
5174
                  if ((inst & 0xffff0000) == 0x3c010000)        /* lui $at */
5175
                    pc = (inst << 16) & 0xffff0000;     /* high word */
5176
                  else if ((inst & 0xffff0000) == 0x24210000)   /* addiu $at */
5177
                    return pc | (inst & 0xffff);        /* low word */
5178
                }
5179
 
5180
              /* Couldn't find the lui/addui pair, so return stub address.  */
5181
              return target_pc;
5182
            }
5183
          else
5184
            /* This is the 'return' part of a call stub.  The return
5185
               address is in $r18.  */
5186
            return get_frame_register_signed (frame, 18);
5187
        }
5188
    }
5189
  return 0;                      /* not a stub */
5190
}
5191
 
5192
/* If the current PC is the start of a non-PIC-to-PIC stub, return the
5193
   PC of the stub target.  The stub just loads $t9 and jumps to it,
5194
   so that $t9 has the correct value at function entry.  */
5195
 
5196
static CORE_ADDR
5197
mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5198
{
5199
  struct gdbarch *gdbarch = get_frame_arch (frame);
5200
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5201
  struct minimal_symbol *msym;
5202
  int i;
5203
  gdb_byte stub_code[16];
5204
  int32_t stub_words[4];
5205
 
5206
  /* The stub for foo is named ".pic.foo", and is either two
5207
     instructions inserted before foo or a three instruction sequence
5208
     which jumps to foo.  */
5209
  msym = lookup_minimal_symbol_by_pc (pc);
5210
  if (msym == NULL
5211
      || SYMBOL_VALUE_ADDRESS (msym) != pc
5212
      || SYMBOL_LINKAGE_NAME (msym) == NULL
5213
      || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0)
5214
    return 0;
5215
 
5216
  /* A two-instruction header.  */
5217
  if (MSYMBOL_SIZE (msym) == 8)
5218
    return pc + 8;
5219
 
5220
  /* A three-instruction (plus delay slot) trampoline.  */
5221
  if (MSYMBOL_SIZE (msym) == 16)
5222
    {
5223
      if (target_read_memory (pc, stub_code, 16) != 0)
5224
        return 0;
5225
      for (i = 0; i < 4; i++)
5226
        stub_words[i] = extract_unsigned_integer (stub_code + i * 4,
5227
                                                  4, byte_order);
5228
 
5229
      /* A stub contains these instructions:
5230
         lui    t9, %hi(target)
5231
         j      target
5232
          addiu t9, t9, %lo(target)
5233
         nop
5234
 
5235
         This works even for N64, since stubs are only generated with
5236
         -msym32.  */
5237
      if ((stub_words[0] & 0xffff0000U) == 0x3c190000
5238
          && (stub_words[1] & 0xfc000000U) == 0x08000000
5239
          && (stub_words[2] & 0xffff0000U) == 0x27390000
5240
          && stub_words[3] == 0x00000000)
5241
        return (((stub_words[0] & 0x0000ffff) << 16)
5242
                + (stub_words[2] & 0x0000ffff));
5243
    }
5244
 
5245
  /* Not a recognized stub.  */
5246
  return 0;
5247
}
5248
 
5249
static CORE_ADDR
5250
mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
5251
{
5252
  CORE_ADDR target_pc;
5253
 
5254
  target_pc = mips_skip_mips16_trampoline_code (frame, pc);
5255
  if (target_pc)
5256
    return target_pc;
5257
 
5258
  target_pc = find_solib_trampoline_target (frame, pc);
5259
  if (target_pc)
5260
    return target_pc;
5261
 
5262
  target_pc = mips_skip_pic_trampoline_code (frame, pc);
5263
  if (target_pc)
5264
    return target_pc;
5265
 
5266
  return 0;
5267
}
5268
 
5269
/* Convert a dbx stab register number (from `r' declaration) to a GDB
5270
   [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM.  */
5271
 
5272
static int
5273
mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
5274
{
5275
  int regnum;
5276
  if (num >= 0 && num < 32)
5277
    regnum = num;
5278
  else if (num >= 38 && num < 70)
5279
    regnum = num + mips_regnum (gdbarch)->fp0 - 38;
5280
  else if (num == 70)
5281
    regnum = mips_regnum (gdbarch)->hi;
5282
  else if (num == 71)
5283
    regnum = mips_regnum (gdbarch)->lo;
5284
  else
5285
    /* This will hopefully (eventually) provoke a warning.  Should
5286
       we be calling complaint() here?  */
5287
    return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5288
  return gdbarch_num_regs (gdbarch) + regnum;
5289
}
5290
 
5291
 
5292
/* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5293
   gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM.  */
5294
 
5295
static int
5296
mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num)
5297
{
5298
  int regnum;
5299
  if (num >= 0 && num < 32)
5300
    regnum = num;
5301
  else if (num >= 32 && num < 64)
5302
    regnum = num + mips_regnum (gdbarch)->fp0 - 32;
5303
  else if (num == 64)
5304
    regnum = mips_regnum (gdbarch)->hi;
5305
  else if (num == 65)
5306
    regnum = mips_regnum (gdbarch)->lo;
5307
  else
5308
    /* This will hopefully (eventually) provoke a warning.  Should we
5309
       be calling complaint() here?  */
5310
    return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
5311
  return gdbarch_num_regs (gdbarch) + regnum;
5312
}
5313
 
5314
static int
5315
mips_register_sim_regno (struct gdbarch *gdbarch, int regnum)
5316
{
5317
  /* Only makes sense to supply raw registers.  */
5318
  gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch));
5319
  /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5320
     decide if it is valid.  Should instead define a standard sim/gdb
5321
     register numbering scheme.  */
5322
  if (gdbarch_register_name (gdbarch,
5323
                             gdbarch_num_regs (gdbarch) + regnum) != NULL
5324
      && gdbarch_register_name (gdbarch,
5325
                                gdbarch_num_regs (gdbarch) + regnum)[0] != '\0')
5326
    return regnum;
5327
  else
5328
    return LEGACY_SIM_REGNO_IGNORE;
5329
}
5330
 
5331
 
5332
/* Convert an integer into an address.  Extracting the value signed
5333
   guarantees a correctly sign extended address.  */
5334
 
5335
static CORE_ADDR
5336
mips_integer_to_address (struct gdbarch *gdbarch,
5337
                         struct type *type, const gdb_byte *buf)
5338
{
5339
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5340
  return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
5341
}
5342
 
5343
/* Dummy virtual frame pointer method.  This is no more or less accurate
5344
   than most other architectures; we just need to be explicit about it,
5345
   because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5346
   an assertion failure.  */
5347
 
5348
static void
5349
mips_virtual_frame_pointer (struct gdbarch *gdbarch,
5350
                            CORE_ADDR pc, int *reg, LONGEST *offset)
5351
{
5352
  *reg = MIPS_SP_REGNUM;
5353
  *offset = 0;
5354
}
5355
 
5356
static void
5357
mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5358
{
5359
  enum mips_abi *abip = (enum mips_abi *) obj;
5360
  const char *name = bfd_get_section_name (abfd, sect);
5361
 
5362
  if (*abip != MIPS_ABI_UNKNOWN)
5363
    return;
5364
 
5365
  if (strncmp (name, ".mdebug.", 8) != 0)
5366
    return;
5367
 
5368
  if (strcmp (name, ".mdebug.abi32") == 0)
5369
    *abip = MIPS_ABI_O32;
5370
  else if (strcmp (name, ".mdebug.abiN32") == 0)
5371
    *abip = MIPS_ABI_N32;
5372
  else if (strcmp (name, ".mdebug.abi64") == 0)
5373
    *abip = MIPS_ABI_N64;
5374
  else if (strcmp (name, ".mdebug.abiO64") == 0)
5375
    *abip = MIPS_ABI_O64;
5376
  else if (strcmp (name, ".mdebug.eabi32") == 0)
5377
    *abip = MIPS_ABI_EABI32;
5378
  else if (strcmp (name, ".mdebug.eabi64") == 0)
5379
    *abip = MIPS_ABI_EABI64;
5380
  else
5381
    warning (_("unsupported ABI %s."), name + 8);
5382
}
5383
 
5384
static void
5385
mips_find_long_section (bfd *abfd, asection *sect, void *obj)
5386
{
5387
  int *lbp = (int *) obj;
5388
  const char *name = bfd_get_section_name (abfd, sect);
5389
 
5390
  if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
5391
    *lbp = 32;
5392
  else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
5393
    *lbp = 64;
5394
  else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
5395
    warning (_("unrecognized .gcc_compiled_longXX"));
5396
}
5397
 
5398
static enum mips_abi
5399
global_mips_abi (void)
5400
{
5401
  int i;
5402
 
5403
  for (i = 0; mips_abi_strings[i] != NULL; i++)
5404
    if (mips_abi_strings[i] == mips_abi_string)
5405
      return (enum mips_abi) i;
5406
 
5407
  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
5408
}
5409
 
5410
static void
5411
mips_register_g_packet_guesses (struct gdbarch *gdbarch)
5412
{
5413
  /* If the size matches the set of 32-bit or 64-bit integer registers,
5414
     assume that's what we've got.  */
5415
  register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32);
5416
  register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64);
5417
 
5418
  /* If the size matches the full set of registers GDB traditionally
5419
     knows about, including floating point, for either 32-bit or
5420
     64-bit, assume that's what we've got.  */
5421
  register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32);
5422
  register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64);
5423
 
5424
  /* Otherwise we don't have a useful guess.  */
5425
}
5426
 
5427
static struct value *
5428
value_of_mips_user_reg (struct frame_info *frame, const void *baton)
5429
{
5430
  const int *reg_p = baton;
5431
  return value_of_register (*reg_p, frame);
5432
}
5433
 
5434
static struct gdbarch *
5435
mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5436
{
5437
  struct gdbarch *gdbarch;
5438
  struct gdbarch_tdep *tdep;
5439
  int elf_flags;
5440
  enum mips_abi mips_abi, found_abi, wanted_abi;
5441
  int i, num_regs;
5442
  enum mips_fpu_type fpu_type;
5443
  struct tdesc_arch_data *tdesc_data = NULL;
5444
  int elf_fpu_type = 0;
5445
 
5446
  /* Check any target description for validity.  */
5447
  if (tdesc_has_registers (info.target_desc))
5448
    {
5449
      static const char *const mips_gprs[] = {
5450
        "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5451
        "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5452
        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5453
        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5454
      };
5455
      static const char *const mips_fprs[] = {
5456
        "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5457
        "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5458
        "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5459
        "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5460
      };
5461
 
5462
      const struct tdesc_feature *feature;
5463
      int valid_p;
5464
 
5465
      feature = tdesc_find_feature (info.target_desc,
5466
                                    "org.gnu.gdb.mips.cpu");
5467
      if (feature == NULL)
5468
        return NULL;
5469
 
5470
      tdesc_data = tdesc_data_alloc ();
5471
 
5472
      valid_p = 1;
5473
      for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
5474
        valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
5475
                                            mips_gprs[i]);
5476
 
5477
 
5478
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5479
                                          MIPS_EMBED_LO_REGNUM, "lo");
5480
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5481
                                          MIPS_EMBED_HI_REGNUM, "hi");
5482
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5483
                                          MIPS_EMBED_PC_REGNUM, "pc");
5484
 
5485
      if (!valid_p)
5486
        {
5487
          tdesc_data_cleanup (tdesc_data);
5488
          return NULL;
5489
        }
5490
 
5491
      feature = tdesc_find_feature (info.target_desc,
5492
                                    "org.gnu.gdb.mips.cp0");
5493
      if (feature == NULL)
5494
        {
5495
          tdesc_data_cleanup (tdesc_data);
5496
          return NULL;
5497
        }
5498
 
5499
      valid_p = 1;
5500
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5501
                                          MIPS_EMBED_BADVADDR_REGNUM,
5502
                                          "badvaddr");
5503
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5504
                                          MIPS_PS_REGNUM, "status");
5505
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5506
                                          MIPS_EMBED_CAUSE_REGNUM, "cause");
5507
 
5508
      if (!valid_p)
5509
        {
5510
          tdesc_data_cleanup (tdesc_data);
5511
          return NULL;
5512
        }
5513
 
5514
      /* FIXME drow/2007-05-17: The FPU should be optional.  The MIPS
5515
         backend is not prepared for that, though.  */
5516
      feature = tdesc_find_feature (info.target_desc,
5517
                                    "org.gnu.gdb.mips.fpu");
5518
      if (feature == NULL)
5519
        {
5520
          tdesc_data_cleanup (tdesc_data);
5521
          return NULL;
5522
        }
5523
 
5524
      valid_p = 1;
5525
      for (i = 0; i < 32; i++)
5526
        valid_p &= tdesc_numbered_register (feature, tdesc_data,
5527
                                            i + MIPS_EMBED_FP0_REGNUM,
5528
                                            mips_fprs[i]);
5529
 
5530
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5531
                                          MIPS_EMBED_FP0_REGNUM + 32, "fcsr");
5532
      valid_p &= tdesc_numbered_register (feature, tdesc_data,
5533
                                          MIPS_EMBED_FP0_REGNUM + 33, "fir");
5534
 
5535
      if (!valid_p)
5536
        {
5537
          tdesc_data_cleanup (tdesc_data);
5538
          return NULL;
5539
        }
5540
 
5541
      /* It would be nice to detect an attempt to use a 64-bit ABI
5542
         when only 32-bit registers are provided.  */
5543
    }
5544
 
5545
  /* First of all, extract the elf_flags, if available.  */
5546
  if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5547
    elf_flags = elf_elfheader (info.abfd)->e_flags;
5548
  else if (arches != NULL)
5549
    elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5550
  else
5551
    elf_flags = 0;
5552
  if (gdbarch_debug)
5553
    fprintf_unfiltered (gdb_stdlog,
5554
                        "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5555
 
5556
  /* Check ELF_FLAGS to see if it specifies the ABI being used.  */
5557
  switch ((elf_flags & EF_MIPS_ABI))
5558
    {
5559
    case E_MIPS_ABI_O32:
5560
      found_abi = MIPS_ABI_O32;
5561
      break;
5562
    case E_MIPS_ABI_O64:
5563
      found_abi = MIPS_ABI_O64;
5564
      break;
5565
    case E_MIPS_ABI_EABI32:
5566
      found_abi = MIPS_ABI_EABI32;
5567
      break;
5568
    case E_MIPS_ABI_EABI64:
5569
      found_abi = MIPS_ABI_EABI64;
5570
      break;
5571
    default:
5572
      if ((elf_flags & EF_MIPS_ABI2))
5573
        found_abi = MIPS_ABI_N32;
5574
      else
5575
        found_abi = MIPS_ABI_UNKNOWN;
5576
      break;
5577
    }
5578
 
5579
  /* GCC creates a pseudo-section whose name describes the ABI.  */
5580
  if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5581
    bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5582
 
5583
  /* If we have no useful BFD information, use the ABI from the last
5584
     MIPS architecture (if there is one).  */
5585
  if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5586
    found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5587
 
5588
  /* Try the architecture for any hint of the correct ABI.  */
5589
  if (found_abi == MIPS_ABI_UNKNOWN
5590
      && info.bfd_arch_info != NULL
5591
      && info.bfd_arch_info->arch == bfd_arch_mips)
5592
    {
5593
      switch (info.bfd_arch_info->mach)
5594
        {
5595
        case bfd_mach_mips3900:
5596
          found_abi = MIPS_ABI_EABI32;
5597
          break;
5598
        case bfd_mach_mips4100:
5599
        case bfd_mach_mips5000:
5600
          found_abi = MIPS_ABI_EABI64;
5601
          break;
5602
        case bfd_mach_mips8000:
5603
        case bfd_mach_mips10000:
5604
          /* On Irix, ELF64 executables use the N64 ABI.  The
5605
             pseudo-sections which describe the ABI aren't present
5606
             on IRIX.  (Even for executables created by gcc.)  */
5607
          if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5608
              && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5609
            found_abi = MIPS_ABI_N64;
5610
          else
5611
            found_abi = MIPS_ABI_N32;
5612
          break;
5613
        }
5614
    }
5615
 
5616
  /* Default 64-bit objects to N64 instead of O32.  */
5617
  if (found_abi == MIPS_ABI_UNKNOWN
5618
      && info.abfd != NULL
5619
      && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5620
      && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5621
    found_abi = MIPS_ABI_N64;
5622
 
5623
  if (gdbarch_debug)
5624
    fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5625
                        found_abi);
5626
 
5627
  /* What has the user specified from the command line?  */
5628
  wanted_abi = global_mips_abi ();
5629
  if (gdbarch_debug)
5630
    fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5631
                        wanted_abi);
5632
 
5633
  /* Now that we have found what the ABI for this binary would be,
5634
     check whether the user is overriding it.  */
5635
  if (wanted_abi != MIPS_ABI_UNKNOWN)
5636
    mips_abi = wanted_abi;
5637
  else if (found_abi != MIPS_ABI_UNKNOWN)
5638
    mips_abi = found_abi;
5639
  else
5640
    mips_abi = MIPS_ABI_O32;
5641
  if (gdbarch_debug)
5642
    fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5643
                        mips_abi);
5644
 
5645
  /* Also used when doing an architecture lookup.  */
5646
  if (gdbarch_debug)
5647
    fprintf_unfiltered (gdb_stdlog,
5648
                        "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5649
                        mips64_transfers_32bit_regs_p);
5650
 
5651
  /* Determine the MIPS FPU type.  */
5652
#ifdef HAVE_ELF
5653
  if (info.abfd
5654
      && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5655
    elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5656
                                             Tag_GNU_MIPS_ABI_FP);
5657
#endif /* HAVE_ELF */
5658
 
5659
  if (!mips_fpu_type_auto)
5660
    fpu_type = mips_fpu_type;
5661
  else if (elf_fpu_type != 0)
5662
    {
5663
      switch (elf_fpu_type)
5664
        {
5665
        case 1:
5666
          fpu_type = MIPS_FPU_DOUBLE;
5667
          break;
5668
        case 2:
5669
          fpu_type = MIPS_FPU_SINGLE;
5670
          break;
5671
        case 3:
5672
        default:
5673
          /* Soft float or unknown.  */
5674
          fpu_type = MIPS_FPU_NONE;
5675
          break;
5676
        }
5677
    }
5678
  else if (info.bfd_arch_info != NULL
5679
           && info.bfd_arch_info->arch == bfd_arch_mips)
5680
    switch (info.bfd_arch_info->mach)
5681
      {
5682
      case bfd_mach_mips3900:
5683
      case bfd_mach_mips4100:
5684
      case bfd_mach_mips4111:
5685
      case bfd_mach_mips4120:
5686
        fpu_type = MIPS_FPU_NONE;
5687
        break;
5688
      case bfd_mach_mips4650:
5689
        fpu_type = MIPS_FPU_SINGLE;
5690
        break;
5691
      default:
5692
        fpu_type = MIPS_FPU_DOUBLE;
5693
        break;
5694
      }
5695
  else if (arches != NULL)
5696
    fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5697
  else
5698
    fpu_type = MIPS_FPU_DOUBLE;
5699
  if (gdbarch_debug)
5700
    fprintf_unfiltered (gdb_stdlog,
5701
                        "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5702
 
5703
  /* Check for blatant incompatibilities.  */
5704
 
5705
  /* If we have only 32-bit registers, then we can't debug a 64-bit
5706
     ABI.  */
5707
  if (info.target_desc
5708
      && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
5709
      && mips_abi != MIPS_ABI_EABI32
5710
      && mips_abi != MIPS_ABI_O32)
5711
    {
5712
      if (tdesc_data != NULL)
5713
        tdesc_data_cleanup (tdesc_data);
5714
      return NULL;
5715
    }
5716
 
5717
  /* try to find a pre-existing architecture */
5718
  for (arches = gdbarch_list_lookup_by_info (arches, &info);
5719
       arches != NULL;
5720
       arches = gdbarch_list_lookup_by_info (arches->next, &info))
5721
    {
5722
      /* MIPS needs to be pedantic about which ABI the object is
5723
         using.  */
5724
      if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5725
        continue;
5726
      if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5727
        continue;
5728
      /* Need to be pedantic about which register virtual size is
5729
         used.  */
5730
      if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5731
          != mips64_transfers_32bit_regs_p)
5732
        continue;
5733
      /* Be pedantic about which FPU is selected.  */
5734
      if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5735
        continue;
5736
 
5737
      if (tdesc_data != NULL)
5738
        tdesc_data_cleanup (tdesc_data);
5739
      return arches->gdbarch;
5740
    }
5741
 
5742
  /* Need a new architecture.  Fill in a target specific vector.  */
5743
  tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5744
  gdbarch = gdbarch_alloc (&info, tdep);
5745
  tdep->elf_flags = elf_flags;
5746
  tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5747
  tdep->found_abi = found_abi;
5748
  tdep->mips_abi = mips_abi;
5749
  tdep->mips_fpu_type = fpu_type;
5750
  tdep->register_size_valid_p = 0;
5751
  tdep->register_size = 0;
5752
 
5753
  if (info.target_desc)
5754
    {
5755
      /* Some useful properties can be inferred from the target.  */
5756
      if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
5757
        {
5758
          tdep->register_size_valid_p = 1;
5759
          tdep->register_size = 4;
5760
        }
5761
      else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
5762
        {
5763
          tdep->register_size_valid_p = 1;
5764
          tdep->register_size = 8;
5765
        }
5766
    }
5767
 
5768
  /* Initially set everything according to the default ABI/ISA.  */
5769
  set_gdbarch_short_bit (gdbarch, 16);
5770
  set_gdbarch_int_bit (gdbarch, 32);
5771
  set_gdbarch_float_bit (gdbarch, 32);
5772
  set_gdbarch_double_bit (gdbarch, 64);
5773
  set_gdbarch_long_double_bit (gdbarch, 64);
5774
  set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5775
  set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5776
  set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5777
 
5778
  set_gdbarch_elf_make_msymbol_special (gdbarch,
5779
                                        mips_elf_make_msymbol_special);
5780
 
5781
  /* Fill in the OS dependant register numbers and names.  */
5782
  {
5783
    const char **reg_names;
5784
    struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5785
                                                         struct mips_regnum);
5786
    if (tdesc_has_registers (info.target_desc))
5787
      {
5788
        regnum->lo = MIPS_EMBED_LO_REGNUM;
5789
        regnum->hi = MIPS_EMBED_HI_REGNUM;
5790
        regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5791
        regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5792
        regnum->pc = MIPS_EMBED_PC_REGNUM;
5793
        regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5794
        regnum->fp_control_status = 70;
5795
        regnum->fp_implementation_revision = 71;
5796
        num_regs = MIPS_LAST_EMBED_REGNUM + 1;
5797
        reg_names = NULL;
5798
      }
5799
    else if (info.osabi == GDB_OSABI_IRIX)
5800
      {
5801
        regnum->fp0 = 32;
5802
        regnum->pc = 64;
5803
        regnum->cause = 65;
5804
        regnum->badvaddr = 66;
5805
        regnum->hi = 67;
5806
        regnum->lo = 68;
5807
        regnum->fp_control_status = 69;
5808
        regnum->fp_implementation_revision = 70;
5809
        num_regs = 71;
5810
        reg_names = mips_irix_reg_names;
5811
      }
5812
    else
5813
      {
5814
        regnum->lo = MIPS_EMBED_LO_REGNUM;
5815
        regnum->hi = MIPS_EMBED_HI_REGNUM;
5816
        regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5817
        regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5818
        regnum->pc = MIPS_EMBED_PC_REGNUM;
5819
        regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5820
        regnum->fp_control_status = 70;
5821
        regnum->fp_implementation_revision = 71;
5822
        num_regs = 90;
5823
        if (info.bfd_arch_info != NULL
5824
            && info.bfd_arch_info->mach == bfd_mach_mips3900)
5825
          reg_names = mips_tx39_reg_names;
5826
        else
5827
          reg_names = mips_generic_reg_names;
5828
      }
5829
    /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5830
       replaced by gdbarch_read_pc?  */
5831
    set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
5832
    set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
5833
    set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5834
    set_gdbarch_num_regs (gdbarch, num_regs);
5835
    set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5836
    set_gdbarch_register_name (gdbarch, mips_register_name);
5837
    set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer);
5838
    tdep->mips_processor_reg_names = reg_names;
5839
    tdep->regnum = regnum;
5840
  }
5841
 
5842
  switch (mips_abi)
5843
    {
5844
    case MIPS_ABI_O32:
5845
      set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5846
      set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5847
      tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5848
      tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5849
      tdep->default_mask_address_p = 0;
5850
      set_gdbarch_long_bit (gdbarch, 32);
5851
      set_gdbarch_ptr_bit (gdbarch, 32);
5852
      set_gdbarch_long_long_bit (gdbarch, 64);
5853
      break;
5854
    case MIPS_ABI_O64:
5855
      set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5856
      set_gdbarch_return_value (gdbarch, mips_o64_return_value);
5857
      tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
5858
      tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5859
      tdep->default_mask_address_p = 0;
5860
      set_gdbarch_long_bit (gdbarch, 32);
5861
      set_gdbarch_ptr_bit (gdbarch, 32);
5862
      set_gdbarch_long_long_bit (gdbarch, 64);
5863
      break;
5864
    case MIPS_ABI_EABI32:
5865
      set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5866
      set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5867
      tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5868
      tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5869
      tdep->default_mask_address_p = 0;
5870
      set_gdbarch_long_bit (gdbarch, 32);
5871
      set_gdbarch_ptr_bit (gdbarch, 32);
5872
      set_gdbarch_long_long_bit (gdbarch, 64);
5873
      break;
5874
    case MIPS_ABI_EABI64:
5875
      set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5876
      set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
5877
      tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5878
      tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5879
      tdep->default_mask_address_p = 0;
5880
      set_gdbarch_long_bit (gdbarch, 64);
5881
      set_gdbarch_ptr_bit (gdbarch, 64);
5882
      set_gdbarch_long_long_bit (gdbarch, 64);
5883
      break;
5884
    case MIPS_ABI_N32:
5885
      set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5886
      set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5887
      tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5888
      tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5889
      tdep->default_mask_address_p = 0;
5890
      set_gdbarch_long_bit (gdbarch, 32);
5891
      set_gdbarch_ptr_bit (gdbarch, 32);
5892
      set_gdbarch_long_long_bit (gdbarch, 64);
5893
      set_gdbarch_long_double_bit (gdbarch, 128);
5894
      set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5895
      break;
5896
    case MIPS_ABI_N64:
5897
      set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5898
      set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5899
      tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5900
      tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5901
      tdep->default_mask_address_p = 0;
5902
      set_gdbarch_long_bit (gdbarch, 64);
5903
      set_gdbarch_ptr_bit (gdbarch, 64);
5904
      set_gdbarch_long_long_bit (gdbarch, 64);
5905
      set_gdbarch_long_double_bit (gdbarch, 128);
5906
      set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
5907
      break;
5908
    default:
5909
      internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5910
    }
5911
 
5912
  /* GCC creates a pseudo-section whose name specifies the size of
5913
     longs, since -mlong32 or -mlong64 may be used independent of
5914
     other options.  How those options affect pointer sizes is ABI and
5915
     architecture dependent, so use them to override the default sizes
5916
     set by the ABI.  This table shows the relationship between ABI,
5917
     -mlongXX, and size of pointers:
5918
 
5919
     ABI                -mlongXX        ptr bits
5920
     ---                --------        --------
5921
     o32                32              32
5922
     o32                64              32
5923
     n32                32              32
5924
     n32                64              64
5925
     o64                32              32
5926
     o64                64              64
5927
     n64                32              32
5928
     n64                64              64
5929
     eabi32             32              32
5930
     eabi32             64              32
5931
     eabi64             32              32
5932
     eabi64             64              64
5933
 
5934
    Note that for o32 and eabi32, pointers are always 32 bits
5935
    regardless of any -mlongXX option.  For all others, pointers and
5936
    longs are the same, as set by -mlongXX or set by defaults.
5937
 */
5938
 
5939
  if (info.abfd != NULL)
5940
    {
5941
      int long_bit = 0;
5942
 
5943
      bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
5944
      if (long_bit)
5945
        {
5946
          set_gdbarch_long_bit (gdbarch, long_bit);
5947
          switch (mips_abi)
5948
            {
5949
            case MIPS_ABI_O32:
5950
            case MIPS_ABI_EABI32:
5951
              break;
5952
            case MIPS_ABI_N32:
5953
            case MIPS_ABI_O64:
5954
            case MIPS_ABI_N64:
5955
            case MIPS_ABI_EABI64:
5956
              set_gdbarch_ptr_bit (gdbarch, long_bit);
5957
              break;
5958
            default:
5959
              internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5960
            }
5961
        }
5962
    }
5963
 
5964
  /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5965
     that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5966
     comment:
5967
 
5968
     ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5969
     flag in object files because to do so would make it impossible to
5970
     link with libraries compiled without "-gp32".  This is
5971
     unnecessarily restrictive.
5972
 
5973
     We could solve this problem by adding "-gp32" multilibs to gcc,
5974
     but to set this flag before gcc is built with such multilibs will
5975
     break too many systems.''
5976
 
5977
     But even more unhelpfully, the default linker output target for
5978
     mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5979
     for 64-bit programs - you need to change the ABI to change this,
5980
     and not all gcc targets support that currently.  Therefore using
5981
     this flag to detect 32-bit mode would do the wrong thing given
5982
     the current gcc - it would make GDB treat these 64-bit programs
5983
     as 32-bit programs by default.  */
5984
 
5985
  set_gdbarch_read_pc (gdbarch, mips_read_pc);
5986
  set_gdbarch_write_pc (gdbarch, mips_write_pc);
5987
 
5988
  /* Add/remove bits from an address.  The MIPS needs be careful to
5989
     ensure that all 32 bit addresses are sign extended to 64 bits.  */
5990
  set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5991
 
5992
  /* Unwind the frame.  */
5993
  set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5994
  set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp);
5995
  set_gdbarch_dummy_id (gdbarch, mips_dummy_id);
5996
 
5997
  /* Map debug register numbers onto internal register numbers.  */
5998
  set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5999
  set_gdbarch_ecoff_reg_to_regnum (gdbarch,
6000
                                   mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6001
  set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
6002
                                    mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6003
  set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
6004
 
6005
  /* MIPS version of CALL_DUMMY */
6006
 
6007
  /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6008
     replaced by a command, and all targets will default to on stack
6009
     (regardless of the stack's execute status).  */
6010
  set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
6011
  set_gdbarch_frame_align (gdbarch, mips_frame_align);
6012
 
6013
  set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
6014
  set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
6015
  set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
6016
 
6017
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6018
  set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
6019
 
6020
  set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
6021
 
6022
  set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p);
6023
 
6024
  set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
6025
  set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
6026
  set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
6027
 
6028
  set_gdbarch_register_type (gdbarch, mips_register_type);
6029
 
6030
  set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
6031
 
6032
  if (mips_abi == MIPS_ABI_N32)
6033
    set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
6034
  else if (mips_abi == MIPS_ABI_N64)
6035
    set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
6036
  else
6037
    set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
6038
 
6039
  /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6040
     HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6041
     need to all be folded into the target vector.  Since they are
6042
     being used as guards for target_stopped_by_watchpoint, why not have
6043
     target_stopped_by_watchpoint return the type of watchpoint that the code
6044
     is sitting on?  */
6045
  set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6046
 
6047
  set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
6048
 
6049
  set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
6050
 
6051
  /* Virtual tables.  */
6052
  set_gdbarch_vbit_in_delta (gdbarch, 1);
6053
 
6054
  mips_register_g_packet_guesses (gdbarch);
6055
 
6056
  /* Hook in OS ABI-specific overrides, if they have been registered.  */
6057
  info.tdep_info = (void *) tdesc_data;
6058
  gdbarch_init_osabi (info, gdbarch);
6059
 
6060
  /* Unwind the frame.  */
6061
  dwarf2_append_unwinders (gdbarch);
6062
  frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind);
6063
  frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind);
6064
  frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind);
6065
  frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
6066
  frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
6067
  frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
6068
  frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
6069
 
6070
  if (tdesc_data)
6071
    {
6072
      set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
6073
      tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
6074
 
6075
      /* Override the normal target description methods to handle our
6076
         dual real and pseudo registers.  */
6077
      set_gdbarch_register_name (gdbarch, mips_register_name);
6078
      set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p);
6079
 
6080
      num_regs = gdbarch_num_regs (gdbarch);
6081
      set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
6082
      set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs);
6083
      set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
6084
    }
6085
 
6086
  /* Add ABI-specific aliases for the registers.  */
6087
  if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
6088
    for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++)
6089
      user_reg_add (gdbarch, mips_n32_n64_aliases[i].name,
6090
                    value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum);
6091
  else
6092
    for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++)
6093
      user_reg_add (gdbarch, mips_o32_aliases[i].name,
6094
                    value_of_mips_user_reg, &mips_o32_aliases[i].regnum);
6095
 
6096
  /* Add some other standard aliases.  */
6097
  for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++)
6098
    user_reg_add (gdbarch, mips_register_aliases[i].name,
6099
                  value_of_mips_user_reg, &mips_register_aliases[i].regnum);
6100
 
6101
  for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++)
6102
    user_reg_add (gdbarch, mips_numeric_register_aliases[i].name,
6103
                  value_of_mips_user_reg,
6104
                  &mips_numeric_register_aliases[i].regnum);
6105
 
6106
  return gdbarch;
6107
}
6108
 
6109
static void
6110
mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
6111
{
6112
  struct gdbarch_info info;
6113
 
6114
  /* Force the architecture to update, and (if it's a MIPS architecture)
6115
     mips_gdbarch_init will take care of the rest.  */
6116
  gdbarch_info_init (&info);
6117
  gdbarch_update_p (info);
6118
}
6119
 
6120
/* Print out which MIPS ABI is in use.  */
6121
 
6122
static void
6123
show_mips_abi (struct ui_file *file,
6124
               int from_tty,
6125
               struct cmd_list_element *ignored_cmd,
6126
               const char *ignored_value)
6127
{
6128
  if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips)
6129
    fprintf_filtered
6130
      (file,
6131
       "The MIPS ABI is unknown because the current architecture "
6132
       "is not MIPS.\n");
6133
  else
6134
    {
6135
      enum mips_abi global_abi = global_mips_abi ();
6136
      enum mips_abi actual_abi = mips_abi (target_gdbarch);
6137
      const char *actual_abi_str = mips_abi_strings[actual_abi];
6138
 
6139
      if (global_abi == MIPS_ABI_UNKNOWN)
6140
        fprintf_filtered
6141
          (file,
6142
           "The MIPS ABI is set automatically (currently \"%s\").\n",
6143
           actual_abi_str);
6144
      else if (global_abi == actual_abi)
6145
        fprintf_filtered
6146
          (file,
6147
           "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6148
           actual_abi_str);
6149
      else
6150
        {
6151
          /* Probably shouldn't happen...  */
6152
          fprintf_filtered
6153
            (file,
6154
             "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6155
             actual_abi_str, mips_abi_strings[global_abi]);
6156
        }
6157
    }
6158
}
6159
 
6160
static void
6161
mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6162
{
6163
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6164
  if (tdep != NULL)
6165
    {
6166
      int ef_mips_arch;
6167
      int ef_mips_32bitmode;
6168
      /* Determine the ISA.  */
6169
      switch (tdep->elf_flags & EF_MIPS_ARCH)
6170
        {
6171
        case E_MIPS_ARCH_1:
6172
          ef_mips_arch = 1;
6173
          break;
6174
        case E_MIPS_ARCH_2:
6175
          ef_mips_arch = 2;
6176
          break;
6177
        case E_MIPS_ARCH_3:
6178
          ef_mips_arch = 3;
6179
          break;
6180
        case E_MIPS_ARCH_4:
6181
          ef_mips_arch = 4;
6182
          break;
6183
        default:
6184
          ef_mips_arch = 0;
6185
          break;
6186
        }
6187
      /* Determine the size of a pointer.  */
6188
      ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6189
      fprintf_unfiltered (file,
6190
                          "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6191
                          tdep->elf_flags);
6192
      fprintf_unfiltered (file,
6193
                          "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6194
                          ef_mips_32bitmode);
6195
      fprintf_unfiltered (file,
6196
                          "mips_dump_tdep: ef_mips_arch = %d\n",
6197
                          ef_mips_arch);
6198
      fprintf_unfiltered (file,
6199
                          "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6200
                          tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
6201
      fprintf_unfiltered (file,
6202
                          "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6203
                          mips_mask_address_p (tdep),
6204
                          tdep->default_mask_address_p);
6205
    }
6206
  fprintf_unfiltered (file,
6207
                      "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6208
                      MIPS_DEFAULT_FPU_TYPE,
6209
                      (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6210
                       : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6211
                       : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6212
                       : "???"));
6213
  fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
6214
                      MIPS_EABI (gdbarch));
6215
  fprintf_unfiltered (file,
6216
                      "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6217
                      MIPS_FPU_TYPE (gdbarch),
6218
                      (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none"
6219
                       : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single"
6220
                       : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double"
6221
                       : "???"));
6222
}
6223
 
6224
extern initialize_file_ftype _initialize_mips_tdep;     /* -Wmissing-prototypes */
6225
 
6226
void
6227
_initialize_mips_tdep (void)
6228
{
6229
  static struct cmd_list_element *mipsfpulist = NULL;
6230
  struct cmd_list_element *c;
6231
 
6232
  mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6233
  if (MIPS_ABI_LAST + 1
6234
      != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6235
    internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
6236
 
6237
  gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6238
 
6239
  mips_pdr_data = register_objfile_data ();
6240
 
6241
  /* Create feature sets with the appropriate properties.  The values
6242
     are not important.  */
6243
  mips_tdesc_gp32 = allocate_target_description ();
6244
  set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
6245
 
6246
  mips_tdesc_gp64 = allocate_target_description ();
6247
  set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
6248
 
6249
  /* Add root prefix command for all "set mips"/"show mips" commands */
6250
  add_prefix_cmd ("mips", no_class, set_mips_command,
6251
                  _("Various MIPS specific commands."),
6252
                  &setmipscmdlist, "set mips ", 0, &setlist);
6253
 
6254
  add_prefix_cmd ("mips", no_class, show_mips_command,
6255
                  _("Various MIPS specific commands."),
6256
                  &showmipscmdlist, "show mips ", 0, &showlist);
6257
 
6258
  /* Allow the user to override the ABI. */
6259
  add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
6260
                        &mips_abi_string, _("\
6261
Set the MIPS ABI used by this program."), _("\
6262
Show the MIPS ABI used by this program."), _("\
6263
This option can be set to one of:\n\
6264
  auto  - the default ABI associated with the current binary\n\
6265
  o32\n\
6266
  o64\n\
6267
  n32\n\
6268
  n64\n\
6269
  eabi32\n\
6270
  eabi64"),
6271
                        mips_abi_update,
6272
                        show_mips_abi,
6273
                        &setmipscmdlist, &showmipscmdlist);
6274
 
6275
  /* Let the user turn off floating point and set the fence post for
6276
     heuristic_proc_start.  */
6277
 
6278
  add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6279
                  _("Set use of MIPS floating-point coprocessor."),
6280
                  &mipsfpulist, "set mipsfpu ", 0, &setlist);
6281
  add_cmd ("single", class_support, set_mipsfpu_single_command,
6282
           _("Select single-precision MIPS floating-point coprocessor."),
6283
           &mipsfpulist);
6284
  add_cmd ("double", class_support, set_mipsfpu_double_command,
6285
           _("Select double-precision MIPS floating-point coprocessor."),
6286
           &mipsfpulist);
6287
  add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6288
  add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6289
  add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6290
  add_cmd ("none", class_support, set_mipsfpu_none_command,
6291
           _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
6292
  add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6293
  add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6294
  add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6295
  add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6296
           _("Select MIPS floating-point coprocessor automatically."),
6297
           &mipsfpulist);
6298
  add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6299
           _("Show current use of MIPS floating-point coprocessor target."),
6300
           &showlist);
6301
 
6302
  /* We really would like to have both "0" and "unlimited" work, but
6303
     command.c doesn't deal with that.  So make it a var_zinteger
6304
     because the user can always use "999999" or some such for unlimited.  */
6305
  add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
6306
                            &heuristic_fence_post, _("\
6307
Set the distance searched for the start of a function."), _("\
6308
Show the distance searched for the start of a function."), _("\
6309
If you are debugging a stripped executable, GDB needs to search through the\n\
6310
program for the start of a function.  This command sets the distance of the\n\
6311
search.  The only need to set it is when debugging a stripped executable."),
6312
                            reinit_frame_cache_sfunc,
6313
                            NULL, /* FIXME: i18n: The distance searched for the start of a function is %s.  */
6314
                            &setlist, &showlist);
6315
 
6316
  /* Allow the user to control whether the upper bits of 64-bit
6317
     addresses should be zeroed.  */
6318
  add_setshow_auto_boolean_cmd ("mask-address", no_class,
6319
                                &mask_address_var, _("\
6320
Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6321
Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6322
Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6323
allow GDB to determine the correct value."),
6324
                                NULL, show_mask_address,
6325
                                &setmipscmdlist, &showmipscmdlist);
6326
 
6327
  /* Allow the user to control the size of 32 bit registers within the
6328
     raw remote packet.  */
6329
  add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6330
                           &mips64_transfers_32bit_regs_p, _("\
6331
Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6332
                           _("\
6333
Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6334
                           _("\
6335
Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6336
that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6337
64 bits for others.  Use \"off\" to disable compatibility mode"),
6338
                           set_mips64_transfers_32bit_regs,
6339
                           NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.  */
6340
                           &setlist, &showlist);
6341
 
6342
  /* Debug this files internals. */
6343
  add_setshow_zinteger_cmd ("mips", class_maintenance,
6344
                            &mips_debug, _("\
6345
Set mips debugging."), _("\
6346
Show mips debugging."), _("\
6347
When non-zero, mips specific debugging is enabled."),
6348
                            NULL,
6349
                            NULL, /* FIXME: i18n: Mips debugging is currently %s.  */
6350
                            &setdebuglist, &showdebuglist);
6351
}

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