URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [gdb/] [regformats/] [rs6000/] [powerpc-cell32l.dat] - Blame information for rev 833

Line No.	Rev	Author	Line
1	227	jeremybenn	`# DO NOT EDIT: generated from rs6000/powerpc-cell32l.xml`
2			`name:powerpc_cell32l`
3			`xmltarget:powerpc-cell32l.xml`
4			`expedite:r1,pc,r0,orig_r3,r4`
5			`32:r0`
6			`32:r1`
7			`32:r2`
8			`32:r3`
9			`32:r4`
10			`32:r5`
11			`32:r6`
12			`32:r7`
13			`32:r8`
14			`32:r9`
15			`32:r10`
16			`32:r11`
17			`32:r12`
18			`32:r13`
19			`32:r14`
20			`32:r15`
21			`32:r16`
22			`32:r17`
23			`32:r18`
24			`32:r19`
25			`32:r20`
26			`32:r21`
27			`32:r22`
28			`32:r23`
29			`32:r24`
30			`32:r25`
31			`32:r26`
32			`32:r27`
33			`32:r28`
34			`32:r29`
35			`32:r30`
36			`32:r31`
37			`64:f0`
38			`64:f1`
39			`64:f2`
40			`64:f3`
41			`64:f4`
42			`64:f5`
43			`64:f6`
44			`64:f7`
45			`64:f8`
46			`64:f9`
47			`64:f10`
48			`64:f11`
49			`64:f12`
50			`64:f13`
51			`64:f14`
52			`64:f15`
53			`64:f16`
54			`64:f17`
55			`64:f18`
56			`64:f19`
57			`64:f20`
58			`64:f21`
59			`64:f22`
60			`64:f23`
61			`64:f24`
62			`64:f25`
63			`64:f26`
64			`64:f27`
65			`64:f28`
66			`64:f29`
67			`64:f30`
68			`64:f31`
69			`32:pc`
70			`32:msr`
71			`32:cr`
72			`32:lr`
73			`32:ctr`
74			`32:xer`
75			`32:fpscr`
76			`32:orig_r3`
77			`32:trap`
78			`128:vr0`
79			`128:vr1`
80			`128:vr2`
81			`128:vr3`
82			`128:vr4`
83			`128:vr5`
84			`128:vr6`
85			`128:vr7`
86			`128:vr8`
87			`128:vr9`
88			`128:vr10`
89			`128:vr11`
90			`128:vr12`
91			`128:vr13`
92			`128:vr14`
93			`128:vr15`
94			`128:vr16`
95			`128:vr17`
96			`128:vr18`
97			`128:vr19`
98			`128:vr20`
99			`128:vr21`
100			`128:vr22`
101			`128:vr23`
102			`128:vr24`
103			`128:vr25`
104			`128:vr26`
105			`128:vr27`
106			`128:vr28`
107			`128:vr29`
108			`128:vr30`
109			`128:vr31`
110			`32:vscr`
111			`32:vrsave`