Subversion Repositories openrisc

# Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.

#

# This program is free software; you can redistribute it and/or modify

# it under the terms of the GNU General Public License as published by

# the Free Software Foundation; either version 3 of the License, or

# (at your option) any later version.

#

# This program is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

# GNU General Public License for more details.

#

# You should have received a copy of the GNU General Public License

# along with this program.  If not, see .

#

# Tests for Powerpc AltiVec register setting and fetching

if $tracelevel then {

    strace $tracelevel

}

#

# Test the use of VSX registers, for Powerpc.

#

set prms_id 0

set bug_id 0

if {![istarget "powerpc*"] || [skip_vsx_tests]} then {

    verbose "Skipping vsx register tests."

    return

}

set testfile "vsx-regs"

set binfile ${objdir}/${subdir}/${testfile}

set srcfile ${testfile}.c

set compile_flags {debug nowarnings quiet}

if [get_compiler_info $binfile] {

    warning "get_compiler failed"

    return -1

}

if [test_compiler_info gcc*] {

    set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"

} elseif [test_compiler_info xlc*] {

    set compile_flags "$compile_flags additional_flags=-qaltivec"

} else {

    warning "unknown compiler"

    return -1

}

if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {

     untested vsx-regs.exp

     return -1

}

gdb_start

gdb_reinitialize_dir $srcdir/$subdir

gdb_load ${binfile}

# Run to `main' where we begin our tests.

if ![runto_main] then {

    gdb_suppress_tests

}

# Data sets used throughout the test

set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."

set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."

set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."

set float_register ".raw 0xdeadbeefdeadbeef."

# First run the F0~F31/VS0~VS31 tests

# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.

for {set i 0} {$i < 32} {incr i 1} {

    send_gdb "set \$f$i = 1\.3"

}

for {set i 0} {$i < 32} {incr i 1} {

    gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"

}

# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.

for {set i 0} {$i < 32} {incr i 1} {

        for {set j 0} {$j < 4} {incr j 1} {

           send_gdb "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"

        }

}

for {set i 0} {$i < 32} {incr i 1} {

    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"

}

for {set i 0} {$i < 32} {incr i 1} {

    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"

}

# Now run the VR0~VR31/VS32~VS63 tests

# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.

for {set i 0} {$i < 32} {incr i 1} {

        for {set j 0} {$j < 4} {incr j 1} {

           send_gdb "set \$vr$i.v4_int32\[$j\] = 1"

        }

}

for {set i 32} {$i < 64} {incr i 1} {

    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"

}

# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.

for {set i 32} {$i < 64} {incr i 1} {

        for {set j 0} {$j < 4} {incr j 1} {

           send_gdb "set \$vs$i.v4_int32\[$j\] = 1"

        }

}

for {set i 0} {$i < 32} {incr i 1} {

    gdb_test "info reg vr$i" "vr$i.*$vector_register3" "info reg vr$i"

}

set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]

set core_supported 0

gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \

        "Save a VSX-enabled corefile" \

{

  -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" {

    pass "Save a VSX-enabled corefile"

    global core_supported

    set core_supported 1

  }

  -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" {

    unsupported "Save a VSX-enabled corefile"

    global core_supported

    set core_supported 0

  }

}

if {!$core_supported} {

  return -1

}

gdb_exit

gdb_start

gdb_reinitialize_dir $srcdir/$subdir

gdb_load ${binfile}

gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \

        "re-load generated corefile" \

{

    -re ".* is not a core dump:.*$gdb_prompt $" {

        fail "re-load generated corefile (bad file format)"

        # No use proceeding from here.

        return;

    }

    -re ".*: No such file or directory.*$gdb_prompt $" {

        fail "re-load generated corefile (file not found)"

        # No use proceeding from here.

        return;

    }

    -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" {

        fail "re-load generated corefile (incomplete note section)"

    }

    -re "Core was generated by .*$gdb_prompt $" {

        pass "re-load generated corefile"

    }

    -re ".*$gdb_prompt $" {

        fail "re-load generated corefile"

    }

    timeout {

        fail "re-load generated corefile (timeout)"

    }

}

for {set i 0} {$i < 32} {incr i 1} {

    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file"

}

for {set i 32} {$i < 64} {incr i 1} {

    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file"

}